CN107452810B - Metal oxide thin film transistor and preparation method thereof - Google Patents

Metal oxide thin film transistor and preparation method thereof Download PDF

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CN107452810B
CN107452810B CN201710858499.3A CN201710858499A CN107452810B CN 107452810 B CN107452810 B CN 107452810B CN 201710858499 A CN201710858499 A CN 201710858499A CN 107452810 B CN107452810 B CN 107452810B
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metal oxide
channel layer
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gate electrode
thin film
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CN107452810A (en
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徐睿
金尚忠
黄杰
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Zhejiang Zhiduo Network Technology Co ltd
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China Jiliang University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Thin Film Transistor (AREA)

Abstract

The invention discloses a metal oxide thin film transistor and a preparation method thereof. The source electrode is arranged on the substrate, the metal oxide channel layer is arranged on the source electrode, the drain electrode is arranged on the metal oxide channel layer, the gate electrode and the gate dielectric layer are formed by in-situ oxidation, the gate electrode is embedded in the gate dielectric layer, and the gate dielectric layer is embedded in the metal oxide channel layer; the metal oxide thin film transistor is provided with not less than 2 gate dielectric layers, and the gate dielectric layers are mutually separated to form a multi-conductive channel with carriers from bottom to top. The metal oxide thin film transistor provided by the invention can break through the limitation of the traditional process on the size on one hand, and can realize high output current under low working voltage due to the parallel connection of multiple channels.

Description

Metal oxide thin film transistor and preparation method thereof
Technical Field
The invention relates to the technical field of Thin Film Transistors (TFT), in particular to a metal oxide thin film transistor and a preparation method thereof.
Background
The thin film transistor is used as a core element of the flat panel display, and forms a driving circuit together with the storage capacitor, thereby playing an important role in realizing large-area, high-definition and high-frame-frequency display. Currently, the most mature and widely used process is the amorphous silicon (a-Si) TFT, but with a low field effect mobility (<1 cm2Vs), it is difficult to drive the active display device, and the a-Si photostability is poor. Although the polysilicon TFT device has higher mobility and better stability, the device has poor uniformity and high preparation cost, and is incompatible with the conventional IC process. Organic Thin Film Transistors (OTFTs) also suffer from low mobility and poor stability.
In recent years, metal oxide TFTs represented by IZO and IGZO are gradually replacing conventional a-Si TFTs and becoming core elements of new-generation flat panel display devices due to their advantages of high mobility, high visible light transmittance, low-temperature fabrication, low cost, good uniformity, and compatibility with IC processes. Nomura et al in 2004NatureThe periodical publication reports TFT [ alpha ] -IGZO with amorphous indium gallium zinc oxide (a-IGZO) as the channel layerNature,2004,432(7061):488-492]Saturation mobility of the device: (μ) Is 6-9 cm2/Vs。
However, with the rapid development of integrated circuits and the demand for higher and higher resolution of displays, the electrical performance of thin film transistors is further improved, and the device size is further reduced. For conventional lateral TFT devices, this is typically achieved by reducing the channel length. However, due to the limitation of the processing technology, generally in the micron scale, further size reduction will greatly increase the manufacturing cost, and the short channel effect becomes a great obstacle to further reducing the conventional device.
The TFT with a vertical structure is adopted, and the thickness of the channel layer clamped between the source electrode and the drain electrode is the length of the channel layer, so that the limitation of the traditional processing technology can be broken through, the channel length can be reduced to submicron or even nanometer level in principle, the working current, the response speed and the on-off ratio of the device are greatly improved, and the starting voltage and the power consumption of the device can be reduced. Y, Yang, etc. [ solution ]Appl. Phys. Lett.,2007,91:092911],[Appl. Phys. Lett.,2004,85(21):5084-5086]Organic transistors (VOFETs) of a vertically stacked structure are reported. However, the source electrode of the transistor is located between the dielectric layer and the channel layer, and the thickness of the source electrode and the interface of the source electrode and the channel layer affect the collection and transmission of carriers. To date, reports of metal oxide TFTs based on a vertical structure have not been found.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide a metal oxide thin film transistor and a preparation method thereof, which can break through the limitation of the traditional process on the size on one hand and can realize high output current under low working voltage on the other hand.
According to an aspect of the present invention, a metal oxide thin film transistor is provided. The metal oxide channel layer is arranged on the substrate and is used for forming a gate dielectric layer; the source electrode is arranged on the substrate, the metal oxide channel layer is arranged on the source electrode, the drain electrode is arranged on the metal oxide channel layer, the gate electrode and the gate dielectric layer are embedded in the metal oxide channel layer, and the gate electrode is embedded in the gate dielectric layer; the metal oxide thin film transistor is provided with not less than 2 gate dielectric layers, and the gate dielectric layers are mutually separated to form a multi-conductive channel with carriers from bottom to top.
Wherein the metal oxide thin film transistor is vertically buriedAnd (5) a gate structure. The metal oxide channel layer is In2O3IZO, IGZO, HIZO or IGO. In the metal oxide channel layer composition2O3Is more than 50 percent. The gate electrode is one of Al, Hf, Ti, Zr, Mg, Mn, Cr and Zn or an alloy formed by the Al, Hf, Ti, Zr, Mg, Mn, Cr and Zn. The gate electrode is at least 2 metal electrodes which are formed by using a certain pattern mask and are separated from each other. The gate dielectric layer is an oxide layer with the thickness less than 10nm formed by in-situ oxidation of the gate electrode under the condition of a conventional thermal annealing process. The gate dielectric layer can also be a dual gate dielectric layer consisting of an insulating layer deposited on the gate electrode and an oxide layer formed by in-situ oxidation. The source electrode and the drain electrode are ITO, high-conductivity IZO, Mo, Cu or Ag.
According to another aspect of the present invention, there is provided a method of manufacturing a metal oxide thin film transistor, the method comprising: forming a source electrode on a substrate; forming a first metal oxide channel layer on the source electrode; using a certain pattern mask on the first metal oxide channel layer, and then depositing metal to form not less than 2 gate electrodes which are mutually separated; continuously growing the metal oxide which is the same as the first metal oxide channel layer on the first metal oxide channel layer and the gate electrode to form a complete metal oxide channel layer, and embedding the gate electrode in the middle of the metal oxide channel layer; forming a drain electrode on the metal oxide channel layer; and annealing the whole structure at 200 ℃ in an atmospheric environment for 10 hours to enable in-situ oxidation reaction to occur between the gate electrode and the metal oxide channel layer, so that a gate dielectric layer with the thickness of less than 10nm grows around the gate electrode. The grid dielectric layers are mutually separated to form a multi-conductive channel with carriers from bottom to top.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention adopts the vertical buried gate structure, which can break through the limitation of the traditional process on the size on one hand, and can avoid the collection and transmission of the source electrode of the VOFET structure to the current carrier on the other hand. 2. The gate electrode and the gate dielectric layer are formed by in-situ oxidation under the conventional thermal annealing condition, so that the manufacturing process can be simplified, and the manufacturing cost can be saved. 3. The invention has a multi-channel structure, and can realize high output current under low working voltage under the premise of not changing the length of the channel due to the parallel connection of the multiple channels.
Drawings
The invention is further described below with reference to the accompanying drawings;
fig. 1 is a cross-sectional view of a metal oxide thin film transistor provided in the present invention;
fig. 2a to fig. 2e are cross-sectional views illustrating a method for fabricating a metal oxide thin film transistor according to the present invention;
FIG. 3 is a cross-sectional view of a metal oxide thin film transistor with dual dielectric layers according to the present invention;
FIG. 4 is a pattern mask on a metal oxide channel layer prior to deposition of a gate electrode of an embodiment;
FIG. 5 is a top view of an embodiment metal oxide thin film transistor;
FIG. 6 is a TEM cross-sectional view of an example metal in-situ oxide layer;
FIG. 7 is a C-V curve of an example in-situ metal oxide layer;
FIG. 8 is a graph of the output characteristics of an example metal oxide thin film transistor;
fig. 9 is a transfer characteristic curve of a metal oxide thin film transistor of an example.
Description of the symbols:
1. a substrate; 2. a source electrode; 3. a first metal oxide channel layer; 4. a gate electrode; 5. a gate dielectric layer; 6. a second metal oxide channel layer; 7. a drain electrode; 8. the direction of carrier motion; 9. a second insulating layer.
Detailed Description
Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that well-known processes are not described in detail herein in order to highlight the focus of the present invention. Also, the drawings are in a very simplified form and are not to scale. It is intended that the embodiments of the invention be considered as a complete disclosure of the invention, rather than as a limiting example.
Metal oxide thin film transistor
Referring to fig. 1, the substrate 1, the source electrode 2, the first metal oxide channel layer 3, the gate electrode 4, the gate dielectric layer 5, the second metal oxide channel layer 6, and the drain electrode 7 are sequentially included from bottom to top. The substrate 1 is made of glass, quartz, silicon wafer, or the like. The material of the source electrode 2 is, for example, conductive ITO, high conductivity IZO, Mo, Cu or Ag metal. The material of the first metal oxide channel layer 3 is, for example, In2O3IZO, IGZO, HIZO or IGO, wherein In is contained In the metal oxide component2O3Is more than 50% by mass, and the carrier concentrationnAt 1015~1018/cm3Within the range. At least 2 gate electrodes 4 spaced apart from each other are formed on the first metal oxide channel layer 3 using a patterned mask, and the gate electrodes 4 are made of, for example, one of Al, Hf, Ti, Zr, Mg, Mn, Cr, Zn, or an alloy thereof. The second metal oxide channel layer 6 is formed on the first metal oxide channel layer 3 and the gate electrode 4 with the gate electrode 4 embedded in the middle of the channel layers. Wherein the first metal oxide channel layer 3 and the second metal oxide channel layer 6 use the same process parameters, the first metal oxide channel layer 3 and the second metal oxide channel layer 6 constitute a complete metal oxide channel layer. The drain electrode 7 is made of, for example, conductive ITO, high conductivity IZO, Mo, Cu, or Ag metal. Wherein the gate dielectric layer 5 is an in-situ oxide layer with a thickness of less than 10nm, such as Al, formed by thermal annealing at 200 deg.C for 10 hr2O3、HfO2、TiO2、ZrO2、MgO、MnO、Cr2O3ZnO, or combinations thereof. The gate dielectric layer can also be a double gate dielectric layer, i.e. SiO is deposited on the gate electrode 42、Si3N4The second insulating layer 9 and the in-situ oxide layer form a dual gate dielectric layer, as shown in fig. 3. The gate dielectric layer 5 and the gate dielectric layer 5 are mutually separated to form a multi-conductive channel with carriers from bottom to top.
Example 1
Referring to FIG. 1, wherein the substrate 1 is SiO with a thickness of 500nm2 A source electrode 2 and a drain electrode 7 of 100nm thick high conductivity IZO film, n-1020/cm3. The first metal oxide channel layer 3 and the second metal oxide channel layer 6 are 100nm thick semiconductor IZO thin films n-1017/cm3. In the high-conductivity IZO film and the semiconductor IZO film2O3The mass percentage of (A) is 90%. The gate electrode 4 is 20nm thick Al metal. The Al metal was formed on the first semiconductor IZO film using the mask of the pattern of fig. 4, the pattern consisted of 10 stripes, the width of the stripe was 500nm, the length was 10 μm, and the distance between the stripes was also 500 nm. The gate dielectric layer 5 is Al formed by in-situ oxidation of Al metal and semiconductor IZO film under the atmospheric environment of 200 ℃ for 10 hours2O3Oxide layer to embed Al metal in Al2O3Intermediate oxide layer, Al2O3The oxide layer is embedded in the middle of the semiconductor IZO film. Al (Al)2O3Oxide layer and Al2O3The oxide layers are mutually separated to form a multi-conductive channel from bottom to top of a current carrier. FIG. 5 is a top view of an exemplary metal oxide thin film transistor with an active area of 100μm2(ii) a FIG. 6 shows example Al2O3TEM cross-sectional view of the oxide layer; FIG. 7 shows example Al2O3Of oxide layersC-VCurve of which Al2O3Capacitance of oxide layerCIs 1.2 mu F/cm2Calculating to obtain the dielectric constant of 6.85; FIG. 8 is a graph showing the output characteristics of an IZO thin film transistor of an embodiment in which the drain voltage V is lowerDChanging from 0V to 5V, gate electrode voltage VGFrom 0V to 4V, it can be seen that IZO TFT of the present embodiment has good saturation characteristics, and is at VGHigh output current of 4.5mA can be obtained under lower voltage of = 4V; FIG. 9 is a graph showing the transfer characteristics of an IZO thin film transistor of the present embodiment, which shows that an IZO TFT of the present embodiment has a high output current, and the current on-off ratio is larger than 106。
Preparation method of metal oxide thin film transistor
Hereinafter, a method of fabricating a metal oxide thin film transistor will be described, and a device structure of the metal oxide thin film transistor will be more apparent from the following description of the fabrication method. Fig. 2a to fig. 2e are cross-sectional views illustrating a method for fabricating a metal oxide thin film transistor according to the present invention. First a substrate 1 is provided. The substrate 1 is made of, for example, glass, quartz, or a silicon wafer, and is cleaned to obtain a good growth surface. Next, a source electrode 2 is formed on the substrate 1, and the material of the source electrode 2 is, for example, conductive ITO, high-conductivity IZO, Mo, Cu or Ag metal. A first metal oxide channel layer 3 is then formed on the formed source electrode 2. The material of the first metal oxide channel layer 3 is, for example, In2O3IZO, IGZO, HIZO or IGO, wherein In is contained In the metal oxide component2O3Is more than 50% by mass, and the carrier concentrationnAt 1015~1018/cm3Within the range. The first metal oxide channel layer 3 may be obtained by controlling the oxygen partial pressure in the reaction process by a magnetron sputtering method. The first metal oxide channel layer 3 is then patterned using a patterned mask, such as an electron beam lithography technique, a photolithographic lift-off technique, or a nanoimprint technique. At least 2 strip-shaped gate electrodes 4 spaced apart from each other are formed on the patterned first metal oxide channel layer 3, and the material of the gate electrodes 4 is, for example, one of Al, Hf, Ti, Zr, Mg, Mn, Cr, and Zn or an alloy formed therebetween. Next, a second metal oxide channel layer 6 is grown on the first metal oxide channel layer 3 and the gate electrode 4, embedding the gate electrode 4 in the middle of the channel layers. Wherein the first metal oxide channel layer 3 and the second metal oxide channel layer 6 use the same process parameters, the first metal oxide channel layer 3 and the second metal oxide channel layer 6 constitute a complete metal oxide channel layer. Then, a drain electrode 7 is formed on the complete metal oxide channel layer, and the material of the drain electrode 7 is, for example, conductive ITO, high conductivity IZO, Mo, Cu or Ag metal. Finally, the structure shown in FIG. 2e is thermally annealed at 200 deg.C for 10 hours in an atmosphere to cause oxidation reaction between the gate electrode 4 and the metal oxide channel layer, thereby forming a layer with a thickness of less than 10nm around the gate electrode 4In-situ oxidation of the gate dielectric layer 5, e.g. Al2O3、HfO2、TiO2、ZrO2、MgO、MnO、Cr2O3ZnO, or combinations thereof, as shown in figure 1. The invention also makes it possible to deposit SiO on the gate electrode 42、Si3N4The second insulating layer 9 and the in-situ oxide layer form a dual gate dielectric layer, which can regulate the dielectric constant and reduce the leakage current, as shown in fig. 3. The formed gate dielectric layer 5 and the gate dielectric layer 5 are mutually separated to form a multi-conductive channel with current carriers from bottom to top.
Example 2
Referring to fig. 2a to 2e, the present invention provides a method for manufacturing an IZO thin film transistor. Growing SiO with a thickness of 500nm2the/Si substrate is subjected to ultrasonic cleaning by acetone, ethanol, deionized water and the like, and is dried by nitrogen to be used as the substrate 1. Then, high-conductivity IZO (n-10) with the thickness of 100nm is formed on the substrate by a direct current magnetron sputtering method20/cm3) As the source electrode 2, the sputtering power density was 0.88W/cm2The voltage is 400V, and the working gas is pure argon. Then, a first semiconductor IZO film (n-10) with a thickness of 100nm is deposited on the formed source electrode 217/cm3) As the first metal oxide channel layer 3, the sputtering power density was 0.22W/cm2Voltage of 280V, pressure of 0.266Pa, oxygen partial pressure O2/Ar+O2The content was 14%. The pattern shown in fig. 4 was formed on the first semiconductor IZO film by electron beam lithography, and the pattern consisted of 10 stripes, the width of which was 500nm and the length of which was 10 μm, and the distance between the stripes was also 500 nm. Then, Al metal with the thickness of 20nm is deposited on the patterned first semiconductor IZO film by direct current magnetron sputtering to form a gate electrode 4, and the sputtering power is 0.22W/cm2The voltage is 400V, and the working gas is pure argon. Then, a second semiconductor IZO film with the thickness of 100nm is deposited on the first semiconductor IZO film and the Al metal by using the same process parameters as the first semiconductor IZO film, the first semiconductor IZO film and the second semiconductor IZO film form a complete IZO channel layer, and the Al metal is embedded in the middle. Then, forming a high conductive IZO (n-10) with a thickness of 100nm on the complete IZO channel layer20/cm3) As the drain electrode 7, the drain electrode 7 has exactly the same process parameters as the source electrode 2. Finally, the whole structure is thermally annealed for 10 hours at the atmospheric environment of 200 ℃ so as to generate Al + In between the Al metal and the IZO channel layer2O3=Al2O3+In，∆G= –752.6 KJ/mol (T=200 ℃) to form in-situ Al with a thickness of less than 5nm around the Al metal2O3The oxide layer serves as a gate dielectric layer 5. Al (Al)2O3Oxide layer and Al2O3The oxide layers are mutually separated to form 10 conductive channels from bottom to top of the current carrier.
The above-mentioned embodiments are merely preferred embodiments, which are not intended to limit the present invention, and the scope of the present invention is defined by the appended claims. Any simple modifications and equivalent changes made to the above embodiments in accordance with the technical spirit of the present invention fall within the scope of the present invention.

Claims (6)

1. A metal oxide thin film transistor comprises a substrate, a source electrode, a metal oxide channel layer, a gate electrode, a gate dielectric layer and a drain electrode; the method is characterized in that: the source electrode is arranged on the substrate, the metal oxide channel layer is arranged on the source electrode, the drain electrode is arranged on the metal oxide channel layer, the gate electrode and the gate dielectric layer are embedded in the metal oxide channel layer, and the gate electrode is embedded in the gate dielectric layer; the metal oxide thin film transistor is provided with not less than 2 gate dielectric layers, and the gate dielectric layers are mutually separated to form a multi-conductive channel with carriers from bottom to top;
the gate dielectric layer is a double gate dielectric layer, and the double gate dielectric layer consists of an insulating layer deposited above a gate electrode and an oxide layer formed by in-situ oxidation; the oxide layer formed by in-situ oxidation is positioned between the gate electrode and the metal oxide channel layer; the in-situ oxidation is an oxidation reaction occurring between the materials of the gate electrode and the metal oxide channel layer; the thickness of an oxide layer formed by in-situ oxidation of the gate electrode is less than 10 nm;
the metal oxide channel layerIs indium oxide In2O3Indium zinc oxide IZO, indium gallium zinc oxide IGZO, indium hafnium zinc oxide HIZO, or indium gallium oxide IGO.
2. The metal oxide thin film transistor of claim 1, wherein In is In said metal oxide channel layer composition2O3Is more than 50 percent.
3. The metal oxide thin film transistor of claim 1, wherein the gate electrode is one of Al, Hf, Ti, Zr, Mg, Mn, Cr, Zn or an alloy thereof.
4. A metal oxide thin film transistor according to claim 1, wherein the gate electrode is not less than 2 metal electrodes spaced apart from each other formed using a patterned mask.
5. The metal oxide thin film transistor of claim 1, wherein the source and drain electrodes are Indium Tin Oxide (ITO), high conductivity IZO, Mo, Cu, or Ag.
6. A method for preparing a metal oxide thin film transistor, the method comprising: forming a source electrode on a substrate; forming a first metal oxide channel layer on the source electrode; using a certain pattern mask on the first metal oxide channel layer, and then depositing metal to form not less than 2 gate electrodes which are mutually separated; depositing an insulating layer on the gate electrode; continuously growing the same metal oxide as the first metal oxide channel layer on the first metal oxide channel layer, the gate electrode and the insulating layer to form a complete metal oxide channel layer, and embedding the gate electrode in the middle of the metal oxide channel layer; forming a drain electrode on the metal oxide channel layer; the whole structure is annealed for 10 hours at 200 ℃ in an atmospheric environment, so that in-situ oxidation reaction is generated between the gate electrode and the metal oxide channel layer, a gate dielectric layer with the thickness of less than 10nm grows around the gate electrode, and the gate dielectric layer are mutually separated to form a multi-conductive channel with current carriers from bottom to top.
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JP2008300419A (en) * 2007-05-29 2008-12-11 Nec Corp Organic thin-film transistor

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Top-Gated Indium–Zinc–Oxide Thin-Film Transistors With In Situ Al2O3/HfO2 Gate Oxide;Yang Song et al;《IEEE ELECTRON DEVICE LETTERS》;20141231;第35卷(第12期);第1251页第1段-1253页最后1段 *

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