CN107634009A - A kind of GaN MOS HEMT devices and preparation method thereof - Google Patents

A kind of GaN MOS HEMT devices and preparation method thereof Download PDF

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Publication number
CN107634009A
CN107634009A CN201710682055.9A CN201710682055A CN107634009A CN 107634009 A CN107634009 A CN 107634009A CN 201710682055 A CN201710682055 A CN 201710682055A CN 107634009 A CN107634009 A CN 107634009A
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layer
gan
gate
sio
dielectric layer
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孙辉
刘美华
林信南
陈东敏
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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Abstract

The invention discloses a kind of GaN MOS HEMT devices and preparation method thereof, this method is：The cvd nitride silicon dielectric layer on GaN epitaxy piece, protection materials surface；Etching forms gate window；The deposit polycrystalline silicon layer in silicon nitride medium layer surface and gate window；Polysilicon layer is oxidized to SiO2Gate dielectric layer；Etching forms ohmic contact hole；Deposit ohmic metal simultaneously forms source-drain electrode；Deposit gate electrode metal simultaneously forms gate electrode；Surface protection simultaneously opens electrode (PAD) window.The preparation technology and condition of the present invention is compatible with Si CMOS technologies, and its technique is simple, workable, has coordinated the contradiction between device performance and process complexity well, and the volume production for GaN MOS HEMT devices provides possibility；The gate dielectric layer of the present invention uses SiO2Film is formed, and its compactness is good, and trapped charge is few, can both reduce the gate leakage current of GaN device, and and can makes GaN device have preferable dynamic characteristic, can be obviously improved the performance and stability of device.

Description

A kind of GaN MOS-HEMT devices and preparation method thereof
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of GaN MOS-HEMT devices and preparation method thereof.
Background technology
Representative of the GaN and GaN system materials as third generation semiconductor material with wide forbidden band, because it has energy gap big (3.4eV), electron saturation velocities height (2 × 107Cm/s), breakdown electric field height (1 × 1010-3×1010V/cm), thermal conductivity is high, resistance to The features such as corrosion and radiation resistance are excellent, it is considered to be research shortwave opto-electronic device and high voltagehigh frequency rate high power device Optimal material.GaN/AlGaN heterojunction structures are wherein most attractive device architectures, because the pole between GaN and AlGaN Strong piezoelectricity and spontaneous polarization effect so that the two of high electron concentration and high electron mobility are formed between GaN/AlGaN Dimensional electron gas (2-DEG), electron concentration is up to 1012-1013cm-2, electron mobility may be up to 2000cm2/V；This causes GaN/ AlGaN HEMTs (HEMT) turn into the mostly important type of device in gallium nitride device field, are equal to Status of the MOSFET in Si devices.
Because the unmatched defect of the intrinsic lattice of GaN/AlGaN heterojunction structures, causes crystalline epitaxial of poor quality, device is deposited In serious gate leakage current, this feature causes the device based on GaN/AlGaN heterojunction structures can not play its maximum Advantage.For this problem, the scheme generally used at present is design MIS (nitride) or MOS (oxide) structure HEMT, i.e. in one layer of fine and close dielectric layer of superficial growth of AlGaN epitaxial materials, on the one hand solve electric leakage of the grid well Flow the problem of big；On the other hand, good dielectric layer improves significantly to the current collapse effect of HEMT device generally existing. And the design for MIS or MOS is broadly divided into 2 big camps, the first kind is using oxide as gate dielectric layer, such as is passed through ALD method grows the breakdown characteristics of densification and the dielectric material that dielectric constant is larger, such as Al2O3, Hf2O3Deng this scheme can To obtain horizontal first-class device property, but it is tentative strong, and volume production is difficult；Second class be using nitride as gate dielectric layer, It is the platform based on Si process compatibles mostly, this scheme generally grows and GaN device extension sheet material by the way of by LPCVD Nitride similar in matter (such as) Si3N4Static and dynamic c haracteristics as dielectric layer, but the device of this scheme manufacture are not so good as The result of the first kind.Based on above contradiction, industrial circle and academia need badly seek a kind of MIS that can combine respective advantage or MOS HEMT preparation scheme.
The content of the invention
The application provides a kind of GaN MOS-HEMT devices and preparation method thereof, to solve GaN HEMT in the prior art The problem of device grid leakage current is big.
In order to solve the above problems, technical scheme is as follows：
A kind of preparation method of GaN MOS-HEMT devices, including：
Prepare GaN epitaxy piece；
SiO is formed on the upper surface of GaN epitaxy piece2Gate dielectric layer；
Etch SiO2Inside gate dielectric layer to GaN epitaxy piece outer surface or GaN epitaxy piece, ohmic contact hole is formed；
The deposit ohmic metal in ohmic contact hole；
The graphical simultaneously high annealing of ohmic metal, to form source-drain electrode；
In SiO2Preset to be formed on gate dielectric layer and gate electrode is made on the region of grid.
A kind of GaN MOS-HEMT devices, including：
GaN epitaxy piece；
To realize the gate electrode of electric insulation, source electrode and drain electrode, the source electrode and drain electrode are distinguished for isolation distribution It is formed at GaN epitaxy piece upper surface；
The SiO being formed between GaN epitaxy piece upper surface, gate electrode, source electrode and drain electrode2Gate dielectric layer.
Also include being formed at GaN epitaxy piece upper surface and SiO2Silicon nitride medium layer between gate dielectric layer, silicon nitride are situated between Correspond to the position of gate electrode on matter layer formed with gate window, SiO2Gate dielectric layer on silicon nitride medium layer by passing through grid window Mouth is extended to inside gate window, to be contacted with GaN epitaxy piece；
Gate electrode is located at SiO2Gate dielectric layer upper surface.
Beneficial effects of the present invention are：
The present invention proposes a kind of GaN MOS-HEMT devices and preparation method thereof, and the preparation method focuses on using heat Aoxidize the fine and close SiO formed2As the gate dielectric layer of GaN HEMT devices, to solve, grid leakage current is big, current collapse is imitated Answer the problem of serious；In gate deposition polysilicon layer, afterwards by high-temperature oxydation, polysilicon layer is oxidized into first for this method The good SiO of compactness2Film, as gate dielectric layer；The GaN MOS-HEMT devices prepared by the oxidation technology of polysilicon, SiO2Forming thin film quality is good, and film forming is uniform, improves GaN HEMT device static and dynamic c haracteristics；Meanwhile system of the invention Preparation Method is compatible with existing Si CMOS technologies platform, is very suitable for GaN MOS-HEMT volume production.
Brief description of the drawings
Fig. 1 is the flow signal corresponding to a kind of GaN MOS-HEMT device preparation methods provided in an embodiment of the present invention Figure；
Fig. 2-Fig. 9 is that the device architecture in a kind of GaN MOS-HEMT device fabrication process provided in an embodiment of the present invention shows It is intended to.
In figure, 101- silicon substrates, 102-GaN cushions, 103- two-dimensional electron gas thin layers, 104-AlGaN barrier layers, 105- GaN cap, 106- silicon nitride medium layers, 107-SiO2Gate dielectric layer, 108- protective layers, 109- polysilicon layers.
Embodiment
In order that the object, technical solutions and advantages of the present invention are clearer, the present invention is made below in conjunction with accompanying drawing into One step it is described in detail, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole implementation Example.Based on the embodiment in the present invention, what those of ordinary skill in the art were obtained under the premise of creative work is not made All other embodiment, belongs to the scope of protection of the invention.
Currently, the related mechanism of most of GaN device research and enterprise are all with existing 4-8inch Si CMOS technologies The Process ba- sis that platform is researched and developed as GaN HEMT devices, so as to develop the cmos compatible GaN HEMT techniques of Si.So not only The time of platform building and adjustment can be saved, R＆D costs can also be greatlyd save.But based on the GaN of this platform manufacture The static and dynamic c haracteristics of HEMT device are poor.In research process, the characteristics of discovery because of LPCVD depositional modes itself, make Obtain in gate dielectric layer and substantial amounts of movable charge be present, such case causes the static and dynamic c haracteristics of GaN HEMT devices to be deteriorated. If reducing the movable charge in gate dielectric layer, the static of GaN HEMT devices can be improved to a certain extent and dynamic is special Property.Therefore, inventor expects the SiO using thermal oxide2As gate dielectric layer.The SiO that thermal oxide is formed2, can because of itself characteristic Dynamic electric charge is less, therefore uses SiO2The gate leakage current of GaN device can be both reduced as gate dielectric layer, and can makes GaN devices Part has preferable dynamic characteristic.
During embodiment is improved, inventor has been found that directly grows SiO on GaN epitaxy piece2Layer, at present may be used Only PECVD and LPCVD etc. the modes used, its SiO formed2Hole in layer can be relatively more, more crisp, are unfavorable for excellent The formation of good gate dielectric layer.Therefore inventor is using the first position growing polycrystalline silicon layer in gate dielectric layer, then by polysilicon layer High-temperature oxydation forms SiO2Layer.
In addition, if the growing polycrystalline silicon layer directly on GaN epitaxy piece, subsequent high temperature will be to the surface of GaN epitaxy piece Cause to damage, therefore in improved embodiment, silicon nitride medium layer is formed in the cap layers of GaN epitaxy piece using elder generation, then Gate window is opened on silicon nitride medium layer, finally the growing polycrystalline silicon layer on silicon nitride medium layer and in gate window.
Embodiment 1：
Referring to Fig. 1, a kind of preparation method of GaN MOS-HEMT devices,
Step 201. prepares GaN epitaxy piece first：The structure of GaN epitaxy piece 201 is as shown in Fig. 2 in silicon substrate 101 GaN cushions 102 (GaN buffer layer), AlGaN potential barrier 104 are sequentially formed with (Silicon substrate) (AlGaN barrier layer), GaN cap 105 (GaN cap layer), GaN cap 105 (GaN cap layer) conduct The upper surface of GaN epitaxy piece；GaN cushions 102 (GaN buffer layer) and (AlGaN of AlGaN potential barrier 104 Barrier layer) between formed two-dimensional electron gas thin layer 103 (2-DEG).GaN cap 105 (GaN cap layer) is used for Passivating material surface, current collapse effect can be significantly inhibited and reduce surface leakage.GaN epitaxy piece can be used for The epitaxial wafer of GaN device is made, can also make to be formed through suitable technique on common Silicon Wafer.
GaN epitaxy piece is cleaned, after cleaning, also specifically includes following steps：
Step 202. is using LPCVD techniques (Low Pressure Chemical Vapor Deposition) at GaN cap 105 (GaN cap layer) Upper deposit thickness is the 30nm (Si of silicon nitride medium layer 1063N4Passivation), referring to Fig. 2.In a further embodiment, (the Si of silicon nitride medium layer 106 of deposition3N4Passivation thickness) can also be adjusted as needed.
Step 203. is using RIE techniques (reactive ion etching method) in (Si of silicon nitride medium layer 1063N4Passivation) Upper etching forms gate window, and gate window etching depth is to the upper surface of the GaN epitaxy piece, referring to Fig. 3.In other reality Apply in example, the etching depth of gate window can also be to inside GaN epitaxy piece, such as etching depth reaches AlGaN potential barrier 104 (AlGaN barrier layer) is internal or gets rid of whole AlGaN potential barrier 104 (AlGaN barrier layer) and arrives Up to GaN cushions 102 (GaN buffer layer) upper surface.
Step 204. is being etched with the Si of gate window using LPCVD techniques (low-pressure chemical vapour deposition technique)3N4Medium Deposit polycrystalline silicon layer 109 (Poly Si) on layer 106, polysilicon layer 109 (Poly Si) is by under 625 DEG C of environment temperatures SiH4Thermally decompose and deposit what is formed, referring to Fig. 4.
Step 205. is by polysilicon layer 109 (Poly Si) in O2:H2=1:1 atmosphere, aoxidize 1 hour at 750 DEG C, to complete It is oxidized to SiO2Gate dielectric layer 107, referring to Fig. 5.The SiO formed by high temperature2Film, compactness is good, internal charge trap density Small, film hole is few, is especially suitable for doing gate dielectric layer；SiO2Gate dielectric layer 107 can significantly lift the grid-control ability of device, subtract The leak channel of few grid, strengthen the stability and repeatability of grid；In addition, because trapped charge is few, the dynamic electric of device Resistance can substantially reduce, and current collapse effect is inhibited.
In addition, it will be appreciated by those skilled in the art that in other embodiments, the oxidation of polysilicon layer 109 (Poly Si) Process conditions can also be adjusted as needed, such as adjustment oxygen content, oxidizing temperature or oxidization time, for example, 700 45-75 minutes are aoxidized at DEG C -800 DEG C, as long as polysilicon is completely oxidized into SiO in a word2.
Step 206. forms ohmic contact hole using RIE techniques (reactive ion etching method) etching, and etching stopping is in GaN caps On 105 (GaN cap layer) of layer, referring to Fig. 6；In a further embodiment, the etching of ohmic contact hole can also stop at AlGaN potential barrier 104 (AlGaN barrier layer) is internal or removes the (AlGaN of AlGaN potential barrier 104 completely barrier layer)；
Step 207.HF cleans ohmic contact hole, and metal ohmic contact is deposited in ohmic contact hole using magnetron sputtering method Source-drain electrode (S levels, D levels) is formed, the structure of metal ohmic contact is Ti/Al/Ti/TiN, and thickness is respectively 200A/1200A/ 200A/200A, referring to Fig. 7.
Step 208. is using magnetron sputtering method in SiO2Grid metal is deposited on gate dielectric layer 107, the structure of grid metal is TiN/Ti/Al, thickness are respectively 300A/200A/3000A, and then photoetching grid metal forms gate electrode (G levels), gate electrode (G levels) Positioned at SiO2The upper surface of the gate dielectric layer 107, (Si of face silicon nitride medium layer 1063N4Passivation the grid opened up on) At window, referring to Fig. 8.
Step 209. surface protection, TEOS/Si is sequentially depositing by the vapour deposition process of plasma enhanced chemical3N4/ For TEOS as protective layer 108, thickness is respectively 6000A/3000A/2000A, and gold-tinted etch-protecting layer 108 forms via contact holes, Metal PAD is opened, interconnects and tests for device, referring to Fig. 9.
In the embodiment having, step 202 can also be omitted, directly forms SiO on the epitaxial wafer of GaN device2Grid are situated between Matter layer, but for scheme of the present embodiment compared to omission step 202, (the Si of silicon nitride medium layer 1063N4Passivation) may be used Play passivation and protective effect, be mainly used to eliminate material surface state, reduce surface damage, improve device stability and can By property.
By said process, a GaN MOS-HEMT for completely being made gate dielectric layer based on polysilicon oxidation has been made Into, behind can carry out multilayer wiring as needed.Described by process above, it can be seen that the manufacturing process of whole device The middle technique used and condition are that Si CMOS technologies platform is compatible, and process complexity is low, workable, very well The contradiction coordinated between device performance and process complexity.Therefore, the preparation side for the GaN MOS-HEMT that this patent proposes Method is that the design of GaN HEMT volume production scheme is provided the foundation and referred to.
Embodiment 2:
As different from Example 1, in the present embodiment:
By polysilicon layer 109 (Poly Si) in O in step 2042:H2=1:1 atmosphere, aoxidize 45 minutes at 800 DEG C, to complete Total oxygen turns to SiO2Film.
Structure using transistor device made of the preparation method of above-described embodiment 1 is as shown in Figure 9.
The GaN MOS-HEMT devices comprise at least：GaN epitaxy piece；Isolation is distributed to realize the gate electrode (G of electric insulation Level), source electrode (S levels) and drain electrode (D levels), the source electrode (S levels) and drain electrode (D levels) be respectively formed in GaN epitaxy piece Upper surface；Simultaneously including being formed between GaN epitaxy piece upper surface, gate electrode (G levels), source electrode (S levels) and drain electrode (D levels) SiO2Gate dielectric layer 107；Gate electrode (G levels) is located at SiO2The upper surface of gate dielectric layer 107.
Preferably, GaN epitaxy piece upper surface and SiO are formed in addition to2Silicon nitride medium layer between gate dielectric layer 107 106(Si3N4Passivation), (Si of silicon nitride medium layer 1063N4Passivation thickness range) is 30nm-35nm, (the Si of silicon nitride medium layer 1063N4Passivation the position of gate electrode (G levels) is corresponded on) formed with gate window, grid Window depth is to the upper surface of GaN epitaxy piece, SiO2Gate dielectric layer 107 is by (the Si of silicon nitride medium layer 1063N4Passivation) It is upper to be extended to by gate window inside gate window, to be contacted with GaN epitaxy piece.
It should be noted that in other embodiments, the depth of gate window can be etched to inside GaN epitaxy piece.
Preferably, the GaN epitaxy piece includes silicon substrate 101 (Silicon substrate), is sequentially formed at silicon substrate GaN cushions 102 (GaN buffer layer), AlGaN potential barrier 104 (AlGaN barrier layer) on 101 and GaN cap 105 (GaN cap layer), upper surface of the GaN cap 105 (GaN cap layer) as GaN epitaxy piece, GaN Two dimension is formed between cushion 102 (GaN buffer layer) and AlGaN potential barrier 104 (AlGaN barrier layer) Electron gas thin layer (2-DEG), SiO2Gate dielectric layer 107 is by (the Si of silicon nitride medium layer 1063N4Passivation grid is passed through on) Window extends to the upper surface of GaN epitaxy piece.
In other embodiments, SiO2Gate dielectric layer 107 can also be by silicon nitride medium layer 106 (Si3N4Passivation GaN cap 105 (GaN cap layer) inside or AlGaN potential barriers are extended to by gate window on) 104 (AlGaN barrier layer) of layer inside or GaN cushions 102 (GaN buffer layer) upper surface.
Preferably, the protective layer 108 deposited on gate electrode (G levels) and source-drain electrode (S levels, D levels), protective layer are additionally included in 108 structure is followed successively by TEOS/Si3N4/ TEOS, using etching mode formed with for exposing gate electrode (G on protective layer 108 Level) and source-drain electrode (S levels, D levels) contact hole (VIA).
Preferably, the structure of source-drain electrode (S levels, D levels) is Ti/Al/Ti/TiN, and thickness is respectively 200A/1200A/ 200A/200A。
Preferably, the structure of gate electrode (G levels) is TiN/Ti/Al, and thickness is respectively 300A/200A/3000A.
Preferably, the structure of protective layer 108 is TEOS/Si3N4/ TEOS, thickness are respectively 6000A/3000A/2000A.
Use above specific case is illustrated to the present invention, is only intended to help and is understood the present invention, not limiting The system present invention.For those skilled in the art, according to the thought of the present invention, can also make some simple Deduce, deform or replace.

Claims (10)

  1. A kind of 1. preparation method of GaN MOS-HEMT devices, it is characterised in that including：
    Prepare GaN epitaxy piece；
    SiO is formed on the upper surface of GaN epitaxy piece2Gate dielectric layer；
    Etch SiO2Inside gate dielectric layer to GaN epitaxy piece outer surface or GaN epitaxy piece, ohmic contact hole is formed；
    The deposit ohmic metal in ohmic contact hole；
    Ohmic metal is graphical and high annealing is to form source-drain electrode；
    In SiO2Preset to be formed on gate dielectric layer and gate electrode is made on the region of grid.
  2. 2. according to the method for claim 1, it is characterised in that SiO2Gate dielectric layer forms through polysilicon layer oxidation.
  3. 3. according to the method for claim 2, it is characterised in that forming SiO2Also in GaN epitaxy piece before gate dielectric layer Silicon nitride medium layer is formed on upper surface.
  4. 4. according to the method for claim 3, it is characterised in that form SiO on the upper surface of GaN epitaxy piece2Gate dielectric layer Including：
    Inside etch nitride silicon dielectric layer to the GaN epitaxy piece surface or GaN epitaxy piece, with the default region for forming grid Form gate window；
    Using LPCVD techniques in silicon nitride medium layer surface and gate window deposit polycrystalline silicon layer；
    High-temperature oxydation polysilicon layer, makes polysilicon layer be oxidized to SiO2Film, form SiO2Gate dielectric layer.
  5. 5. according to the method for claim 4, it is characterised in that high-temperature oxydation polysilicon layer refers to polysilicon layer in O2、H2Gas Complete oxidation is SiO under atmosphere, hot environment2Film.
  6. 6. according to the method for claim 4, it is characterised in that the GaN epitaxy piece includes substrate, is sequentially formed at substrate On cushion, barrier layer and cap layers, upper surface of the cap layers as GaN epitaxy piece；Etch nitride silicon dielectric layer is to outside the GaN Prolong and refer to etch nitride silicon dielectric layer to the upper surface of cap layers or cap layers inside or potential barrier inside the upper surface or GaN epitaxy piece of piece Layer is internal or etches away barrier layer completely.
  7. 7. according to the method for claim 1, it is characterised in that also include after gate electrode is made：Deposited in device surface Protective layer, the contact hole for exposing gate electrode and source-drain electrode is formed using etching mode on the protection layer.
  8. A kind of 8. GaN MOS-HEMT devices, it is characterised in that including：
    GaN epitaxy piece；
    To realize the gate electrode of electric insulation, source electrode and drain electrode, the source electrode and drain electrode are formed respectively for isolation distribution In GaN epitaxy piece upper surface；
    The SiO being formed between GaN epitaxy piece upper surface, gate electrode, source electrode and drain electrode2Gate dielectric layer.
    Also include being formed at GaN epitaxy piece upper surface and SiO2Silicon nitride medium layer between gate dielectric layer, on silicon nitride medium layer Corresponding to gate electrode position formed with gate window, SiO2Gate dielectric layer on silicon nitride medium layer by gate window by being extended To inside gate window, to be contacted with GaN epitaxy piece；
    Gate electrode is located at SiO2Gate dielectric layer upper surface.
  9. 9. GaN MOS-HEMT devices according to claim 8, it is characterised in that the GaN device GaN epitaxy piece includes Substrate, the cushion being sequentially formed on substrate, barrier layer and cap layers, upper surface of the cap layers as GaN epitaxy piece, cushion and Two-dimensional electron gas thin layer, SiO are formed between barrier layer2Gate dielectric layer by gate window on silicon nitride medium layer by extending to cap Inside layer upper surface or cap layers or inside barrier layer or cushion upper surface.
  10. 10. GaN MOS-HEMT devices according to claim 9, it is characterised in that be additionally included in gate electrode and source and drain electricity The protective layer of extremely upper deposition, on the protection layer using etching mode formed with for forming contact of the gate electrode with source-drain electrode Hole.
CN201710682055.9A 2017-08-10 2017-08-10 A kind of GaN MOS HEMT devices and preparation method thereof Pending CN107634009A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108615769A (en) * 2018-05-25 2018-10-02 中国电子科技集团公司第十三研究所 The preparation method of gallium oxide MOSFET element
CN111192827A (en) * 2019-08-14 2020-05-22 深圳方正微电子有限公司 Preparation method of p-GaN cap layer of enhanced high electron mobility transistor
CN112259459A (en) * 2020-10-20 2021-01-22 中国科学院微电子研究所 Gallium nitride-based electronic device and manufacturing method thereof
CN117438394A (en) * 2023-12-21 2024-01-23 润新微电子(大连)有限公司 GaN HEMT cascade device multi-layer sealing structure and preparation method thereof

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CN102834920A (en) * 2010-01-30 2012-12-19 美国国家半导体公司 Low leakage gan mosfet
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US20090166815A1 (en) * 2007-12-28 2009-07-02 Fujitsu Limited Semiconductor device and method for manufacturing semiconductor device
US20100314696A1 (en) * 2009-06-10 2010-12-16 Panasonic Corporation Field-effect transistor and method of fabricating same
CN102834920A (en) * 2010-01-30 2012-12-19 美国国家半导体公司 Low leakage gan mosfet
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108615769A (en) * 2018-05-25 2018-10-02 中国电子科技集团公司第十三研究所 The preparation method of gallium oxide MOSFET element
CN111192827A (en) * 2019-08-14 2020-05-22 深圳方正微电子有限公司 Preparation method of p-GaN cap layer of enhanced high electron mobility transistor
CN111192827B (en) * 2019-08-14 2022-06-14 深圳方正微电子有限公司 Preparation method of p-GaN cap layer of enhanced high electron mobility transistor
CN112259459A (en) * 2020-10-20 2021-01-22 中国科学院微电子研究所 Gallium nitride-based electronic device and manufacturing method thereof
CN117438394A (en) * 2023-12-21 2024-01-23 润新微电子(大连)有限公司 GaN HEMT cascade device multi-layer sealing structure and preparation method thereof
CN117438394B (en) * 2023-12-21 2024-04-16 润新微电子(大连)有限公司 GaN HEMT cascade device multi-layer sealing structure and preparation method thereof

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Application publication date: 20180126