CN111223777B - GaN-based HEMT device and manufacturing method thereof - Google Patents
GaN-based HEMT device and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 114
- 239000000463 material Substances 0.000 claims abstract description 64
- 238000011065 in-situ storage Methods 0.000 claims abstract description 37
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 29
- 230000000779 depleting effect Effects 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 21
- 150000004767 nitrides Chemical class 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 10
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 7
- 229910002704 AlGaN Inorganic materials 0.000 claims description 6
- 238000003780 insertion Methods 0.000 claims description 5
- 230000037431 insertion Effects 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 3
- 230000010287 polarization Effects 0.000 abstract description 14
- 230000002269 spontaneous effect Effects 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 description 16
- 238000000034 method Methods 0.000 description 14
- 238000002161 passivation Methods 0.000 description 8
- 230000006378 damage Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
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- 229910052737 gold Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
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- 238000004151 rapid thermal annealing Methods 0.000 description 2
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
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- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- Ceramic Engineering (AREA)
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- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a GaN-based HEMT device and a manufacturing method thereof. The manufacturing method comprises the steps of manufacturing a heterojunction, manufacturing a source electrode and a drain electrode which are matched with the heterojunction, wherein two-dimensional electron gas is formed in the heterojunction, and the source electrode and the drain electrode can be electrically connected through the two-dimensional electron gas; and further comprising the steps of growing an insulating layer directly on the heterojunction in situ at low temperature and growing a third semiconductor directly on the insulating layer in situ, the third semiconductor being capable of depleting a two-dimensional electron gas located thereunder; and manufacturing a grid electrode matched with the third semiconductor. After the heterojunction is formed by growth, the temperature is reduced, the insulating layer is directly grown on the heterojunction at low temperature in situ, the secondary pollution of the material can be avoided, the interface state density is reduced, the insulating layer with an amorphous structure can be formed, the spontaneous polarization and the piezoelectric polarization of the insulating layer material are eliminated, and the pollution to the growth of other structures of the device is avoided.
Description
Technical Field
The invention relates to a manufacturing method of a HEMT device, in particular to a GaN-based HEMT device and a manufacturing method thereof, and belongs to the technical field of semiconductors.
Background
The GaN-based HEMT device is a novel HEMT device, and the working principle is mainly that due to spontaneous polarization and piezoelectric polarization of III-nitride materials, two-dimensional electron gas is formed on a heterostructure interface, and the GaN-based HEMT device has extremely high electron concentration (up to 10) 13 /cm 2 ) The electron concentration can be controlled by the gate voltage, so that the control of the current is realized, and the field effect transistor is formed. But the HEMT of the Schottky structure has large grid leakage and small grid voltage swing (the maximum grid voltage is 1V-2V). Therefore, it is necessary to prepare HEMT devices with metal-insulator-semiconductor (MIS) structures, and the introduction of the insulating layer can reduce gate leakage, increase swing, and play a role in protecting the barrier layer in the etching process. However, on the one hand, unlike the Si system, the GaN material system can obtain a natural gate oxide layer with good interface and excellent quality through thermal oxidation, and can only obtain a gate dielectric layer and a passivation layer through various thin film deposition means. On the other hand, the GaN-based HEMT device has a large number of surface states on the surface of the barrier layer, so that when the device works, the surface states capture a large number of electrons to be negatively charged, so that the concentration of channel electrons is reduced, and the output current of the device is greatly reduced, namely a so-called current collapse phenomenon. Surface state is an important cause of current collapse effect of the HEMT device, and surface passivation is one of means for solving the current collapse effect. And the surface of the GaN-based HEMT is passivated by a dielectric layer, so that the surface state filling probability can be reduced, and the current collapse degree is reduced. Today's researchers use moreSiO 2 、SiNx、Al 2 O 3 、HfO 2 、Sc 2 O 3 The passivation medium commonly used as a gate dielectric layer of the HEMT device comprises SiO 2 、Sc 2 O 3 On the one hand, the materials of the dielectric layers are not matched with III-nitride, and the growth methods of the dielectric layers and the passivation layers are Plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), plasma enhanced atomic layer deposition (PE-ALD) and the like, and the problems of the methods are that heterojunction materials are required to be taken out from a growth chamber and transferred to other dielectric layer deposition chambers, so that secondary pollution of the materials is caused, a large number of interface states are inevitably present at the interface of the heterojunction materials and the dielectric layers, hysteresis phenomena of threshold voltage and current collapse are generated in the working process of the device, and popularization and application of the device are affected. The growing medium layer can avoid secondary pollution by the in-situ growth method, but for AlN, BN and the formed ternary quaternary compound serving as the medium layer, crystals are obtained by high-temperature in-situ growth, have great spontaneous polarization and piezoelectric polarization, so that two-dimensional electron gas is formed at the interface between the HEMT structure and the medium layer, the device has double channels due to the existence of the two-dimensional electron gas, the gate leakage current is seriously increased, the effect of reducing electric leakage of the medium layer is weakened, the gate voltage swing is difficult to increase, and the medium layer loses the due effect. In addition, due to the effects of spontaneous polarization and piezoelectric polarization, a heterojunction interface of a GaN-based HEMT structure is provided with two-dimensional electron gas, is a depletion type transistor structure, and can be turned off only by applying negative voltage, and an enhancement type device does not need negative voltage, so that the circuit complexity and cost are reduced in the fields of microwave power amplifiers and low-noise power amplifiers; the depletion type device is in a normally open state, and in the application field of the digital fast circuit, the enhancement type device can form low-power complementary logic, so that a circuit is simplified, and the safety of the circuit can be improved, so that the development of the enhancement type device is imperative. At present, P-type GaN and InGaN are mostly used as cap layers for preparing the enhanced field effect transistor, but acceptor atoms of the P-type GaN and the InGaN have larger activation energy and are easily passivated by H, and the doping efficiency is only 0.1-1%.And the p-type cap layer grows on the barrier layer directly, the p-type cap layer between the gate source and the gate drain must be etched in order to reduce the resistivity in the device manufacturing process, and the etching process inevitably causes damage and destruction to the surface of the barrier layer, so that leakage current and current collapse are increased.
Disclosure of Invention
The invention mainly aims to provide a GaN-based HEMT device and a manufacturing method thereof, thereby overcoming the defects in the prior art.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a manufacturing method of a GaN-based HEMT device, which comprises the following steps: a step of forming a heterojunction including a first semiconductor and a second semiconductor formed on the first semiconductor and having a band gap wider than that of the first semiconductor, the heterojunction having a two-dimensional electron gas formed therein;
and a step of manufacturing a source electrode and a drain electrode which are matched with the heterojunction, wherein the source electrode and the drain electrode can be electrically connected through the two-dimensional electron gas; the manufacturing method further comprises the following steps:
directly growing an insulating layer on the heterojunction at a low temperature in situ;
a step of growing a third semiconductor in situ directly on the insulating layer, the third semiconductor being capable of depleting a two-dimensional electron gas located thereunder;
and manufacturing a grid electrode matched with the third semiconductor.
Further, the growth temperature of the insulating layer is lower than the temperature for manufacturing the heterojunction.
In some more specific embodiments, the method of making comprises: and growing the insulating layer by adopting a metal organic chemical vapor phase epitaxy mode, wherein the growth temperature of the insulating layer is 300-800 ℃.
In some more specific embodiments, the method of making comprises: and growing the insulating layer by adopting a molecular beam epitaxy mode, wherein the growth temperature of the insulating layer is 300-600 ℃.
In some more specific embodiments, the method of making comprises: the heterojunction is formed by adopting any one mode of metal organic chemical vapor phase epitaxy and molecular beam epitaxy.
Further, the insulating layer is of an amorphous structure.
Preferably, the material of the insulating layer is selected from group III nitrides.
Preferably, the material of the insulating layer includes any one of AlN, BN, BAlN, BGaN and BAlGaN, but is not limited thereto.
Preferably, the thickness of the insulating layer is 5 to 50nm.
Further, the material of the third semiconductor is selected from P-type semiconductor.
Preferably, the material of the P-type semiconductor includes P-type BN, but is not limited thereto.
Further, the material of the first semiconductor is selected from group III nitrides.
Preferably, the material of the first semiconductor includes GaN, but is not limited thereto.
Further, the material of the second semiconductor is selected from group III nitrides.
Preferably, the material of the second semiconductor includes any one of AlGaN, alInN, alInGaN, alGaN, alInN and AlInGaN, but is not limited thereto.
In some more specific embodiments, the method of making comprises: and processing the heterojunction at least by adopting an etching or ion implantation mode to form an isolation region in the heterojunction so as to realize isolation among devices.
Preferably, the thickness of the etching is 100-500nm.
Preferably, the ion implantation energy is 10keV-200keV, and the implantation dosage is 10 13 cm -2 ～10 15 cm -2 。
The embodiment of the invention also provides a GaN-based HEMT device manufactured by the manufacturing method of the GaN-based HEMT device.
The embodiment of the invention also provides a GaN-based HEMT device, which comprises:
a heterojunction including a first semiconductor and a second semiconductor formed on the first semiconductor and having a band gap wider than that of the first semiconductor, and a source electrode, a drain electrode, and a gate electrode mated with the heterojunction, the heterojunction having a two-dimensional electron gas formed therein, the source electrode and the drain electrode being capable of being electrically connected by the two-dimensional electron gas;
and an insulating layer formed on the heterojunction, the insulating layer being formed between the source electrode and the drain electrode, and a third semiconductor being further formed on the insulating layer, the third semiconductor being distributed under the gate electrode.
Further, the insulating layer is of an amorphous structure.
Preferably, the material of the insulating layer is selected from group III nitrides.
Preferably, the material of the insulating layer includes any one of AlN, BN, BAlN, BGaN and BAlGaN, but is not limited thereto.
Preferably, the thickness of the insulating layer is 5 to 50nm.
Further, the material of the third semiconductor is selected from P-type semiconductor.
Preferably, the material of the P-type semiconductor includes P-type BN, but is not limited thereto.
Further, the material of the first semiconductor is selected from group III nitrides.
Preferably, the material of the first semiconductor includes GaN, but is not limited thereto.
Further, the material of the second semiconductor is selected from group III nitrides.
Preferably, the material of the second semiconductor includes any one of AlGaN, alInN, alInGaN, alGaN, alInN and AlInGaN, but is not limited thereto.
Further, an interposer is formed between the first semiconductor and the second semiconductor.
Preferably, the material of the insertion layer includes AlN, but is not limited thereto.
Further, the heterojunction is formed on a buffer layer formed on the substrate.
Further, the substrate includes a homogeneous substrate or a heterogeneous substrate.
Preferably, the material of the homogeneous substrate includes GaN, but is not limited thereto.
Preferably, the material of the heterogeneous substrate includes any one of GaN, sapphire, si, and silicon carbide, but is not limited thereto.
Compared with the prior art, the manufacturing method provided by the invention has the advantages that after the basic structure of the HEMT device (the basic structure of the HEMT device comprises a heterojunction) is formed in epitaxial growth equipment, the temperature is reduced, and an insulating layer is directly grown at low temperature in situ on the basic structure of the HEMT device; the secondary pollution of the material can be avoided by in-situ growth, the interface state density is reduced, and especially, the III nitride such as AlN, BN, BAlN, BGaN or BAlGaN can reach an amorphous state by adopting a low-temperature growth mode so as to form an insulating layer with an amorphous structure, which is beneficial to eliminating spontaneous polarization and piezoelectric polarization of the insulating layer material, and two-dimensional electron gas does not exist at the interface between the insulating layer and a barrier layer (namely a second semiconductor) of the HEMT device; in addition, when the insulating layer is formed in an in-situ growth mode, the pollution to the growth of other structures of the device is avoided; secondly, the insulating layer can play a role in protecting the barrier layer, the P-type semiconductor grows in situ on the insulating layer, and the barrier layer is not etched when the etching process is carried out, so that the damage to the structure of the device is avoided; and thirdly, the HEMT device structure of the p-type semiconductor is regrown after the insulating layer is formed in a low-temperature in-situ growth mode, so that an amorphous in-situ gate dielectric layer is formed, in-situ passivation is realized, the threshold voltage can be regulated to form an enhanced device, etching damage is avoided, gate leakage can be effectively reduced, gate swing is increased, current collapse is inhibited, and the comprehensive performance of the HEMT device is effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an epitaxial structure of a GaN-based HEMT device according to an exemplary embodiment of the invention;
fig. 2 is a schematic structural diagram of a GaN-based HEMT device according to an exemplary embodiment of the invention;
fig. 3 is a schematic structural diagram of another GaN-based HEMT device according to an exemplary embodiment of the invention.
Detailed Description
In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical scheme, the implementation process, the principle and the like are further explained as follows.
The embodiment of the invention provides a manufacturing method of a GaN-based HEMT device, which comprises the following steps: a step of forming a heterojunction including a first semiconductor and a second semiconductor formed on the first semiconductor and having a band gap wider than that of the first semiconductor, the heterojunction having a two-dimensional electron gas formed therein;
and a step of manufacturing a source electrode and a drain electrode which are matched with the heterojunction, wherein the source electrode and the drain electrode can be electrically connected through the two-dimensional electron gas; the manufacturing method further comprises the following steps:
directly growing an insulating layer on the heterojunction at a low temperature in situ;
a step of growing a third semiconductor in situ directly on the insulating layer, the third semiconductor being capable of depleting a two-dimensional electron gas located thereunder;
and manufacturing a grid electrode matched with the third semiconductor.
Further, the growth temperature of the insulating layer is lower than the temperature for manufacturing the heterojunction.
In some more specific embodiments, the method of making comprises: and growing the insulating layer by adopting a metal organic chemical vapor phase epitaxy mode, wherein the growth temperature of the insulating layer is 300-800 ℃.
In some more specific embodiments, the method of making comprises: and growing the insulating layer by adopting a molecular beam epitaxy mode, wherein the growth temperature of the insulating layer is 300-600 ℃.
In some more specific embodiments, the method of making comprises: the heterojunction is formed by adopting any one mode of metal organic chemical vapor phase epitaxy and molecular beam epitaxy.
Further, the insulating layer is of an amorphous structure.
Preferably, the material of the insulating layer is selected from group III nitrides.
Preferably, the material of the insulating layer includes any one of AlN, BN, BAlN, BGaN and BAlGaN, but is not limited thereto.
Preferably, the thickness of the insulating layer is 5 to 50nm.
Further, the material of the third semiconductor is selected from P-type semiconductor.
Preferably, the material of the P-type semiconductor includes P-type BN, but is not limited thereto.
Further, the material of the first semiconductor is selected from group III nitrides.
Preferably, the material of the first semiconductor includes GaN, but is not limited thereto.
Further, the material of the second semiconductor is selected from group III nitrides.
Preferably, the material of the second semiconductor includes any one of AlGaN, alInN, alInGaN, alGaN, alInN and AlInGaN, but is not limited thereto.
In some more specific embodiments, the method of making comprises: and processing the heterojunction at least by adopting an etching or ion implantation mode to form an isolation region in the heterojunction so as to realize isolation among devices.
Preferably, the thickness of the etching is 100-500nm.
Preferably, the ion implantation energy is 10keV-200keV, and the implantation dosage is10 13 cm -2 ～10 15 cm -2 。
The embodiment of the invention also provides a GaN-based HEMT device manufactured by the manufacturing method of the GaN-based HEMT device.
The embodiment of the invention also provides a GaN-based HEMT device, which comprises:
a heterojunction including a first semiconductor and a second semiconductor formed on the first semiconductor and having a band gap wider than that of the first semiconductor, and a source electrode, a drain electrode, and a gate electrode mated with the heterojunction, the heterojunction having a two-dimensional electron gas formed therein, the source electrode and the drain electrode being capable of being electrically connected by the two-dimensional electron gas;
and an insulating layer formed on the heterojunction, the insulating layer being formed between the source electrode and the drain electrode, and a third semiconductor being further formed on the insulating layer, the third semiconductor being distributed under the gate electrode.
Further, the insulating layer is of an amorphous structure.
Preferably, the material of the insulating layer is selected from group III nitrides.
Preferably, the material of the insulating layer includes any one of AlN, BN, BAlN, BGaN and BAlGaN, but is not limited thereto.
Preferably, the thickness of the insulating layer is 5 to 50nm.
Further, the material of the third semiconductor is selected from P-type semiconductor.
Preferably, the material of the P-type semiconductor includes P-type BN, but is not limited thereto.
Further, the material of the first semiconductor is selected from group III nitrides.
Preferably, the material of the first semiconductor includes GaN, but is not limited thereto.
Further, the material of the second semiconductor is selected from group III nitrides.
Preferably, the material of the second semiconductor includes any one of AlGaN, alInN, alInGaN, alGaN, alInN and AlInGaN, but is not limited thereto.
Further, an interposer is formed between the first semiconductor and the second semiconductor.
Preferably, the material of the insertion layer includes AlN, but is not limited thereto.
Further, the heterojunction is formed on a buffer layer formed on the substrate.
Further, the substrate includes a homogeneous substrate or a heterogeneous substrate.
Preferably, the material of the homogeneous substrate includes GaN, but is not limited thereto.
Preferably, the material of the heterogeneous substrate includes any one of GaN, sapphire, si, and silicon carbide, but is not limited thereto.
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In some more specific embodiments, a method for fabricating a GaN-based HEMT device may include the steps of:
a basic structure of a GaN-based HEMT device is grown, wherein the basic structure of the GaN-based HEMT device comprises a substrate, a buffer layer formed on the substrate, and a heterojunction formed on the buffer layer (the heterojunction comprises a channel layer and a barrier layer);
after the growth of the basic structure of the GaN-based HEMT device is finished, forming an insulating layer (also called a medium layer) in an epitaxial growth device for growing the basic structure of the GaN-based HEMT device by direct low-temperature in-situ growth, and continuing to grow a third semiconductor (namely a p-type semiconductor or a p-type layer or a p-type cap layer) in situ after the insulating layer is grown;
windows are processed in the source region and the drain region of the insulating layer, and then the source electrode and the drain electrode which are electrically contacted with the basic structure of the GaN-based HEMT device are manufactured by utilizing the windows; the source electrode and the drain electrode can be electrically connected through two-dimensional electron gas (2 DEG) formed in the basic structure of the GaN-based HEMT device;
and manufacturing a gate on the third semiconductor, and etching the third semiconductor between the gate and the source electrode and between the gate and the drain electrode.
According to the manufacturing method of the GaN-based HEMT device, the insulating layer is grown by using the in-situ low-temperature method to serve as the dielectric layer and the passivation layer of the GaN-based HEMT device, secondary pollution of materials can be avoided by in-situ growth, interface state density is reduced as much as possible, and particularly, the insulating layer materials such as AlN, BN, BAlN, BGaN or BAlGaN and the like can form an amorphous structure by adopting a low-temperature growth mode, so that spontaneous polarization and piezoelectric polarization of the materials can be eliminated, two-dimensional electron gas does not exist at the barrier layer interface of the basic structure of the insulating layer and the GaN-based HEMT device, and pollution to device structure growth does not exist when the insulating layer is grown in-situ; in addition, the p-type BN is grown on the insulating layer in situ to be used for exhausting two-dimensional electron gas to prepare the enhanced device, and the main advantages are that the BN is easy to obtain a p-type doped semiconductor (i.e. a p-type semiconductor or called a p-type layer), for example, the activation energy of the p-type semiconductor formed by doping the BN with Mg is very small, and the barrier layer is inevitably damaged by etching the p-type semiconductor between the grid electrode and the source electrode as well as between the grid electrode and the drain electrode when the enhanced HEMT device is manufactured by adopting the p-type GaN cap layer with a common structure, so that the problems of leakage current, current collapse and the like are caused; the p-type semiconductor is grown on the insulating layer in situ, so that the damage to the barrier layer of the HEMT device caused by an etching process can be avoided, the electrical property of the device is improved, the amorphous in-situ gate dielectric layer can be formed and in-situ passivation can be realized by regrowing the HEMT device structure of the p-type semiconductor after the insulating layer is grown in situ at low temperature, the threshold voltage can be regulated to form an enhanced device, the etching damage is avoided, the gate leakage can be effectively reduced, the gate swing is increased, the current collapse is restrained, and the effective improvement of the comprehensive performance of the GaN-based HEMT device is realized.
It should be noted that, any combination of the technical features of the above embodiments may be used, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
Specifically, a manufacturing method of a GaN-based HEMT device comprises the following steps:
in a more specific embodiment of the present invention, a manufacturing process of a GaN-based HEMT includes the steps of:
1) Growing a basic structure of the GaN-based HEMT device in MOCVD or MBE epitaxial growth equipment, wherein the basic structure of the GaN-based HEMT device comprises a buffer layer (with the thickness of 20-30 nm), a GaN layer (namely a first semiconductor or called a channel layer with the thickness of 1um-4 um) and a barrier layer (namely a second semiconductor with the thickness of 10nm-50 nm) which are sequentially grown on a homogeneous substrate (such as GaN) or a heterogeneous substrate (such as silicon, sapphire and silicon carbide), wherein an AlN insertion layer can be formed between the GaN layer and the barrier layer, and the AlN insertion layer has the thickness of 0.5nm-2 nm);
2) Reducing the temperature in the reaction chamber of the MOCVD or MBE epitaxial growth apparatus and adjusting the temperature, gas pressure and source flow, and depositing in situ an insulating layer of amorphous structure having a thickness of about 5-50 nm (the insulating layer is made of AlN, BN, BAlN, BGaN, BAlGaN, and the low temperature growth mode can enable AlN, BN, BAlN, BGaN or BAlGaN group III nitride to reach an amorphous state), wherein in some more specific embodiments, the temperature of the reaction chamber of the MOCVD epitaxial growth apparatus in this step is adjusted between 300-800 ℃, and the temperature of the reaction chamber of the MBE mode epitaxial growth apparatus in this step is adjusted between 300-600 ℃;
3) After the insulating layer is grown, continuing to grow a third semiconductor (such as p-type BN) in situ to form an epitaxial structure of the GaN-based HEMT device shown in FIG. 1;
4) Photoetching to protect the device mesa, etching (etching thickness 100-500 nm) or ion implantation (ion implantation energy 10keV-200keV, implantation dosage 10) 13 cm -2 -10 15 cm -2 ) Forming a device isolation region on the basic structure of the GaN-based HEMT device in a manner of realizing isolation between devices; the GaN-based HEMT device structure obtained by etching isolation is shown in figure 2; the structure of the GaN-based HEMT device obtained by ion implantation isolation is shown in figure 3;
5) Etching the third semiconductor between the grid electrode and the source electrode and between the grid electrode and the drain electrode by a dry etching or wet etching method;
6) Photoetching a source electrode pattern and a drain electrode pattern, and etching the insulating layer by a dry etching or wet etching method to open holes for the source electrode and the drain electrode;
7) Preparing a source electrode and a drain electrode in a source electrode and drain electrode region by an electron beam evaporation or sputtering method, wherein source electrode and drain electrode metals comprise one or more alloys of titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), platinum (Pt) and the like; then forming ohmic contact by rapid thermal annealing under the high-temperature and protective gas environment; the annealing temperature is generally 500-950 ℃, the annealing time is 10-120 seconds, and the protective gas comprises N 2 Or Ar;
8) Photoetching a grid pattern, and depositing metal on an insulating layer (or called an insulating medium layer or a medium layer) by an electron beam evaporation or sputtering mode to form a grid; the gate metal includes one or more metals of nickel (Ni), gold (Au), platinum (Pt), palladium (Pd), and the like.
9) The treatment was carried out at 300-500℃for 10 minutes using a rapid thermal annealing apparatus.
Compared with the prior art, the manufacturing method provided by the invention has the advantages that after the basic structure of the HEMT device (the basic structure of the HEMT device comprises a heterojunction) is formed in epitaxial growth equipment, the temperature is reduced, and an insulating layer is directly grown at low temperature in situ on the basic structure of the HEMT device; the secondary pollution of the material can be avoided by in-situ growth, the interface state density is reduced, and especially, the III nitride such as AlN, BN, BAlN, BGaN or BAlGaN can reach an amorphous state by adopting a low-temperature growth mode so as to form an insulating layer with an amorphous structure, which is beneficial to eliminating spontaneous polarization and piezoelectric polarization of the insulating layer material, and two-dimensional electron gas does not exist at the interface between the insulating layer and a barrier layer (namely a second semiconductor) of the HEMT device; in addition, when the insulating layer is formed by adopting a low-temperature in-situ growth mode, the pollution to the growth of other structures of the device is avoided; secondly, the insulating layer can play a role in protecting the barrier layer, the P-type semiconductor grows in situ on the insulating layer, the barrier layer cannot be etched when an etching process is carried out, and the device cannot be damaged; and thirdly, the HEMT device structure of the P-type semiconductor is regrown after the insulating layer is formed in a low-temperature in-situ growth mode, so that an amorphous in-situ gate dielectric layer is formed, in-situ passivation is realized, the threshold voltage can be regulated to form an enhanced device, etching damage is avoided, gate leakage can be effectively reduced, gate swing is increased, current collapse is inhibited, and the comprehensive performance of the HEMT device is effectively improved.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (28)
1. A manufacturing method of a GaN-based HEMT device comprises the following steps:
a step of forming a heterojunction including a first semiconductor and a second semiconductor formed on the first semiconductor and having a band gap wider than that of the first semiconductor, the heterojunction having a two-dimensional electron gas formed therein;
and a step of manufacturing a source electrode and a drain electrode which are matched with the heterojunction, wherein the source electrode and the drain electrode can be electrically connected through the two-dimensional electron gas; the manufacturing method is characterized by further comprising the following steps:
directly growing an insulating layer on the heterojunction at low temperature in situ, wherein the insulating layer is of an amorphous structure, the insulating layer is made of any one of AlN, BN, BAlN, BGaN and BAlGaN, and two-dimensional electron gas does not exist at the interface between the insulating layer and the second semiconductor;
a step of growing a third semiconductor in situ directly on the insulating layer, the third semiconductor being capable of depleting two-dimensional electron gas located thereunder, the third semiconductor being selected from P-type semiconductors;
and manufacturing a grid electrode matched with the third semiconductor.
2. The method of manufacturing according to claim 1, wherein: the growth temperature of the insulating layer is lower than the temperature for manufacturing and forming the heterojunction.
3. A method of manufacturing according to claim 1 or 2, characterized by comprising: and growing the insulating layer by adopting a metal organic chemical vapor phase epitaxy mode, wherein the growth temperature of the insulating layer is 300-800 ℃.
4. A method of manufacturing according to claim 1 or 2, characterized by comprising: and growing the insulating layer by adopting a molecular beam epitaxy mode, wherein the growth temperature of the insulating layer is 300-600 ℃.
5. The method of manufacturing according to claim 1, characterized by comprising: the heterojunction is formed by adopting any one mode of metal organic chemical vapor phase epitaxy and molecular beam epitaxy.
6. The method of manufacturing according to claim 1, wherein: the thickness of the insulating layer is 5-50 nm.
7. The method of manufacturing according to claim 1, wherein: the third semiconductor material comprises P-type BN.
8. The method of manufacturing according to claim 1, wherein: the first semiconductor is made of III-nitride.
9. The method of manufacturing according to claim 8, wherein: the material of the first semiconductor comprises GaN.
10. The method of manufacturing according to claim 1, wherein: the material of the second semiconductor is selected from III group nitride.
11. The method of manufacturing according to claim 10, wherein: the material of the second semiconductor includes any one of AlGaN, alInN, alInGaN.
12. The method of manufacturing according to claim 1, further comprising: and processing the heterojunction at least by adopting an etching or ion implantation mode to form an isolation region in the heterojunction so as to realize isolation among devices.
13. The method of manufacturing according to claim 12, wherein: the thickness of the etching is 100-500nm.
14. The method of manufacturing according to claim 12, wherein: the energy of the ion implantation is 10keV-200keV, and the implantation dosage is 10 13 cm -2 ～10 15 cm -2 。
15. A GaN-based HEMT device formed by the method of fabricating a GaN-based HEMT device of any of claims 1-14.
16. The GaN-based HEMT device is characterized by comprising:
a heterojunction including a first semiconductor and a second semiconductor formed on the first semiconductor and having a band gap wider than that of the first semiconductor, and a source electrode, a drain electrode, and a gate electrode mated with the heterojunction, the heterojunction having a two-dimensional electron gas formed therein, the source electrode and the drain electrode being capable of being electrically connected by the two-dimensional electron gas;
and an insulating layer formed on the heterojunction, wherein the insulating layer is formed between the source electrode and the drain electrode, a third semiconductor is further formed on the insulating layer, the third semiconductor is distributed below the grid electrode, the insulating layer is of an amorphous structure, the insulating layer is made of any one of AlN, BN, BAlN, BGaN and BAlGaN, the insulating layer is formed by adopting a metal organic chemical vapor phase epitaxy mode, the growth temperature of the insulating layer is 300-800 ℃, or the insulating layer is formed by adopting a molecular beam epitaxy mode, the growth temperature of the insulating layer is 300-600 ℃, two-dimensional electron gas does not exist at the interface between the insulating layer and the second semiconductor, and the third semiconductor is selected from P-type semiconductors.
17. The GaN-based HEMT device of claim 16, wherein: the thickness of the insulating layer is 5-50 nm.
18. The GaN-based HEMT device of claim 16, wherein: the third semiconductor material comprises P-type BN.
19. The GaN-based HEMT device of claim 16, wherein: the first semiconductor is made of III-nitride.
20. The GaN-based HEMT device of claim 19, wherein: the material of the first semiconductor comprises GaN.
21. The GaN-based HEMT device of claim 16, wherein: the material of the second semiconductor is selected from III group nitride.
22. The GaN-based HEMT device of claim 21, wherein: the material of the second semiconductor includes any one of AlGaN, alInN, alInGaN.
23. The GaN-based HEMT device of claim 16, wherein: an interposer is also formed between the first semiconductor and the second semiconductor.
24. The GaN-based HEMT device of claim 23, wherein: the material of the insertion layer comprises AlN.
25. The GaN-based HEMT device of claim 16, wherein: the heterojunction is formed on a buffer layer formed on a substrate.
26. The GaN-based HEMT device of claim 25, wherein: the substrate comprises a homogeneous substrate or a heterogeneous substrate.
27. The GaN-based HEMT device of claim 26, wherein: the material of the homogeneous substrate comprises GaN.
28. The GaN-based HEMT device of claim 26, wherein: the material of the heterogeneous substrate comprises any one of sapphire, si and silicon carbide.
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| TW201513345A (en) * | 2013-09-03 | 2015-04-01 | Triquint Semiconductor Inc | Linear high-electron mobility transistor |
| CN108389903A (en) * | 2018-03-01 | 2018-08-10 | 中国科学院微电子研究所 | AlGaN/GaN high electron mobility transistor and preparation method with graphene heat dissipating layer |
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| TW201513345A (en) * | 2013-09-03 | 2015-04-01 | Triquint Semiconductor Inc | Linear high-electron mobility transistor |
| CN108389903A (en) * | 2018-03-01 | 2018-08-10 | 中国科学院微电子研究所 | AlGaN/GaN high electron mobility transistor and preparation method with graphene heat dissipating layer |
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