CN117096177A - Concave gate enhanced gallium oxide transistor and preparation method thereof - Google Patents
Concave gate enhanced gallium oxide transistor and preparation method thereof Download PDFInfo
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- CN117096177A CN117096177A CN202310947646.XA CN202310947646A CN117096177A CN 117096177 A CN117096177 A CN 117096177A CN 202310947646 A CN202310947646 A CN 202310947646A CN 117096177 A CN117096177 A CN 117096177A
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 63
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 49
- 150000002500 ions Chemical class 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 claims description 116
- 238000000034 method Methods 0.000 claims description 28
- 229910052782 aluminium Inorganic materials 0.000 claims description 18
- 229910052733 gallium Inorganic materials 0.000 claims description 14
- 229910052738 indium Inorganic materials 0.000 claims description 13
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 10
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 238000009832 plasma treatment Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 3
- 239000010408 film Substances 0.000 description 81
- 239000010409 thin film Substances 0.000 description 22
- 239000010931 gold Substances 0.000 description 19
- 238000005530 etching Methods 0.000 description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 229910052737 gold Inorganic materials 0.000 description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
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- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000012159 carrier gas Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910017052 cobalt Inorganic materials 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 229910052741 iridium Inorganic materials 0.000 description 5
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
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- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001017 electron-beam sputter deposition Methods 0.000 description 2
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- 239000007787 solid Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
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- 239000010703 silicon Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a concave gate enhanced gallium oxide transistor and a preparation method thereof, wherein the gallium oxide transistor comprises Ga which are sequentially stacked 2 O 3 Substrate, ga 2 O 3 Buffer layer, ga 2 O 3 A channel layer; further comprises: the first high-guiding layer and the second high-guiding layer are respectively arranged on two opposite sides of the channel layer; sequentially stacking a space layer, a barrier layer and a donor layer which are arranged on the channel layer; constituting the first semiconductor material in the donor layerAt least one of the ions of (2) is a donor ion; a groove recessed toward the substrate is formed in the donor layer; two-dimensional electron gas is formed at the interface of the space layer and the channel layer except the projection area of the groove at the interface; the insulated gate dielectric layer is arranged on the inner wall of the groove and the donor layer; setting a grid electrode on the insulated gate dielectric layer; and a source electrode and a drain electrode respectively arranged on the first high-conductivity layer and the second high-conductivity layer. The invention realizes the enhancement type transistor by combining the arrangement of the donor layer and the concave gate structure.
Description
Technical Field
The invention relates to the technical field of transistors, in particular to a concave gate enhanced gallium oxide transistor and a preparation method thereof.
Background
In recent years, various power devices such as schottky diode (SBD), metal Oxide Semiconductor Field Effect Transistor (MOSFET), metal semiconductor field effect transistor (MESFET) and the like have been prepared based on gallium oxide materials. In order to produce gallium oxide-based high-frequency devices, studies have recently been started (Al x Ga 1-x ) 2 O 3 Heterostructure, support (Al x Ga 1-x ) 2 O 3 Barrier layer and Ga 2 O 3 Two-dimensional electron gas (2 DEG) formed by heterojunction of channel layer for preparing high mobility transistor (HEMT), i.e. in conventional high mobility lateral gallium oxide device, the generation of two-dimensional electron gas mainly comes from (Al x Ga 1-x ) 2 O 3 Barrier layer and Ga 2 O 3 The spontaneous polarization and piezoelectric polarization of the heterojunction of the channel layer have the structure shown in figure 1, and specifically comprise Ga which are sequentially stacked 2 O 3 Substrate 11, ga 2 O 3 Buffer layer 12, ga 2 O 3 Channel layer 13 and disposed on Ga 2 O 3 On the channel layer 13 (Al x Ga 1-x ) 2 O 3 The barrier layer 15 (between the barrier layer and the channel layer may be further provided (Al x Ga 1-x ) 2 O 3 Spatial layer), arranged at (Al x Ga 1-x ) 2 O 3 A gate electrode 16 on the barrier layer 15, a source electrode 17 and a drain electrode 18 disposed on the high-conductivity layer 14; wherein Ga 2 O 3 Channel layers 13 and (Al x Ga 1-x ) 2 O 3 The barrier layer 15 forms a heterojunction and forms a two-dimensional electron gas. But due to the presence of two-dimensional electron gas, the high mobility lateral gallium oxide transistor device is a sky-lightHowever, depletion mode devices, enhancement mode high mobility lateral gallium oxide transistor devices have not been reported. In addition, (Al) x Ga 1-x ) 2 O 3 Barrier layer and Ga 2 O 3 The polarization effect of the heterojunction of the channel layer is very strong, and it is difficult to fully deplete the two-dimensional electron gas, which is also a difficulty in preparing the enhanced high mobility lateral gallium oxide transistor device.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a concave gate enhancement type gallium oxide transistor and a preparation method thereof, which aims to solve the problem that the existing high mobility lateral gallium oxide transistor is a depletion type device, and no enhancement type high mobility lateral gallium oxide transistor is reported at present.
The technical scheme of the invention is as follows:
in a first aspect of the present invention, there is provided a concave gate enhanced gallium oxide transistor comprising Ga sequentially stacked 2 O 3 Substrate, ga 2 O 3 Buffer layer, ga 2 O 3 A channel layer;
further comprises:
a first high-conductivity layer and a second high-conductivity layer respectively arranged on the Ga 2 O 3 Opposite sides on the channel layer;
a space layer, a barrier layer and a donor layer sequentially stacked on the Ga 2 O 3 A channel layer disposed on and between the first and second high-guiding layers; the donor layer includes a first semiconductor material, at least one of ions constituting the first semiconductor material being a donor ion; the donor layer is provided with a crystal orientation toward the Ga 2 O 3 A recess recessed in a substrate direction; the space layer and the Ga 2 O 3 Two-dimensional electron gas is arranged outside a projection area of the groove at the interface of the channel layer;
the insulated gate dielectric layer is arranged on the inner wall of the groove and the donor layer;
the grid electrode is arranged on the insulated gate dielectric layer;
and the source electrode and the drain electrode are respectively arranged on the first high-conductivity layer and the second high-conductivity layer.
Optionally, the first semiconductor material comprises Si 3 N 4 、SiO 2 At least one of them.
Optionally, the thickness of the donor layer is 20-50 nm.
Optionally, the materials of the space layer and the barrier layer are respectively and independently selected from Al doped Ga 2 O 3 Or In-doped Ga 2 O 3 。
Optionally, the Al is doped with Ga 2 O 3 The mole number of Al accounts for 0% -20% of the sum of mole numbers of Al and Ga, and 0% is not taken; or, the In is doped with Ga 2 O 3 The mole number of In accounts for 0% -20% of the sum of the mole numbers of In and Ga, and 0% is not taken.
Optionally, the thickness of the barrier layer is 10-20 nm.
Optionally, the first donor ions are implanted into both the first high-guiding layer and the second high-guiding layer.
Optionally, the thickness of the space layer is 1-2 nm and/or the Ga 2 O 3 The thickness of the buffer layer is 5-10 mu m; and/or the Ga 2 O 3 The thickness of the channel layer is 100-600 nm.
In a second aspect of the present invention, a method for preparing a concave gate enhanced gallium oxide transistor is provided, wherein the method comprises the steps of:
providing Ga 2 O 3 A substrate;
at the Ga 2 O 3 Ga is formed on a substrate 2 O 3 A buffer layer;
at the Ga 2 O 3 Forming Ga on a buffer layer 2 O 3 A channel layer;
at the Ga 2 O 3 A first high-conductivity layer and a second high-conductivity layer are respectively formed on two opposite sides of the channel layer;
at the Ga 2 O 3 On the channel layerForming a space layer, a barrier layer and a donor layer which are sequentially stacked between the first high-conductivity layer and the second high-conductivity layer; the donor layer includes a first semiconductor material, at least one of ions constituting the first semiconductor material being a donor ion;
forming a donor layer in the Ga 2 O 3 A recess recessed in a substrate direction; the space layer and the Ga 2 O 3 Two-dimensional electron gas is arranged outside a projection area of the groove at the interface of the channel layer;
forming an insulated gate dielectric layer on the inner wall of the groove and the donor layer;
forming a source electrode and a drain electrode on the first high-conductivity layer and the second high-conductivity layer, respectively;
and forming a grid electrode on the insulated gate dielectric layer.
Optionally, the step of forming a donor layer on the barrier layer specifically includes:
in-situ N plasma treatment is carried out firstly, and Si is deposited on the barrier layer 3 N 4 、SiO 2 At least one of (a) and (b) forming a donor layer.
The beneficial effects are that: the invention does not use barrier layer and Ga 2 O 3 The channel layer heterojunction forms a two-dimensional electron gas, but the two-dimensional electron gas is formed by a donor state formed by donor ions constituting the first semiconductor material in the donor layer, i.e., the source of the two-dimensional electron gas in the present invention is not the polarization effect of the barrier layer, but the two-dimensional electron gas is obtained by the donor state at the interface, so that the two-dimensional electron gas is obtained by (Al x Ga 1-x ) 2 O 3 Barrier layer and Ga 2 O 3 The two-dimensional electron gas formed by the polarization effect of the heterojunction of the channel layer is more easily depleted, a precondition is provided for preparing the enhanced device, and then the enhanced device is realized by forming a concave gate structure by means of grooves in the barrier layer.
Drawings
Fig. 1 is a schematic structural diagram of a prior art high mobility lateral gallium oxide device.
Fig. 2 is a schematic structural diagram of a concave-gate enhancement type gallium oxide transistor according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a process for manufacturing a concave-gate enhanced GaN transistor according to an embodiment of the invention, wherein (a) is Ga 2 O 3 Schematic of the substrate, (b) is Ga 2 O 3 Ga is formed on a substrate 2 O 3 Schematic diagram of buffer layer, (c) is Ga 2 O 3 Forming Ga on a buffer layer 2 O 3 Schematic diagram of channel layer, (d) is Ga 2 O 3 A first film is formed on the channel layer, (e) a second film is formed on the first film, (f) a third film is formed on the second film, (g) a groove is formed on the third film, (h) a first high-guiding layer and a second high-guiding layer are formed, (i) an insulating gate dielectric film is formed, (j) a source-drain region insulating gate dielectric opening is formed, (k) a source electrode and a drain electrode are formed, and (l) a gate electrode is formed.
Detailed Description
The invention provides a concave gate enhanced gallium oxide transistor and a preparation method thereof, which are used for making the purposes, technical schemes and effects of the invention clearer and more definite, and are further described in detail below. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The terms such as "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
When an element is referred to as being "fixed" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
If there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
In addition, it should be noted that, the technical solutions of the embodiments of the present invention may be combined with each other, but it is necessary to be based on the fact that those skilled in the art can implement the embodiments, and when the technical solutions are inconsistent or cannot be implemented, it should be considered that the combination of the technical solutions does not exist, and is not within the scope of protection required by the present invention.
The embodiment of the invention provides a concave gate enhanced gallium oxide transistor, which comprises Ga which are sequentially stacked as shown in fig. 2 2 O 3 Substrate 1, ga 2 O 3 Buffer layer 2, ga 2 O 3 A channel layer 3;
the concave gate enhanced gallium oxide transistor further comprises:
a first high-conductivity layer 4 and a second high-conductivity layer 5 respectively arranged on the Ga 2 O 3 Opposite sides on the channel layer 3;
a space layer 6, a barrier layer 7 and a donor layer 8, in this orderIs laminated and arranged on the Ga 2 O 3 A channel layer 3 and arranged between the first high guiding layer 4 and the second high guiding layer 5; the donor layer 8 comprises a first semiconductor material, at least one of the ions constituting the first semiconductor material being a donor ion; the donor layer 8 is provided with a layer of the Ga 2 O 3 A groove recessed in the direction of the substrate 1; the space layer 6 and the Ga 2 O 3 Two-dimensional electron gas is formed at the interface of the channel layer 3 except for the projection area of the groove at the interface;
an insulated gate dielectric layer 9 disposed on the inner wall of the recess and the donor layer 8;
a gate electrode 10 disposed on the insulating gate dielectric layer 9;
a source electrode 11 and a drain electrode 12 are respectively disposed on the first high guiding layer 4 and the second high guiding layer 5.
Is supported by the traditional lateral gallium oxide transistor (Al x Ga 1-x ) 2 O 3 Barrier layer and Ga 2 O 3 Different from the two-dimensional electron gas formed by the heterojunction of the channel layer, the barrier layer and Ga are not utilized in the embodiment 2 O 3 The channel layer heterojunction forms a two-dimensional electron gas, but rather is formed by a donor state formed by donor ions constituting the first semiconductor material in the donor layer, i.e., the source of the two-dimensional electron gas in this embodiment is not the polarization effect of the barrier layer, but is obtained by the donor state at the interface, so that the two-dimensional electron gas is generated by (Al x Ga 1-x ) 2 O 3 Barrier layer and Ga 2 O 3 The two-dimensional electron gas formed by the polarization effect of the heterojunction of the channel layer is more easily depleted, a precondition is provided for preparing the enhanced device, and then the enhanced device is realized by means of the concave gate structure formed by the grooves in the barrier layer.
In this embodiment, a recess is formed in the donor layer, the bottom of the recess is abutted to the upper surface of the barrier layer, i.e. the first semiconductor material of the donor layer is not present in the recess region, and two-dimensional electron gas cannot be formed by the donor state formed by the donor ions constituting the first semiconductor material, so that the recessAt the space layer with Ga 2 O 3 The projection area at the interface of the channel layer is not provided with two-dimensional electron gas, the device cannot be conducted, namely, when no voltage is applied to the grid electrode, the device is in a blocking state; when a gate voltage is applied, an electron accumulation layer is formed in the bottom area of the groove, so that the conduction of the device is promoted, and the enhancement type is realized.
As shown in fig. 2, in some embodiments, the bottom of the recess abuts the upper surface of the barrier layer 7.
In some embodiments, the first semiconductor material comprises Si 3 N 4 、SiO 2 At least one of them. Si (Si) 3 N 4 Consists of Si ions and Ni ions, wherein the S ions are donor ions, si 3 N 4 The Si ions in the film are diffused to the lower layer to leave N ions with negative electricity, but the electronegativity of the N ions is still strong, the trapped electrons can leave positive charges (like hollow dots in fig. 2) at the original positions for achieving stability, the Si ions are diffused to generate movable electrons, and the movable electrons are actually a very thin electron layer and can be regarded as two-dimensional electron gas (like solid dots in fig. 2). Specifically, the diffusion depth of Si ions cannot exceed one hundred nanometers, and therefore, the diffusion depth of Si ions determines the formation of two-dimensional electron gas in the space layer and Ga 2 O 3 At the interface of the channel layer.
In addition, the Si 3 N 4 、SiO 2 The donor layer formed by at least one of the above materials can form two-dimensional electron gas, and can also play a role in reducing the oxidation of the surface of the device and avoid the electric leakage of the surface of the device.
In some embodiments, the donor layer has a thickness of 20 to 50nm, which may be, for example, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, or the like.
In some embodiments, the materials of the space layer and the barrier layer are each independently selected from Al doped Ga 2 O 3 Or In-doped Ga 2 O 3 Specifically, the Al-doped beta-Ga 2 O 3 Or In-doped beta-Ga 2 O 3 。
In some embodiments, the Al dopingGa 2 O 3 The mole number of Al accounts for 0% -20% of the sum of mole numbers of Al and Ga, and 0% is not taken; or, the In is doped with Ga 2 O 3 The mole number of In accounts for 0% -20% of the sum of the mole numbers of In and Ga, and 0% is not taken. I.e. by being in Ga 2 O 3 The material is doped with Al or In to form (Al x Ga 1-x ) 2 O 3 Alloy or (In) x G 1-x ) 2 O 3 Alloy, where x=0 to 0.2 (excluding 0).
Al doped with Ga 2 O 3 Or In-doped Ga 2 O 3 The material is a ternary alloy material, and the alloy material can produce alloy scattering on two-dimensional electron gas, so that the mobility of the device is affected. In order to reduce the influence of alloy scattering, therefore, the barrier layer and Ga 2 O 3 A space layer is interposed between the channel layers, and the thickness is 1 to 2nm (for example, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm, or the like). The material of the space layer is also obtained by mixing Ga 2 O 3 The material being doped with Al or In to form (Al x Ga 1-x ) 2 O 3 Alloy or (In) x G 1-x ) 2 O 3 The alloy, but in particular applications, has an x value that is less than the x value in the barrier layer.
In some embodiments, the barrier layer has a thickness of 10 to 20nm. The thickness and molar composition of the barrier layer directly affect Ga 2 O 3 The concentration of the two-dimensional electron gas In the channel is generally higher as the barrier layer is thicker, and higher Al or In composition produces higher concentration of the two-dimensional electron gas. In the present invention, however, two-dimensional electron gas is not generated through the barrier layer, and therefore, in order to avoid the generation of two-dimensional electron gas by the barrier layer, it is necessary to reduce the Al or In composition and thickness of the barrier layer, and therefore, when the thickness of the barrier layer is 10 to 20nm, the Al or In molar ratio is 0% to 20%, the barrier layer does not generate two-dimensional electron gas (e.g., when the Al or In molar ratio is 15%, the thickness of the barrier layer is set to 15nm, the barrier layer does not generate two-dimensional electron gas, and when the thickness of the barrier layer is set to 20nm, the barrier layer does not generate two-dimensional electron gas, and at the same time, when the Al or In molar ratio is relatively high, it can be realized that the generation of no two-dimensional electron gas is generated by reducing the thickness of the barrier layerWhen the molar ratio of Al or In is 20% and the thickness of the barrier layer is set to 10nm, it is possible to realize that no two-dimensional electron gas is generated. Compared with the prior two-dimensional electron gas formed by the barrier layer (the content of the Al or In component is enough and the thickness of the barrier layer is enough), the invention forms the two-dimensional electron gas by the charges at the interface, adopts the barrier layer with low Al or In component and low thickness (avoids the generation of the two-dimensional electron gas) and ensures the two-dimensional electron gas to be matched with Ga 2 O 3 The channel layers have smaller lattice mismatch, and the reliability of the device can be improved.
In some embodiments, the Ga 2 O 3 The substrate is beta-Ga 2 O 3 A substrate, which is a high-resistance substrate and has an electron concentration of less than 10 14 Individual/cm 3 Wherein at least one of Fe and Mg is doped, and Ga doped with Fe or Mg 2 O 3 The substrate is a commonly used high-resistance substrate.
β-Ga 2 O 3 Has monoclinic crystal structure and best thermal stability. beta-Ga 2 O 3 With ultra wide band gap of 4.9eV and high critical breakdown field strength of 8MV/cm, the temperature of the material is over 200cm at room temperature 2 V.s, 2790cm at low temperature 2 Mobility of/V.s and 2X 10 7 The electron saturation velocity of cm/s is an ideal material for preparing high-power devices.
In some embodiments, the substrate has a thickness of 100 to 650 μm.
In some embodiments, the Ga 2 O 3 The buffer layer is beta-Ga 2 O 3 A buffer layer of unintentionally doped (UID) beta-Ga 2 O 3 Buffer layer or doped beta-Ga 2 O 3 A buffer layer of doped beta-Ga 2 O 3 The buffer layer may be doped with at least one of Si, sn, ge, V, nb, ta.
In some embodiments, the beta-Ga 2 O 3 The electron concentration of the buffer layer was 5×10 15 ～1×10 17 Individual/cm 3 。
In some embodiments, the Ga 2 O 3 Thickness of buffer layerThe degree is 5-10 mu m. Ga 2 O 3 The buffer layer plays a role in withstand voltage in the off state, and thus the thickness of the buffer layer is relatively thick, generally 5 to 10 μm. For example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm may be used.
In some embodiments, the Ga 2 O 3 The material of the channel layer is intrinsic Ga 2 O 3 . To reduce Ga 2 O 3 Scattering of the buffer layer on two-dimensional electron gas, improving mobility of the device, and dispersing the buffer layer in Ga 2 O 3 The buffer layer is provided with a layer of high-quality intrinsic gallium oxide material, i.e. intrinsic Ga 2 O 3 And the channel layer is used as a transport channel of the two-dimensional electron gas.
In some embodiments, the Ga 2 O 3 The thickness of the channel layer is 100-600 nm. For example, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, or the like can be used.
In some embodiments, the first high guiding layer and the second high guiding layer are both implanted with first donor ions. So that it can form ohmic contacts with the source and drain electrodes. Specifically, the first donor ion includes, but is not limited to, si ion. The concentration of the first donor ion is 1×10 19 ～2×10 19 Individual/cm 3 。
In some embodiments, the material of the insulated gate dielectric layer includes but is not limited to Al 2 O 3 、SiO 2 At least one of AlN.
In some embodiments, the thickness of the insulated gate dielectric layer is 10-80 nm.
In some embodiments, the gate has a thickness of 50-200 nm, which may be, for example, 50nm, 60nm, 80nm, 100nm, 150nm, 180nm, 200nm, or the like.
In some embodiments, the material of the gate electrode is selected from at least one of nickel, gold, titanium, aluminum, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, and tungsten, but is not limited thereto.
In some embodiments, the source has a thickness of 20-200 nm, such as 20nm, 50nm, 60nm, 80nm, 100nm, 150nm, 180nm, 200nm, or the like.
In some embodiments, the material of the source electrode is at least one selected from titanium, gold, aluminum, nickel, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, and tungsten, but is not limited thereto. These materials may form ohmic contacts with the first high guiding layer.
In some embodiments, the drain has a thickness of 20-200 nm, which may be, for example, 20nm, 50nm, 60nm, 80nm, 100nm, 150nm, 180nm, 200nm, or the like.
In some embodiments, the material of the drain electrode is at least one selected from titanium, gold, aluminum, nickel, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, and tungsten, but is not limited thereto. These materials may form an ohmic contact with the second high guiding layer.
The embodiment of the invention also provides a preparation method of the concave gate enhanced gallium oxide transistor, wherein as shown in fig. 3, the preparation method comprises the following steps:
s1, as shown in FIG. 3 (a), ga is provided 2 O 3 A substrate 1;
s2, as shown in FIG. 3 (b), is the Ga 2 O 3 Ga is formed on a substrate 1 2 O 3 A buffer layer 2;
s3, as shown in FIG. 3 (c), is the Ga 2 O 3 Ga is formed on the buffer layer 2 2 O 3 A channel layer 3;
s4, as shown in FIG. 3 (h), is the Ga 2 O 3 A first high-conductivity layer 4 and a second high-conductivity layer 5 are respectively formed on two opposite sides of the channel layer 3;
s5, as shown in FIG. 3 (h), is the Ga 2 O 3 A space layer 6, a barrier layer 7 and a donor layer 8 which are sequentially stacked are formed on the channel layer 3 and between the first high-guiding layer 4 and the second high-guiding layer 5; the donor layer includes a first semiconductor material, at least one of ions constituting the first semiconductor material being a donor ion;
s6, as shown in FIG. 3 (h), the Ga is formed in the donor layer 8 2 O 3 A recess 13 recessed 10 in the direction of the substrate 1; the space layer 6 and the Ga 2 O 3 Except for the recess 13 at the interface of the channel layer 3Two-dimensional electron gas is formed outside the projection area;
s7, as shown in (j) of FIG. 3, forming an insulated gate dielectric layer 9 on the inner wall of the groove 13 and the donor layer 8;
s8, as shown in (k) of fig. 3, forming a source electrode 11 and a drain electrode 12 on the first high-conductivity layer 4 and the second high-conductivity layer 6, respectively;
s9, as shown in fig. 3 (l), a gate 10 is formed on the insulating gate dielectric layer 9 (the gate is formed on the insulating gate dielectric layer in the recess).
The embodiment of the invention provides a simple method, and the embodiment of the invention realizes the two-dimensional electron gas by utilizing the donor state provided at the interface by utilizing the donor layer, and simultaneously realizes the preparation of the strong transistor by utilizing the concave gate structure, different from the traditional method for forming the two-dimensional electron gas by the polarization effect of the barrier layer.
In this embodiment, the materials, doped ions, thicknesses, etc. of the layers are described above, and will not be described here again.
In step S2, in some embodiments, the Ga is deposited by a method including, but not limited to, one of Metal Organic Chemical Vapor Deposition (MOCVD) method, molecular Beam Epitaxy (MBE) method, hydride Vapor Phase Epitaxy (HVPE) method, plasma Enhanced Chemical Vapor Deposition (PECVD) method 2 O 3 Ga is formed on a substrate 2 O 3 And a buffer layer.
In step S3, in some embodiments, the Ga is deposited by a method including, but not limited to, one of Metal Organic Chemical Vapor Deposition (MOCVD) method, molecular Beam Epitaxy (MBE) method, hydride Vapor Phase Epitaxy (HVPE) method, plasma Enhanced Chemical Vapor Deposition (PECVD) method 2 O 3 Forming Ga on a buffer layer 2 O 3 And a channel layer.
In steps S4-S6, in some embodiments, the Ga 2 O 3 A first high-conductivity layer 4 and a second high-conductivity layer 5 are respectively formed on two opposite sides of the channel layer 3; at the Ga 2 O 3 The step of forming the space layer 6, the barrier layer 7 and the donor layer 8, which are sequentially stacked, on the channel layer 3 and between the first high-guiding layer 4 and the second high-guiding layer 5, specifically includes:
s41, as shown in FIG. 3 (d), in the Ga 2 O 3 A first thin film 6 'is formed on the channel layer 3, the first thin film 6' including Al-doped Ga 2 O 3 Or In-doped Ga 2 O 3 (i.e. (Al) x Ga 1-x ) 2 O 3 )；
S42, as shown in (e) of FIG. 3, forming a second film 7' on the first film 6', the second film 7' including Al-doped Ga 2 O 3 Or In-doped Ga 2 O 3 (i.e. (Al) x Ga 1-x ) 2 O 3 )；
S43, as shown in (f) of FIG. 3, an in-situ N plasma treatment is first performed, and then a third film 8' is formed on the second film 7', the third film 8' including Si 3 N 4 、SiO 2 At least one of (a) and (b); the Ga 2 O 3 A two-dimensional electron gas (as solid dots in figure f) is formed at the interface of the channel layer 3 and the first film 6', and a positive charge (as hollow dots in figure f) is formed at the interface of the third film 8' and the second film 7 ';
s44, as shown in (g) of FIG. 3, etching is performed on the third film 8', and etching damage is repaired by wet etching, so that a groove 13 is formed;
s45, as shown in (h) of fig. 3, donor ions are respectively injected into two side areas of the first film 6', the second film 7', and the third film 8' which are integrally arranged in a laminated way, and the two side areas are annealed at 850-900 ℃ for 20-30 min for activation, so as to form a first high-conductivity layer 4 and a second high-conductivity layer 5; the regions of the first film 6', the second film 7', and the third film 8' into which the donor ions are not implanted, i.e., the space layer 6, the barrier layer 7, and the donor layer 8, respectively. In step S45, the implantation depth of the donor ions is from the surface of the third film 8' to Ga 2 O 3 At the interface of the channel layer 3 and the first thin film 6', the implantation depth of the donor ions may extend to Ga 2 O 3 In the channel layer 3, the first high guiding layer 4 and the second high guiding layer 5 are obtained to have a thicker thickness, but the thicknesses of the first high guiding layer 4 and the second high guiding layer 5 do not exceed 200nm.
In this embodiment, in step S43, the N plasma treatment can promote the shift of the threshold voltage of the device to the left, avoiding the threshold voltage from being too high.
As shown in fig. 1, in order to manufacture a groove structure of a lateral gallium oxide transistor device of a conventional structure, it is necessary to use a semiconductor device having a structure which is extremely stable in chemical properties (Al x Ga 1-x ) 2 O 3 The barrier layer is etched with high difficulty. In the step S44 of the present invention, the etched material is Si with very mature silicon process 3 N 4 Or SiO 2 Is no longer extremely chemically stable (Al x Ga 1-x ) 2 O 3 Si in the present invention 3 N 4 (or SiO) 2 ) And (Al) x Ga 1-x ) 2 O 3 The etching selectivity of the barrier layer is much higher than that of the conventional device (Al x Ga 1-x ) 2 O 3 Barrier layer and Ga 2 O 3 The etching selection ratio of the channel layer reduces the difficulty of the etching process and improves the process repeatability of the device.
In step S43, in some embodiments, at least one of Low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), atmospheric Pressure Chemical Vapor Deposition (APCVD), low temperature chemical vapor deposition (PCVD) is used, and then a third film is formed on the second film.
In step S6, in some embodiments, the bottom of the groove 13 abuts against the upper surface of the barrier layer 7.
In steps S7-S8, in some embodiments, an insulated gate dielectric layer 9 is formed on the inner wall of the recess 13 and the donor layer 8; the step of forming the source electrode 11 and the drain electrode 12 on the first high-conductivity layer 4 and the second high-conductivity layer 6 respectively specifically includes:
s71, as shown in FIG. 3 (i), al is deposited on the inner wall of the groove 13, the donor layer 8, and the first and second high guiding layers 4 and 5 2 O 3 、SiO 2 At least one of AlN and AlN to form an insulated gate dielectric film 9';
s72, as shown in (j) of FIG. 3, etching away the insulating gate dielectric film 9 'on the first high-conductivity layer 4 and the second high-conductivity layer 5, wherein the remaining insulating gate dielectric film 9' is the insulating gate dielectric layer 9;
s73, as shown in (k) of fig. 3, a first metal material is deposited on the first high-guiding layer 4 and the second high-guiding layer 5, respectively, to form a source electrode 11 and a drain electrode 12, respectively.
In particular, the drain electrode may be formed by depositing a first metal material on the first and second high guiding layers using a method including, but not limited to, electron beam evaporation or sputtering.
In some embodiments, the first metal material is selected from at least one of titanium, gold, aluminum, nickel, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten, but is not limited thereto.
After step S8, an annealing step is further included before step S9. The annealing is performed at 850-900 ℃ for 20-30 min. The annealing aims to enable the source electrode and the drain electrode to form ohmic contact with the first high-conductivity layer and the second high-conductivity layer respectively.
In step S9, in some embodiments, the step of forming a gate on the insulating gate dielectric layer specifically includes:
and depositing a second metal material on the insulated gate dielectric layer to form a gate. In particular, the gate electrode may be formed by depositing a second metal material on the first regulation layer using a method including, but not limited to, electron beam evaporation or sputtering.
In some embodiments, the second metal material is selected from at least one of nickel, gold, titanium, aluminum, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten, but is not limited thereto.
The following is a detailed description of specific examples.
Example 1
The embodiment provides a preparation method of a concave gate enhanced gallium oxide transistor, which comprises the following steps:
(1) As shown in FIG. 3 (a), ga is provided 2 O 3 Substrate 1, said Ga 2 O 3 Substrate 1 is Fe-doped beta-Ga 2 O 3 A high-resistance substrate with a thickness ofSequentially ultrasonically cleaning with acetone and isopropanol for 5min, washing with a large amount of deionized water, and drying with nitrogen;
(2) As shown in FIG. 3 (b), the MOCVD apparatus was used to produce TEGa and O 2 As a gallium source and oxygen source, siH 4 As a doping source, N is used as 2 Epitaxial growth at 800 ℃ with Ga as carrier gas 2 O 3 Ga having a thickness of 10 μm is formed on a substrate 1 2 O 3 Buffer layer 2, ga 2 O 3 Buffer layer 2 is Si doped beta-Ga 2 O 3 A buffer layer having an electron concentration of 5×10 16 Individual/cm 3 。
(3) As shown in FIG. 3 (c), the MOCVD apparatus was used to produce TEGa and O 2 As a gallium source and an oxygen source, N 2 Epitaxial growth at 800 ℃ with Ga as carrier gas 2 O 3 Ga with a thickness of 300nm is formed on the buffer layer 2 2 O 3 Channel layer 3, the Ga 2 O 3 The channel layer 3 is intrinsic beta-Ga 2 O 3 A channel layer;
(4) As shown in FIG. 3 (d), epitaxial growth was performed in Ga using an MBE apparatus 2 O 3 A first thin film 6' with a thickness of 1nm is formed on the channel layer 3, the first thin film being beta- (Al) 0.05 Ga 0.95 ) 2 O 3 A film;
(5) As shown in fig. 3 (e), epitaxial growth is performed by using an MBE apparatus to form a second thin film 7' having a thickness of 10nm, which is β - (Al), on the first thin film 6 0.2 Ga 0.8 ) 2 O 3 A film;
(6) As shown in FIG. 3 (f), in LPCVD equipment, an in-situ N plasma treatment is performed first, and then SiH is used 2 Cl 2 And NH 3 As a raw material, a third film 8 'having a thickness of 35nm, which is Si, is formed on the second film 7' by epitaxial growth at a deposition temperature of 800 DEG C 3 N 4 A film; ga 2 O 3 Two-dimensional electron gas is formed at the interface of the channel layer 3 and the first film 6', and positive charges are formed at the interface of the third film 8' and the second film 7 ';
(8) As shown in fig. 3 (g), etching is performed on the third film 8 'and the etching damage is repaired by wet etching to form a groove 13, the bottom of the groove 13 being abutted against the upper surface of the second film 7' (the width of the groove being Ga) 2 O 3 30% of the channel layer width);
(9) As shown in fig. 3 (h), si ions are implanted into both side regions of the first thin film 6', the second thin film 7', and the third thin film 8' as a whole, which are stacked (the implantation concentration of both sides is 1×10 19 Individual/cm 3 ) Activating by annealing at 900 ℃ for 20min to form a first high-guiding layer 4 and a second high-guiding layer 5 with the thickness of 46 nm; the regions of the first film 6', the second film 7', and the third film 8' into which the donor ions are not implanted, that is, the space layer 6, the barrier layer 7, and the donor layer 8, which are sequentially stacked, respectively;
(10) As shown in fig. 3 (i), al is deposited on the inner wall of the groove 13, the donor layer 8, and the first and second high guiding layers 4 and 5 by ALD process 2 O 3 Forming an insulating gate dielectric film 9' with the thickness of 30 nm;
(11) As shown in (j) of fig. 3, etching away the insulating gate dielectric film 9 'on the first high-conductivity layer 4 and the second high-conductivity layer 5, and opening the insulating gate dielectric of the source/drain region, wherein the remaining insulating gate dielectric film 9' which is not etched away is the insulating gate dielectric layer 9;
(12) As shown in fig. 3 (k), ti and Au are sequentially deposited on the first high-conductive layer 4 and the second high-conductive layer 5, respectively, to obtain a Ti layer having a thickness of 50nm and an Au layer having a thickness of 150nm, which are stacked, and the Ti layer and the Au layer are put into a stripping solution to be stripped by a lift-off stripping process, thereby forming a source electrode 11 and a drain electrode 12, respectively. The device prepared above is placed in a rapid thermal processing furnace and is placed in N 2 Annealing at 475 ℃ for 1min in the environment to form good ohmic contact;
(13) As shown in fig. 3 (l), ni and Au are sequentially deposited on the insulating gate dielectric layer 9 on the groove region by electron beam evaporation to obtain a layer of 50nm thick Ni and a layer of 150nm thick Au which are stacked, and the layers are put into a stripping solution and stripped by lift-off to form a gate electrode 10 on the insulating gate dielectric layer 9.
Example 2
The embodiment provides a preparation method of a concave gate enhanced gallium oxide transistor, which comprises the following steps:
(1) As shown in FIG. 3 (a), ga is provided 2 O 3 Substrate 1, said Ga 2 O 3 Substrate 1 is Fe-doped beta-Ga 2 O 3 The high-resistance substrate with the thickness of 100 mu m is sequentially ultrasonically cleaned for 5min by acetone and isopropanol respectively, then is rinsed by a large amount of deionized water, and is dried by nitrogen;
(2) As shown in FIG. 3 (b), the MOCVD apparatus was used to produce TEGa and O 2 As a gallium source and an oxygen source, N 2 Epitaxial growth at 800 ℃ with Ga as carrier gas 2 O 3 Ga 5 μm thick is formed on a substrate 1 2 O 3 Buffer layer 2, ga 2 O 3 Buffer layer 2 is unintentionally doped beta-Ga 2 O 3 A buffer layer having an electron concentration of 5×10 15 Individual/cm 3 ；
(3) As shown in FIG. 3 (c), the MOCVD apparatus was used to produce TEGa and O 2 As a gallium source and an oxygen source, N 2 Epitaxial growth at 800 ℃ with Ga as carrier gas 2 O 3 Ga with thickness of 100nm is formed on the buffer layer 2 2 O 3 Channel layer 3, the Ga 2 O 3 The channel layer 3 is intrinsic beta-Ga 2 O 3 A channel layer;
(4) As shown in FIG. 3 (d), epitaxial growth was performed in Ga using an MBE apparatus 2 O 3 A first thin film 6' with a thickness of 1nm is formed on the channel layer 3, the first thin film being beta- (Al) 0.03 Ga 0.97 ) 2 O 3 A film;
(5) As shown in fig. 3 (e), epitaxial growth is performed by using an MBE apparatus to form a second thin film 7' having a thickness of 20nm, which is β - (Al), on the first thin film 6 0.1 Ga 0.9 ) 2 O 3 A film;
(6) As shown in FIG. 3 (f), in the LPCVD apparatus, an in-situ N plasma is first performedSub-treatment with SiH 2 Cl 2 And NH 3 As a raw material, performing epitaxial growth at a deposition temperature of 700 ℃, and forming a third film 8 'having a thickness of 20nm on the second film 7', wherein the third film is Si 3 N 4 A film; ga 2 O 3 Two-dimensional electron gas is formed at the interface of the channel layer 3 and the first film 6', and positive charges are formed at the interface of the third film 8' and the second film 7 ';
(8) As shown in fig. 3 (g), etching is performed on the third film 8 'and the etching damage is repaired by wet etching to form a groove 13, the bottom of the groove 13 being abutted against the upper surface of the second film 7' (the width of the groove being Ga) 2 O 3 40% of the channel layer width);
(9) As shown in fig. 3 (h), si ions are implanted into both side regions of the first thin film 6', the second thin film 7', and the third thin film 8' as a whole, which are stacked, and extend to Ga 2 O 3 In the channel layer (implantation concentration of 1X 10 on both sides) 19 Individual/cm 3 ) Activating by annealing at 850 ℃ for 30min to form a first high-guiding layer 4 and a second high-guiding layer 5 with the thickness of 100 nm; the regions of the first film 6', the second film 7', and the third film 8' into which the donor ions are not implanted, that is, the space layer 6, the barrier layer 7, and the donor layer 8, which are sequentially stacked, respectively;
(10) As shown in fig. 3 (i), al is deposited on the inner wall of the groove 13, the donor layer 8, and the first and second high guiding layers 4 and 5 by ALD process 2 O 3 Forming an insulating gate dielectric film 9' with the thickness of 20 nm;
(11) As shown in (j) of fig. 3, etching away the insulating gate dielectric film 9 'on the first high-conductivity layer 4 and the second high-conductivity layer 5, and opening the insulating gate dielectric of the source/drain region, wherein the remaining insulating gate dielectric film 9' which is not etched away is the insulating gate dielectric layer 9;
(12) As shown in fig. 3 (k), ti and Au are sequentially deposited on the first high-guiding layer 4 and the second high-guiding layer 5, respectively, by electron beam evaporation to obtain a Ti layer with a thickness of 20nm and an Au layer with a thickness of 120nm, respectively, which are laminated, and put into a stripping solution to be stripped by lift-offAfter the peeling, the source electrode 11 and the drain electrode 12 are formed. The device prepared above is placed in a rapid thermal processing furnace and is placed in N 2 Annealing at 475 ℃ for 1min in the environment to form good ohmic contact;
(13) As shown in fig. 3 (l), ni and Au are sequentially deposited on the insulating gate dielectric layer 9 on the groove region by using an electron beam evaporation method, a Ni layer with a thickness of 20nm and an Au layer with a thickness of 120nm are obtained to be laminated, and the laminated layers are put into a stripping solution to be stripped by using a lift-off stripping process, and then a gate electrode 10 is formed on the insulating gate dielectric layer 9.
Example 3
The embodiment provides a preparation method of a concave gate enhanced gallium oxide transistor, which comprises the following steps:
(1) As shown in FIG. 3 (a), ga is provided 2 O 3 Substrate 1, said Ga 2 O 3 Substrate 1 is Fe-doped beta-Ga 2 O 3 The high-resistance substrate with the thickness of 650 mu m is sequentially cleaned by acetone and isopropanol for 5min respectively, then is rinsed by a large amount of deionized water, and is dried by nitrogen;
(2) As shown in FIG. 3 (b), the MOCVD apparatus was used to produce TEGa and O 2 As a gallium source and oxygen source, siH 4 As a doping source, N is used as 2 Epitaxial growth at 800 ℃ with Ga as carrier gas 2 O 3 Ga having a thickness of 10 μm is formed on a substrate 1 2 O 3 Buffer layer 2, ga 2 O 3 Buffer layer 2 is Si doped beta-Ga 2 O 3 A buffer layer having an electron concentration of 1×10 17 Individual/cm 3 ；
(3) As shown in FIG. 3 (c), the MOCVD apparatus was used to produce TEGa and O 2 As a gallium source and an oxygen source, N 2 Epitaxial growth at 800 ℃ with Ga as carrier gas 2 O 3 Ga with a thickness of 600nm is formed on the buffer layer 2 2 O 3 Channel layer 3, the Ga 2 O 3 The channel layer 3 is intrinsic beta-Ga 2 O 3 A channel layer;
(4) As shown in FIG. 3 (d), epitaxial growth was performed in Ga using an MBE apparatus 2 O 3 On the channel layer 3Forming a first film 6' having a thickness of 2nm, the first film being beta- (Al) 0.04 Ga 0.96 ) 2 O 3 A film;
(5) As shown in fig. 3 (e), epitaxial growth is performed by using an MBE apparatus to form a second thin film 7' having a thickness of 15nm, which is β - (Al), on the first thin film 6 0.15 Ga 0.85 ) 2 O 3 A film;
(6) As shown in FIG. 3 (f), in LPCVD equipment, an in-situ N plasma treatment is performed first, and then SiH is used 2 Cl 2 And NH 3 As a raw material, a third film 8 'having a thickness of 50nm, which is Si, was formed on the second film 7' by epitaxial growth at a deposition temperature of 750 DEG C 3 N 4 A film; ga 2 O 3 Two-dimensional electron gas is formed at the interface of the channel layer 3 and the first film 6', and positive charges are formed at the interface of the third film 8' and the second film 7 ';
(8) As shown in fig. 3 (g), etching is performed on the third film 8 'and the etching damage is repaired by wet etching to form a groove 13, the bottom of the groove 13 being abutted against the upper surface of the second film 7' (the width of the groove being Ga 2 O 3 25% of the channel layer width);
(9) As shown in fig. 3 (h), si ions are implanted into both side regions of the first thin film 6', the second thin film 7', and the third thin film 8' as a whole, which are stacked (the implantation concentration of both sides is 1×10 19 Individual/cm 3 ) Activating by annealing at 900 ℃ for 20min to form a first high-guiding layer 4 and a second high-guiding layer 5 with the thickness of 67 nm; the regions of the first film 6', the second film 7', and the third film 8' into which the donor ions are not implanted, that is, the space layer 6, the barrier layer 7, and the donor layer 8, which are sequentially stacked, respectively;
(10) As shown in fig. 3 (i), al is deposited on the inner wall of the groove 13, the donor layer 8, and the first and second high guiding layers 4 and 5 by ALD process 2 O 3 Forming an insulating gate dielectric film 9' with the thickness of 60 nm;
(11) As shown in (j) of fig. 3, etching away the insulating gate dielectric film 9 'on the first high-conductivity layer 4 and the second high-conductivity layer 5, and opening the insulating gate dielectric of the source/drain region, wherein the remaining insulating gate dielectric film 9' which is not etched away is the insulating gate dielectric layer 9;
(12) As shown in fig. 3 (k), ti and Au are sequentially deposited on the first high-conductive layer 4 and the second high-conductive layer 5, respectively, to obtain a Ti layer having a thickness of 50nm and an Au layer having a thickness of 150nm, which are stacked, and the Ti layer and the Au layer are put into a stripping solution to be stripped by a lift-off stripping process, thereby forming a source electrode 11 and a drain electrode 12, respectively. The device prepared above is placed in a rapid thermal processing furnace and is placed in N 2 Annealing at 475 ℃ for 1min in the environment to form good ohmic contact;
(13) As shown in fig. 3 (l), ni and Au are sequentially deposited on the insulating gate dielectric layer 9 on the groove region by electron beam evaporation to obtain a layer of 50nm thick Ni and a layer of 150nm thick Au which are stacked, and the layers are put into a stripping solution and stripped by lift-off to form a gate electrode 10 on the insulating gate dielectric layer 9.
It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (10)
1. A concave gate enhanced gallium oxide transistor is characterized by comprising Ga which are sequentially stacked 2 O 3 Substrate, ga 2 O 3 Buffer layer, ga 2 O 3 A channel layer;
further comprises:
a first high-conductivity layer and a second high-conductivity layer respectively arranged on the Ga 2 O 3 Opposite sides on the channel layer;
a space layer, a barrier layer and a donor layer sequentially stacked on the Ga 2 O 3 A channel layer disposed on and between the first and second high-guiding layers; the donor layer comprises a first semiconductor material, at least one of ions constituting the first semiconductor material is donor ionA seed; the donor layer is provided with a crystal orientation toward the Ga 2 O 3 A recess recessed in a substrate direction; the space layer and the Ga 2 O 3 Two-dimensional electron gas is arranged outside a projection area of the groove at the interface of the channel layer;
the insulated gate dielectric layer is arranged on the inner wall of the groove and the donor layer;
the grid electrode is arranged on the insulated gate dielectric layer;
and the source electrode and the drain electrode are respectively arranged on the first high-conductivity layer and the second high-conductivity layer.
2. The recessed gate enhancement gallium oxide transistor of claim 1, wherein the first semiconductor material comprises Si 3 N 4 、SiO 2 At least one of them.
3. The concave gate enhanced gallium oxide transistor according to claim 2, wherein the donor layer has a thickness of 20 to 50nm.
4. The recessed gate enhancement type gallium oxide transistor according to claim 1, wherein the material of the space layer and the barrier layer is each independently selected from Al-doped Ga 2 O 3 Or In-doped Ga 2 O 3 。
5. The recessed gate enhancement mode gallium oxide transistor of claim 4, wherein the Al is doped with Ga 2 O 3 The mole number of Al accounts for 0% -20% of the sum of mole numbers of Al and Ga, and 0% is not taken; or, the In is doped with Ga 2 O 3 The mole number of In accounts for 0% -20% of the sum of the mole numbers of In and Ga, and 0% is not taken.
6. The recessed gate enhancement mode gallium oxide transistor of claim 5, wherein the barrier layer has a thickness of 10-20 nm.
7. The concave gate enhanced gallium oxide transistor according to claim 1, wherein the first and second high-conductivity layers are each implanted with first donor ions.
8. The concave gate enhanced gallium oxide transistor according to claim 1, wherein the thickness of the space layer is 1-2 nm and/or the Ga 2 O 3 The thickness of the buffer layer is 5-10 mu m; and/or the Ga 2 O 3 The thickness of the channel layer is 100-600 nm.
9. The preparation method of the concave gate enhanced gallium oxide transistor is characterized by comprising the following steps:
providing Ga 2 O 3 A substrate;
at the Ga 2 O 3 Ga is formed on a substrate 2 O 3 A buffer layer;
at the Ga 2 O 3 Forming Ga on a buffer layer 2 O 3 A channel layer;
at the Ga 2 O 3 A first high-conductivity layer and a second high-conductivity layer are respectively formed on two opposite sides of the channel layer;
at the Ga 2 O 3 Forming a space layer, a barrier layer and a donor layer which are sequentially stacked on the channel layer and between the first high-guiding layer and the second high-guiding layer; the donor layer includes a first semiconductor material, at least one of ions constituting the first semiconductor material being a donor ion;
forming a donor layer in the Ga 2 O 3 A recess recessed in a substrate direction; the space layer and the Ga 2 O 3 Two-dimensional electron gas is arranged outside a projection area of the groove at the interface of the channel layer;
forming an insulated gate dielectric layer on the inner wall of the groove and the donor layer;
forming a source electrode and a drain electrode on the first high-conductivity layer and the second high-conductivity layer, respectively;
and forming a grid electrode on the insulated gate dielectric layer.
10. The method of claim 9, wherein the step of forming a donor layer on the barrier layer comprises:
in-situ N plasma treatment is carried out firstly, and Si is deposited on the barrier layer 3 N 4 、SiO 2 At least one of (a) and (b) forming a donor layer.
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| CN117438303B (en) * | 2023-11-28 | 2024-04-26 | 苏州摩尔镓芯半导体科技有限公司 | Semiconductor structure and preparation method thereof |
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