TW201513345A - Linear high-electron mobility transistor - Google Patents

Linear high-electron mobility transistor Download PDF

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TW201513345A
TW201513345A TW103129665A TW103129665A TW201513345A TW 201513345 A TW201513345 A TW 201513345A TW 103129665 A TW103129665 A TW 103129665A TW 103129665 A TW103129665 A TW 103129665A TW 201513345 A TW201513345 A TW 201513345A
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layer
algan
aluminum
algan layer
inaln
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TW103129665A
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Chinese (zh)
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Hua Quen Tserng
Tso Min Chou
Paul Saunier
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Triquint Semiconductor Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/432Heterojunction gate for field effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a gallium nitride (GaN) buffer layer formed on a substrate, an aluminum gallium nitride (AlGaN) layer formed on the GaN buffer layer, and an indium aluminum nitride barrier layer formed on the AlGaN layer. Other embodiments may also be described and/or claimed.

Description

線性高電子移動率電晶體 Linear high electron mobility transistor

本揭示內容的實施例大體上關於積體電路的領域,且更明確地說,關於線性高電子移動率電晶體以及製作方法。 Embodiments of the present disclosure are generally directed to the field of integrated circuits, and more particularly to linear high electron mobility transistors and methods of fabrication.

相關申請案 Related application

本申請案主張2013年9月3日提申的美國臨時專利申請案第61/873,306號的優先權,該案的標題為「線性高電子移動率電晶體(LINEAR HIGH-ELECTRON MOBILITY TRANSISTOR)」,本文以引用的方式將其完整揭示內容併入。 The present application claims priority to U.S. Provisional Patent Application Serial No. 61/873,306, filed on Sep. 3, 2013, which is entitled "LINEAR HIGH-ELECTRON MOBILITY TRANSISTOR", The entire disclosure is hereby incorporated by reference.

高電子移動率電晶體(High-Electron Mobility Transistor,HEMT)通常包含一被形成在具有不同能隙的兩個半導體材料之間的異質接面。舉例來說,高移動率電荷載子可以利用一寬能隙層(舉例來說,n型施體供應層)與一窄能隙層的異質接面來產生。於寬能隙氮化物電晶體的情況中,該些電荷能夠藉由自發性與壓電性極化來誘發,不需要在該寬能隙層中摻雜。電流通常被侷限在該些層的一介面處的一超窄通道,並且在源極終端與汲極終端之間流動,該電流受控於被施加至一閘極終端的電壓。 A High-Electron Mobility Transistor (HEMT) typically includes a heterojunction formed between two semiconductor materials having different energy gaps. For example, high mobility charge carriers can be generated using a wide gap layer (for example, an n-type donor supply layer) and a heterojunction of a narrow gap layer. In the case of a wide band gap nitride transistor, the charges can be induced by spontaneous and piezoelectric polarization without the need to dope in the wide band gap. The current is typically confined to an ultra-narrow channel at one interface of the layers and flows between the source terminal and the drain terminal, the current being controlled by the voltage applied to a gate terminal.

雖然異質結構場效電晶體可以從超高頻率(Ultra High Frequency,UHF)至毫米波頻率顯露適當的功率效能;不過,習知的裝置卻可能會因裝置非線性的關係而在提供線性放大器操作中遭遇困難。當此些電晶體被運用在需要線性放大的情況中時,可能必須提供外部電路以補償該些電晶體的非線性特性。 Although heterostructure field effect transistors can be from ultra high frequencies (Ultra High Frequency, UHF) to millimeter wave frequencies reveal appropriate power performance; however, conventional devices may encounter difficulties in providing linear amplifier operation due to device nonlinearity. When such transistors are used in situations where linear amplification is required, external circuitry may have to be provided to compensate for the non-linear characteristics of the transistors.

本發明的一項觀點係一種設備,其包括:一基板;一氮化鎵(GaN)緩衝層,其被形成在該基板上;一氮化鋁鎵(AlGaN)層,其被形成在該GaN緩衝層上,該AlGaN層的鋁濃度小於約15%;以及一氮化銦鋁(InAlN)阻障層,其被形成在該AlGaN層上,其中,該AlGaN層薄於該InAlN阻障層。 An aspect of the invention is an apparatus comprising: a substrate; a gallium nitride (GaN) buffer layer formed on the substrate; an aluminum gallium nitride (AlGaN) layer formed on the GaN On the buffer layer, the AlGaN layer has an aluminum concentration of less than about 15%; and an indium aluminum nitride (InAlN) barrier layer formed on the AlGaN layer, wherein the AlGaN layer is thinner than the InAlN barrier layer.

本發明的另一項觀點係一種方法,其包括:形成一氮化鎵(GaN)緩衝層在一基板上;形成一氮化鋁鎵(AlGaN)層在該GaN緩衝層上,該AlGaN層的厚度介於約40至60埃之間;形成一氮化銦鋁(InAlN)阻障層在該AlGaN層上;以及形成一閘極、源極、以及汲極在該InAlN阻障層上。 Another aspect of the present invention is a method comprising: forming a gallium nitride (GaN) buffer layer on a substrate; forming an aluminum gallium nitride (AlGaN) layer on the GaN buffer layer, the AlGaN layer The thickness is between about 40 and 60 angstroms; an indium aluminum nitride (InAlN) barrier layer is formed over the AlGaN layer; and a gate, a source, and a drain are formed on the InAlN barrier layer.

本發明的另一項觀點係一種系統,其包括:一收發器,用以傳送與接收射頻(RF)信號;以及一高電子移動率電晶體(HEMT),其被併入於該收發器裡面或是耦合該收發器,該HEMT包含:一基板;一氮化鎵(GaN)緩衝層,其被形成在該基板上;一氮化鋁鎵(AlGaN)層,其被形成在該GaN緩衝層上,該AlGaN層的鋁濃度小於約15%;以及一氮化銦鋁(InAlN)阻障層,其被形成在該AlGaN層上。 Another aspect of the present invention is a system comprising: a transceiver for transmitting and receiving radio frequency (RF) signals; and a high electron mobility transistor (HEMT) incorporated in the transceiver Or coupling the transceiver, the HEMT includes: a substrate; a gallium nitride (GaN) buffer layer formed on the substrate; an aluminum gallium nitride (AlGaN) layer formed on the GaN buffer layer The AlGaN layer has an aluminum concentration of less than about 15%; and an indium aluminum nitride (InAlN) barrier layer formed on the AlGaN layer.

100‧‧‧積體電路(IC)裝置 100‧‧‧Integrated circuit (IC) device

104‧‧‧基板 104‧‧‧Substrate

108‧‧‧堆疊 108‧‧‧Stacking

112‧‧‧GaN緩衝層 112‧‧‧GaN buffer layer

116‧‧‧氮化鋁鎵(AlGaN)層 116‧‧‧AlGaN layer

120‧‧‧AlN層 120‧‧‧AlN layer

124‧‧‧氮化銦鋁(InAlN)阻障層 124‧‧‧Indium Nitride (InAlN) barrier layer

126‧‧‧閘極絕緣體 126‧‧‧gate insulator

128‧‧‧閘極 128‧‧‧ gate

132‧‧‧源極 132‧‧‧ source

136‧‧‧汲極 136‧‧‧汲

200‧‧‧IC裝置的電子分佈圖 200‧‧‧Electrical distribution of IC devices

204‧‧‧第一IC裝置的電子分佈 204‧‧‧Electronic distribution of the first IC device

208‧‧‧第二IC裝置的電子分佈 208‧‧‧Electronic distribution of the second IC device

300‧‧‧IC裝置的能帶圖 300‧‧‧Energy diagram of IC device

304‧‧‧第一IC裝置的能帶圖 304‧‧‧Energy diagram of the first IC device

308‧‧‧第二IC裝置的能帶圖 308‧‧‧Energy band diagram of the second IC device

400‧‧‧IC裝置的電子分佈圖 400‧‧‧Electrical distribution of IC devices

404‧‧‧第一IC裝置的響應輪廓 404‧‧‧Response profile of the first IC device

408‧‧‧第二IC裝置的響應輪廓 408‧‧‧Response profile of the second IC device

500‧‧‧IC裝置的能帶圖 500‧‧‧Energy diagram of IC device

504‧‧‧第一IC裝置的響應輪廓 504‧‧‧Response profile of the first IC device

508‧‧‧第二IC裝置的響應輪廓 508‧‧‧Response profile of the second IC device

600‧‧‧以閘極電壓為函數的跨導gm的圖 600‧‧‧Figure of transconductance gm as a function of gate voltage

604‧‧‧和一線性IC裝置相關聯的響應輪廓 604‧‧‧ Response profile associated with a linear IC device

608‧‧‧和一習知裝置相關聯的響應輪廓 608‧‧‧ Response profile associated with a conventional device

800‧‧‧系統 800‧‧‧ system

802‧‧‧功率放大器(PA)模組 802‧‧‧Power Amplifier (PA) Module

804‧‧‧收發器 804‧‧‧ transceiver

806‧‧‧天線切換模組(ASM) 806‧‧‧Antenna Switching Module (ASM)

808‧‧‧天線結構 808‧‧‧Antenna structure

810‧‧‧功率調節器 810‧‧‧Power Regulator

配合隨附圖式將可藉由下面的詳細說明輕易地瞭解實施 例。為便利此說明,相同的元件符號代表相同的結構性元件。在隨附圖式的圖中透過範例圖解實施例,而沒有限制意義。 The implementation will be easily understood by the following detailed description. example. To facilitate this description, the same element symbols represent the same structural elements. Embodiments are illustrated by way of example in the figures of the drawings, without limitation.

圖1概略圖解根據各種實施例的一積體電路(Integrated Circuit,IC)裝置的剖視圖。 1 schematically illustrates a cross-sectional view of an integrated circuit (IC) device in accordance with various embodiments.

圖2所示的係根據各種實施例的IC裝置的電子分佈圖。 2 is an electronic distribution diagram of an IC device according to various embodiments.

圖3所示的係根據各種實施例的IC裝置的能帶圖。 3 is an energy band diagram of an IC device according to various embodiments.

圖4所示的係根據各種實施例的IC裝置的電子分佈圖。 4 is an electronic distribution diagram of an IC device according to various embodiments.

圖5所示的係根據各種實施例的IC裝置的能帶圖。 Figure 5 shows an energy band diagram of an IC device according to various embodiments.

圖6所示的係根據各種實施例之以閘極電壓為函數的跨導的圖。 Figure 6 is a diagram of a transconductance as a function of gate voltage in accordance with various embodiments.

圖7所示的係根據各種實施例之用於製作一積體電路裝置的方法的流程圖。 Figure 7 is a flow diagram of a method for fabricating an integrated circuit device in accordance with various embodiments.

圖8概略圖解根據各種實施例之包含一IC裝置的範例系統。 FIG. 8 diagrammatically illustrates an example system including an IC device in accordance with various embodiments.

本揭示內容的實施例提供一積體電路(IC)裝置(例如,舉例來說,高電子移動率電晶體(HEMT))的結構性配置、製作方法、以及系統。 Embodiments of the present disclosure provide a structural configuration, fabrication method, and system of an integrated circuit (IC) device, such as, for example, a high electron mobility transistor (HEMT).

在下面的詳細說明中會參考構成說明之一部分的隨附圖式,其中,所有圖式中的相同元件符號代表相同部件,且圖中藉由可以實行本揭示內容之主旨的解釋性實施例來顯示。應該瞭解的係,可以運用其它實施例,並且可以進行結構性或邏輯性變化,其並沒有脫離本揭示內容的範疇。所以,下面的詳細說明沒有限制的意義,而且,實施例的範疇係由隨附的申請專利範圍及它們的等效範圍來定義。 BRIEF DESCRIPTION OF THE DRAWINGS In the following detailed description, reference should be made to the claims in the claims display. Other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the embodiments is defined by the scope of the appended claims and their equivalents.

為達本揭示內容之目的,「A及/或B」一語的意義為(A)、(B)、 或是(A與B)。為達本揭示內容之目的,「A、B、及/或C」一語的意義為(A)、(B)、(C)、(A與B)、(A與C)、(B與C)、或是(A、B、以及C)。 For the purposes of this disclosure, the meaning of the terms "A and/or B" is (A), (B), Or (A and B). For the purposes of this disclosure, the meaning of the terms "A, B, and/or C" is (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

本說明可能使用到「於一實施例中」或是「於實施例中」等用語,每一個用語可以各自表示多個相同或不同實施例中的一或更多者。再者,關於本揭示內容之實施例所使用的「包括」、「包含」、「具有」、以及類似用詞為同義詞。 The description may use terms such as "in an embodiment" or "in an embodiment", each of which may denote one or more of the same or different embodiments. Further, the terms "including", "comprising", "having", and the like, as used in the embodiments of the present disclosure are synonymous.

本文中可能使用到「耦合」一詞及其衍生詞。「被耦合」可能意謂著下面之中的一或更多者。「被耦合」可能意謂著二或更多個元件直接物理性或電性接觸。然而,「被耦合」亦可能意謂著二或更多個元件彼此雖然間接接觸,但是仍然協同運作或是彼此互動;並且可能意謂著一或更多個其它元件被耦合或是被連接在被認為係彼此耦合的元件之間。 The term "coupling" and its derivatives may be used in this article. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still operate cooperatively or interact with each other; and may mean that one or more other elements are coupled or connected It is considered to be between components that are coupled to each other.

於各種實施例中,「一被形成在第二層上的第一層」一語可能意謂著該第一層被形成在該第二層上方,並且該第一層的至少一部分可以直接接觸(舉例來說,直接物理性及/或電性接觸)或是間接接觸(舉例來說,在該第一層與該第二層之間有一或更多其它層)該第二層的至少一部分。 In various embodiments, the phrase "a first layer formed on a second layer" may mean that the first layer is formed over the second layer, and at least a portion of the first layer may be in direct contact. (for example, direct physical and/or electrical contact) or indirect contact (for example, one or more other layers between the first layer and the second layer) at least a portion of the second layer .

圖1概略圖解根據各種實施例的一IC裝置100的剖視圖。舉例來說,該IC裝置100可以為一HEMT裝置。 FIG. 1 schematically illustrates a cross-sectional view of an IC device 100 in accordance with various embodiments. For example, the IC device 100 can be a HEMT device.

IC裝置100可以被製作在一基板104上。該基板104通常包含一支撐材料,其上沉積一層堆疊(或是簡稱「堆疊108」)。於一實施例中,該基板104包含矽(Si)、碳化矽(SiC)、氧化鋁(Al2O3)或藍寶石、氮化鎵(GaN)、及/或氮化鋁(AlN)。包含合宜II-VI族及III-V族半導體材料系統的其它材料亦能夠於其它實施例中用於該基板104。於一實施例中,該基板104可以由 能夠於其上磊晶成長一GaN緩衝層112之材料的任何材料或材料之組合構成。 The IC device 100 can be fabricated on a substrate 104. The substrate 104 typically includes a support material on which a stack (or simply "stack 108") is deposited. In one embodiment, the substrate 104 comprises germanium (Si), tantalum carbide (SiC), aluminum oxide (Al 2 O 3 ) or sapphire, gallium nitride (GaN), and/or aluminum nitride (AlN). Other materials comprising suitable II-VI and III-V semiconductor material systems can also be used in the substrate 104 in other embodiments. In one embodiment, the substrate 104 can be constructed of any material or combination of materials capable of epitaxially growing a GaN buffer layer 112.

被形成在基板104上的堆疊108可以包含由形成一或更多個異質接面/異質結構的不同材料系統組成的磊晶沉積層。堆疊108的該些層可於現場形成。也就是,堆疊108可在形成堆疊108之組成層的製造設備(舉例來說,一反應室)中被形成在基板104上,而不需要從該製造設備中移除基板104。 The stack 108 formed on the substrate 104 may comprise an epitaxial deposited layer composed of different material systems that form one or more heterojunction/heterostructures. The layers of stack 108 can be formed in the field. That is, the stack 108 can be formed on the substrate 104 in a fabrication facility (eg, a reaction chamber) that forms a constituent layer of the stack 108 without the need to remove the substrate 104 from the fabrication facility.

於其中一實施例中,IC裝置100的堆疊108包含被形成在基板104上的GaN緩衝層112。該GaN緩衝層112可以在基板104與堆疊108的其它層之間提供一晶體結構過渡區,從而充當一緩衝層或隔離層。舉例來說,GaN緩衝層112可以在基板104與其它晶格不匹配的材料之間提供應力釋放。該GaN緩衝層112可以與基板104磊晶耦合。於其它實施例中,一凝核層(例如,AlN,圖中並未顯示)可以插入於該基板104與該GaN緩衝層112之間。 In one embodiment, the stack 108 of IC devices 100 includes a GaN buffer layer 112 formed on a substrate 104. The GaN buffer layer 112 can provide a crystal structure transition region between the substrate 104 and other layers of the stack 108 to act as a buffer or isolation layer. For example, GaN buffer layer 112 can provide stress relief between substrate 104 and other lattice mismatched materials. The GaN buffer layer 112 can be epitaxially coupled to the substrate 104. In other embodiments, a nucleation layer (eg, AlN, not shown) may be interposed between the substrate 104 and the GaN buffer layer 112.

於某些實施例中,GaN緩衝層112的厚度從約1至2微米。如本文中的用法,某一層的厚度係指該層在實質上垂直於基板104的一主要表面的方向中的大小。該GaN緩衝層112可以於其它實施例中包含其它合宜材料及/或厚度。於某些實施例中,該GaN緩衝層112可以沒有被摻雜。 In some embodiments, the GaN buffer layer 112 has a thickness of from about 1 to 2 microns. As used herein, the thickness of a layer refers to the size of the layer in a direction substantially perpendicular to a major surface of the substrate 104. The GaN buffer layer 112 can include other suitable materials and/or thicknesses in other embodiments. In some embodiments, the GaN buffer layer 112 may not be doped.

堆疊108可以進一步包含:一氮化鋁鎵(AlGaN)層116,其被形成在該GaN緩衝層112上;一AlN層120,其被形成在該AlGaN層116上;一氮化銦鋁(InAlN)阻障層124,其被形成在該AlN層120上;以及一閘極絕緣體126,其被形成在該InAlN阻障層上。 The stack 108 may further include: an aluminum gallium nitride (AlGaN) layer 116 formed on the GaN buffer layer 112; an AlN layer 120 formed on the AlGaN layer 116; an indium aluminum nitride (InAlN) a barrier layer 124 formed on the AlN layer 120; and a gate insulator 126 formed on the InAlN barrier layer.

IC裝置100可以進一步包含一閘極128,其被形成在閘極絕緣體126上。該閘極128可以充當IC裝置100的一連接終端。該閘極128可以直接耦合閘極絕緣體126。該閘極128通常係由一導電材料(例如,金屬)構成。於某些實施例中,該閘極128可以為鎳(Ni)、鉑(Pt)、銥(Ir)、鉬(Mo)、金(Au)、及/或鋁(Al)。 The IC device 100 can further include a gate 128 formed on the gate insulator 126. The gate 128 can serve as a connection terminal of the IC device 100. The gate 128 can be directly coupled to the gate insulator 126. The gate 128 is typically constructed of a conductive material (e.g., metal). In some embodiments, the gate 128 can be nickel (Ni), platinum (Pt), iridium (Ir), molybdenum (Mo), gold (Au), and/or aluminum (Al).

IC裝置100可以進一步包含被形成在閘極絕緣體126上的一源極132與汲極136。於某些實施例中,該源極132與汲極136可以藉由實施歐姆凹部(ohmic recess)而延伸貫穿堆疊108的一或更多層,舉例來說,往下抵達GaN緩衝層112。該源極132與該汲極136可以為歐姆接點。該源極132與該汲極136可以為再成長的接點,其可以提供比標準成長的接點相對為低的接觸阻值。於實施例中,該源極132與該汲極136的接觸阻值可以為約0.01ohm.mm。 The IC device 100 can further include a source 132 and a drain 136 formed on the gate insulator 126. In some embodiments, the source 132 and the drain 136 may extend through one or more layers of the stack 108 by performing an ohmic recess, for example, down to the GaN buffer layer 112. The source 132 and the drain 136 may be ohmic contacts. The source 132 and the drain 136 can be re-growth contacts that can provide a relatively low contact resistance compared to standard grown contacts. In an embodiment, the contact resistance of the source 132 and the drain 136 may be about 0.01 ohm. Mm.

該源極132與該汲極136可以各自由一導電材料(例如,金屬)所構成。於一實施例中,該源極132與該汲極136中的每一者可以包含鈦(Ti)、鋁(Al)、鉬(Mo)、金(Au)、及/或矽(Si)。於其它實施例中亦能夠使用其它材料。 The source 132 and the drain 136 may each be formed of a conductive material (eg, metal). In one embodiment, each of the source 132 and the drain 136 may comprise titanium (Ti), aluminum (Al), molybdenum (Mo), gold (Au), and/or germanium (Si). Other materials can also be used in other embodiments.

一異質接面可以被形成在該InAlN阻障層124與該GaN緩衝層112之間。該InAlN阻障層124的能隙能量可以大於該GaN緩衝層112的能隙能量。該InAlN阻障層124可以為一供應移動電荷載子的較寬能隙層,而GaN緩衝層112可以係為該些移動電荷載子提供一通道的較窄能隙層。 A heterojunction may be formed between the InAlN barrier layer 124 and the GaN buffer layer 112. The energy gap energy of the InAlN barrier layer 124 may be greater than the energy gap energy of the GaN buffer layer 112. The InAlN barrier layer 124 can be a wider energy gap layer that supplies mobile charge carriers, and the GaN buffer layer 112 can provide a narrower energy gap layer for the mobile charge carriers.

AlGaN層116可以被定位在該InAlN阻障層124與該GaN緩 衝層112之間,用以改善線性度。明確地說,該AlGaN層116可以在IC裝置100的操作期間(舉例來說,當一電壓被施加至閘極128時)於GaN緩衝層112處促成一極化誘發的通道,從而形成一垂直延伸在該通道之中的三維電子氣(Three-Dimensional Electron Gas,3DEG)。舉例來說,這可以允許電流(移動電荷載子)在該源極132與該汲極136之間流動。此延伸的電子氣可以導致實質上恆定的跨導對閘極電壓輪廓。結果,該IC裝置100可以和一更線性的操作及低振幅調變至振幅調變(AM-to-AM)失真相關聯。 The AlGaN layer 116 can be positioned on the InAlN barrier layer 124 and the GaN Between the layers 112 to improve linearity. In particular, the AlGaN layer 116 can contribute to a polarization induced channel at the GaN buffer layer 112 during operation of the IC device 100 (for example, when a voltage is applied to the gate 128), thereby forming a vertical Three-Dimensional Electron Gas (3DEG) extending in the channel. For example, this may allow current (mobile charge carriers) to flow between the source 132 and the drain 136. This extended electron gas can result in a substantially constant transconductance versus gate voltage profile. As a result, the IC device 100 can be associated with a more linear operation and low amplitude modulation to amplitude modulation (AM-to-AM) distortion.

AlN層120可被用來藉由降低因一底層(舉例來說,AlGaN層116)之粗糙表面所導致的合金散射而增強電子移動率。 The AlN layer 120 can be used to enhance electron mobility by reducing alloy scattering caused by the rough surface of a bottom layer (for example, AlGaN layer 116).

閘極絕緣體126(當存在時)可以當作InAlN阻障層124與閘極128之間的絕緣層,該閘極128會經由該閘極絕緣體126來電容耦合該InAlN阻障層124。這可以形成一金屬-絕緣體-半導體(Metal-Insulator-Semiconductor,MIS)結構或是一金屬-氧化物-半導體結構。於各種實施例中,該閘極絕緣體126可以幫助提供較低的閘極洩漏以及較高的崩潰電壓。除了提供較低的閘極洩漏以及較高的崩潰電壓之外,此結構還可以具有以相對小的閘極-源極電容變化在寬廣的閘極電壓擺動範圍中達成實質上恆定增益gm的優點,其對應於相對小的振幅調變至相位調變(AM-to-PM)失真。該閘極絕緣體126能夠為在相對低溫度處(舉例來說,500℃或600℃)成長的現場成長GaN或AlN,其可以導至極高電阻係數之具有多晶結構的材料。該閘極絕緣體126可以包含GaN、AlN、Al2O3、氧化鑭(La2O3)、氮化矽、二氧化矽、或是任何其它合宜的介電材料。 The gate insulator 126 (when present) can serve as an insulating layer between the InAlN barrier layer 124 and the gate 128 via which the gate 128 is capacitively coupled to the InAlN barrier layer 124. This can form a Metal-Insulator-Semiconductor (MIS) structure or a metal-oxide-semiconductor structure. In various embodiments, the gate insulator 126 can help provide lower gate leakage and higher breakdown voltage. In addition to providing a low gate leakage and high breakdown voltages outside this structure may also have a relatively small gate - source capacitance variation substantially constant gain g m reached in a wide range of gate voltage swing of An advantage, which corresponds to a relatively small amplitude modulation to phase modulation (AM-to-PM) distortion. The gate insulator 126 can be a field grown GaN or AlN grown at relatively low temperatures (for example, 500 ° C or 600 ° C), which can lead to a material having a polycrystalline structure with a very high resistivity. The gate insulator 126 may comprise GaN, AlN, Al 2 O 3 , lanthanum oxide (La 2 O 3 ), tantalum nitride, hafnium oxide, or any other suitable dielectric material.

於某些實施例中,閘極絕緣體126的厚度可以小於約50埃, 舉例來說,18埃,InAlN阻障層124的厚度可以為約80埃,AlN層120的厚度可以為約10埃,以及AlGaN層116的厚度可以為約40至60埃。 In some embodiments, the gate insulator 126 can have a thickness of less than about 50 angstroms. For example, 18 angstroms, the thickness of the InAlN barrier layer 124 can be about 80 angstroms, the thickness of the AlN layer 120 can be about 10 angstroms, and the thickness of the AlGaN layer 116 can be about 40 to 60 angstroms.

於各種實施例中,AlGaN層116可以有固定或緩變的鋁含量。舉例來說,於其中一實施例中,該AlGaN層116可以具有依照AlxGa1-xN的材料濃度,其中,x為代表鋁與鎵之相對數量的數值。於某些實施例中,x的數值為約0至0.15。於一具有固定鋁含量的實施例中,該AlGaN層116可以在該層的整個厚度中具有Al0.04Ga0.96N的相對材料濃度。於此實施例中,舉例來說,該AlGaN層116可以有約40埃的厚度。於一具有緩變鋁含量的實施例中,在GaN緩衝層112旁邊的AlGaN層116的一部分處的x可以為0並且可以逐漸增加至在AlN層120旁邊的AlGaN層116的一部分處的約0.15。於此實施例中,舉例來說,該AlGaN層116可以有約50埃的厚度。於其它實施例中亦能夠使用x的其它數值或是其它緩變結構。 In various embodiments, the AlGaN layer 116 can have a fixed or slowly varying aluminum content. For example, in one embodiment, the AlGaN layer 116 can have a material concentration in accordance with Al x Ga 1-x N, where x is a value representing the relative amount of aluminum and gallium. In certain embodiments, the value of x is from about 0 to 0.15. In an embodiment having a fixed aluminum content, the AlGaN layer 116 can have a relative material concentration of Al 0.04 Ga 0.96 N throughout the thickness of the layer. In this embodiment, for example, the AlGaN layer 116 can have a thickness of about 40 angstroms. In an embodiment having a graded aluminum content, x at a portion of the AlGaN layer 116 beside the GaN buffer layer 112 may be zero and may be gradually increased to about 0.15 at a portion of the AlGaN layer 116 beside the AlN layer 120. . In this embodiment, for example, the AlGaN layer 116 can have a thickness of about 50 angstroms. Other values of x or other slowly varying structures can also be used in other embodiments.

圖2所示的係根據各種實施例的IC裝置(舉例來說,IC裝置100)的電子分佈圖200。明確地說,圖200顯示一第一IC裝置的電子分佈204以及一第二IC裝置的電子分佈208。為達圖200之測量的目的,該第一IC裝置可以包含一30埃的閘極絕緣體(舉例來說,一GaN蓋部);一80埃的InAlN阻障層,銦的濃度為0.17;一10埃的AlN層;以及一40埃的AlGaN層,鋁的濃度為0.04。該第二IC裝置可以雷同於該第一IC裝置;不過,可能不包含該閘極絕緣體。 2 is an electronic distribution diagram 200 of an IC device (eg, IC device 100) in accordance with various embodiments. In particular, diagram 200 shows an electronic distribution 204 of a first IC device and an electronic distribution 208 of a second IC device. For the purpose of measuring the graph 200, the first IC device may include a 30 angstrom gate insulator (for example, a GaN cap portion); an 80 angstrom InAlN barrier layer having a concentration of indium of 0.17; A 10 angstrom AlN layer; and a 40 angstrom AlGaN layer have an aluminum concentration of 0.04. The second IC device can be identical to the first IC device; however, the gate insulator may not be included.

圖3所示的係根據各種實施例的IC裝置(舉例來說,IC裝置100)的能帶圖300。明確地說,圖300顯示上面針對圖2所述的第一IC裝置的能帶圖304以及上面針對圖2所述的第二IC裝置的能帶圖308。 3 is an energy band diagram 300 of an IC device (for example, IC device 100) in accordance with various embodiments. In particular, diagram 300 shows an energy band diagram 304 of the first IC device described above with respect to FIG. 2 and an energy band diagram 308 of the second IC device described above with respect to FIG.

圖2與3的電子分佈圖與能帶圖證實本發明的裝置相較於習知裝置在垂直方向中有延伸及較廣的電子分佈。這可以導致在高射頻(Radio Frequency,RF)輸入驅動位準處提高線性能力與功率效能。 The electronic distribution and energy band diagrams of Figures 2 and 3 demonstrate that the apparatus of the present invention has an extended and wider distribution of electrons in the vertical direction than conventional apparatus. This can result in improved linearity and power performance at high radio frequency (RF) input drive levels.

圖4所示的係根據各種實施例的IC裝置(舉例來說,IC裝置100)的電子分佈圖400。明確地說,圖400顯示一第一IC裝置的響應輪廓404以及一第二IC裝置的響應輪廓408。為達圖400之測量的目的,該第一IC裝置可以包含一30埃的閘極絕緣體(舉例來說,一GaN蓋部);一80埃的InAlN阻障層,銦的濃度為0.17;一10埃的AlN層;以及一50埃的AlGaN層,其緩變的鋁濃度為0至0.15。該第二IC裝置可以雷同於圖4的第一IC裝置;不過,可能不包含該閘極絕緣體。 4 is an electronic distribution diagram 400 of an IC device (eg, IC device 100) in accordance with various embodiments. In particular, diagram 400 shows a response profile 404 of a first IC device and a response profile 408 of a second IC device. For the purpose of measuring 400, the first IC device may include a 30 angstrom gate insulator (for example, a GaN cap portion); an 80 angstrom InAlN barrier layer having a concentration of indium of 0.17; A 10 angstrom AlN layer; and a 50 angstrom AlGaN layer have a graded aluminum concentration of 0 to 0.15. The second IC device can be identical to the first IC device of FIG. 4; however, the gate insulator may not be included.

圖5所示的係根據各種實施例的IC裝置(舉例來說,IC裝置100)的能帶圖500。明確地說,圖500顯示上面針對圖4所述的第一IC裝置的響應輪廓504以及上面針對圖4所述的第二IC裝置的響應輪廓508。 Figure 5 shows an energy band diagram 500 of an IC device (e.g., IC device 100) in accordance with various embodiments. In particular, graph 500 shows the response profile 504 of the first IC device described above with respect to FIG. 4 and the response profile 508 of the second IC device described above with respect to FIG.

雷同於圖2與3的響應輪廓,圖4與5的響應輪廓證實本發明的裝置相較於習知裝置在垂直方向中有延伸及較廣的電子分佈。 Similar to the response profiles of Figures 2 and 3, the response profiles of Figures 4 and 5 demonstrate that the apparatus of the present invention has an extended and wider distribution of electrons in the vertical direction than conventional devices.

圖6所示的係根據各種實施例之以閘極電壓為函數的跨導gm的圖600。明確地說,圖600圖解可以和一線性IC裝置(舉例來說,IC裝置100)相關聯的響應輪廓604,其對照於可以和一習知裝置相關聯的響應輪廓608。如能夠在圖中所見,對照於響應輪廓608,響應輪廓604相對於閘極電壓呈現較廣且更恆定的跨導gm。因此,對照於習知裝置,IC裝置100可以有改善的裝置線性度以及較高的飽和輸出功率位準。 Figure 6 shows a graph 600 of transconductance gm as a function of gate voltage, in accordance with various embodiments. In particular, diagram 600 illustrates a response profile 604 that can be associated with a linear IC device (e.g., IC device 100) that is responsive to a response profile 608 that can be associated with a conventional device. As can be seen in the figure, in response to the contour 608, the response profile 604 exhibits a wider and more constant transconductance gm with respect to the gate voltage. Thus, IC device 100 can have improved device linearity and a higher saturation output power level than conventional devices.

圖7所示的係根據各種實施例之用於製作一IC裝置(舉例來 說,圖1的IC裝置100)的方法700的流程圖。方法700包含:在704處,於一基板(舉例來說,基板104)上形成一緩衝層(舉例來說,GaN緩衝層112);在708處,於該緩衝層上形成一AlGaN層(舉例來說,AlGaN層116);在712處,於該AlGaN層上形成一AlN層(舉例來說,AlN層120);在716處,於該AlN層上形成一阻障層(舉例來說,InAlN阻障層124);在720處,於該阻障層上形成一閘極絕緣體(舉例來說,閘極絕緣體126);以及在724處,分別形成一閘極、源極、以及汲極(舉例來說,閘極128、源極132、以及汲極136)。於某些實施例中,該閘極可以被形成在該閘極絕緣體上,而該源極與汲極可以被形成在一堆疊的下方層上。於各種實施例中,其它層可以被形成用以插入在此些層之間。 7 is used to fabricate an IC device according to various embodiments (for example A flowchart of a method 700 of the IC device 100) of FIG. The method 700 includes, at 704, forming a buffer layer (eg, GaN buffer layer 112) on a substrate (eg, substrate 104); at 708, forming an AlGaN layer on the buffer layer (for example In other words, the AlGaN layer 116); at 712, an AlN layer (for example, the AlN layer 120) is formed on the AlGaN layer; and at 716, a barrier layer is formed on the AlN layer (for example, InAlN barrier layer 124); at 720, a gate insulator (for example, gate insulator 126) is formed on the barrier layer; and at 724, a gate, a source, and a drain are respectively formed (For example, gate 128, source 132, and drain 136). In some embodiments, the gate can be formed on the gate insulator, and the source and drain can be formed on a lower layer of the stack. In various embodiments, other layers may be formed for insertion between such layers.

根據各種實施例,一或更多層可以藉由下面的方式被磊晶沉積:分子射束磊晶(Molecular Beam Epitaxy,MBE)、原子層磊晶(Atomic Layer Epitaxy,ALE)、化學射束磊晶(Chemical Beam Epitaxy,CBE)、及/或金屬有機化學氣相沉積(Metal-Organic Chemical Vapor Deposition,MOCVD)。於其它實施例中亦能使用其它合宜的沉積技術。該堆疊的該些層的材料及/或厚度可以和已經配合圖1的IC裝置100所述的實施例相符。 According to various embodiments, one or more layers may be epitaxially deposited by the following methods: Molecular Beam Epitaxy (MBE), Atomic Layer Epitaxy (ALE), Chemical Beam Lei Chemical Beam Epitaxy (CBE), and/or Metal-Organic Chemical Vapor Deposition (MOCVD). Other suitable deposition techniques can also be used in other embodiments. The materials and/or thicknesses of the layers of the stack may be consistent with the embodiments already described in connection with IC device 100 of FIG.

該源極與該汲極可以藉由再成長製程(re-growth process)來形成,用以提供具有低接觸阻值或低導通阻值的歐姆接點。於該再成長製程中,材料可以在要形成該源極與該汲極的區域中被選擇性移除(舉例來說,蝕刻)。一高度摻雜的材料(舉例來說,n++材料)可以被沉積在該些層已經被被選擇性移除的區域之中。於某些實施例中,該源極與汲極的該高度摻雜材料可以為和用於該緩衝層或阻障層之材料雷同的材料。舉例來說,於該 緩衝包含GaN的系統中,一被矽(Si)高度摻雜的以GaN為基礎的材料可以被磊晶沉積在該些選擇性移除的區域之中,達到400至700埃的厚度。該高度摻雜的材料能夠藉由MBE、ALE、CBE、MOCVD、或是它們的合宜組合被磊晶沉積。於其它實施例中亦能夠針對該高度摻雜的材料使用其它材料、厚度、或是沉積技術。舉例來說,一或更多個金屬(舉例來說,其包含鈦(Ti)及/或金(Au))會利用掀離製程(lift-off process)以厚度1000埃至1500埃被形成在/被沉積在該高度摻雜的材料上。於其它實施例中亦能夠針對該一或更多個金屬使用其它材料、厚度、及/或技術。 The source and the drain may be formed by a re-growth process to provide an ohmic contact having a low contact resistance or a low on-resistance. In the re-growth process, material may be selectively removed (eg, etched) in the region where the source and the drain are to be formed. A highly doped material (for example, n++ material) can be deposited in regions where the layers have been selectively removed. In some embodiments, the highly doped material of the source and drain may be the same material as that used for the buffer or barrier layer. For example, in the In systems that buffer GaN, a GaN-based material that is highly doped with germanium (Si) can be epitaxially deposited in the selectively removed regions to a thickness of 400 to 700 angstroms. The highly doped material can be epitaxially deposited by MBE, ALE, CBE, MOCVD, or a suitable combination thereof. Other materials, thicknesses, or deposition techniques can also be used for this highly doped material in other embodiments. For example, one or more metals (for example, including titanium (Ti) and/or gold (Au)) may be formed at a thickness of 1000 angstroms to 1500 angstroms using a lift-off process. / deposited on the highly doped material. Other materials, thicknesses, and/or techniques can also be used with the one or more metals in other embodiments.

於某些實施例中,該源極與該汲極可以藉由植入製程被形成,其使用植入技術來引入雜質(舉例來說,矽),用以在該源極與該汲極之中提供一高度摻雜的材料。在植入之後,該源極與該汲極會在高溫處(舉例來說,1100至1200℃)被退火。該再成長製程可以較佳地避免和植入後退火相關聯的高溫。 In some embodiments, the source and the drain can be formed by an implantation process that uses implant technology to introduce impurities (eg, germanium) for the source and the drain A highly doped material is provided. After implantation, the source and the drain are annealed at a high temperature (for example, 1100 to 1200 ° C). This re-growth process can preferably avoid high temperatures associated with post-implant annealing.

該閘極可以藉由於該閘極絕緣體上沉積一導電材料而被形成在該閘極絕緣體上。該閘極材料能夠藉由任何合宜的沉積製程被沉積,舉例來說,其包含蒸發、原子層沉積(Atomic Layer Deposition,ALD)、及/或化學氣相沉積(Chemical Vapor Deposition,CVD)。 The gate can be formed on the gate insulator by depositing a conductive material on the gate insulator. The gate material can be deposited by any suitable deposition process, for example, including evaporation, Atomic Layer Deposition (ALD), and/or Chemical Vapor Deposition (CVD).

各種操作雖然依照最有助於瞭解本發明所主張之主旨的方式被描述為依序的多個分離操作;然而,說明的順序不應被視為隱喻此些操作必定為順序相依。明確地說,此些操作可以不依照呈現的順序來實施。本文所述的操作可以和所述實施例不同的順序來實施。於額外的實施例中可以實施各種額外的操作及/或省略已述的操作。 The various operations are described as a plurality of separate operations in a sequential manner in a manner that is most helpful in understanding the subject matter of the present invention; however, the order of the description should not be considered as a metaphor such operations must be sequential dependent. In particular, such operations may not be implemented in the order presented. The operations described herein can be implemented in a different order than the described embodiments. Various additional operations may be implemented and/or the operations described above may be omitted in additional embodiments.

一以InAlN/GaN為基礎的裝置(例如,IC裝置100)可以具有優於其它習知裝置(舉例來說,AlGaN/GaN結構)的數項優點。舉例來說,藉由在該InAlN阻障層之中提供約17%的銦濃度可以出現所希望的晶格匹配。這可以減少應變,其可以導致可靠度提高、較高的自發性極化電荷密度、在較高的電子濃度中有較大的能隙不連續性、以及較高的電子飽和速度。所有此結果皆可促成高於其它裝置的電流容量(current capacity)。這可特別實用於行動無線、基地台、有線TV、mmW通信、…等的線性功率及低雜訊放大器中。 An InAlN/GaN based device (e.g., IC device 100) can have several advantages over other conventional devices (e.g., AlGaN/GaN structures). For example, the desired lattice matching can occur by providing an indium concentration of about 17% in the InAlN barrier layer. This can reduce strain, which can result in increased reliability, higher spontaneous polarization charge density, greater energy gap discontinuities in higher electron concentrations, and higher electron saturation rates. All of this result can contribute to higher current capacity than other devices. This can be especially useful in linear power and low noise amplifiers for mobile wireless, base stations, cable TV, mmW communications, etc.

一IC裝置(舉例來說,IC裝置100)可被併入於各種設備與系統之中。圖8中所示的係一範例系統800的方塊圖。如圖示,系統800包含一功率放大器(Power Amplifier,PA)模組802,於某些實施例中,其可能係一射頻(RF)PA模組。該系統800可以包含一收發器804,其如圖示般地耦合功率放大器模組802。該功率放大器模組802可以包含IC裝置,舉例來說,本文中所述的IC裝置100。 An IC device (for example, IC device 100) can be incorporated into various devices and systems. A block diagram of an example system 800 is shown in FIG. As shown, system 800 includes a Power Amplifier (PA) module 802, which in some embodiments may be a radio frequency (RF) PA module. The system 800 can include a transceiver 804 that couples the power amplifier module 802 as shown. The power amplifier module 802 can include an IC device, such as the IC device 100 described herein.

功率放大器模組802可以從收發器804處接收一RF輸入信號RFin。該功率放大器模組802可以放大該RF輸入信號RFin,用以提供RF輸出信號RFout。該RF輸入信號RFin與該RF輸出信號RFout兩者皆可以為一傳送鏈路的一部分,在圖8中分別以Tx-RFin及Tx-RFout來表示。 Power amplifier module 802 can receive an RF input signal RFin from transceiver 804. The power amplifier module 802 can amplify the RF input signal RFin to provide an RF output signal RFout. Both the RF input signal RFin and the RF output signal RFout can be part of a transmission link, represented by Tx-RFin and Tx-RFout, respectively, in FIG.

該RF輸出信號RFout可以被提供至一天線切換模組(Antenna Switch Module,ASM)806,其透過一天線結構808來實行該RF輸出信號RFout的空中(Over-The-Air,OTA)傳送。該ASM 806亦可以透過天線結構808接收RF信號並且將該些已接收的RF信號Rx沿著一接收鏈路耦合至收發器 804。於某些實施例中,舉例來說,該收發器804可以額外地/替代地將該IC裝置100併入於一低雜訊放大器之中。 The RF output signal RFout can be provided to an Antenna Switch Module (ASM) 806 that performs an Over-The-Air (OTA) transmission of the RF output signal RFout through an antenna structure 808. The ASM 806 can also receive RF signals through the antenna structure 808 and couple the received RF signals Rx along a receive link to the transceiver. 804. In some embodiments, for example, the transceiver 804 can additionally/alternatively incorporate the IC device 100 into a low noise amplifier.

於各種實施例中,天線結構808可以包含一或更多個有向性及/或全向性天線,舉例來說,其包含雙極天線、單極天線、貼片天線、迴路天線、微帶天線、或是適合用於RF信號之OTA傳送/接收的任何其它類型天線。 In various embodiments, antenna structure 808 can include one or more directional and/or omnidirectional antennas, for example, including dipole antennas, monopole antennas, patch antennas, loop antennas, microstrips Antenna, or any other type of antenna suitable for OTA transmission/reception of RF signals.

於某些實施例中,系統800可以包含一功率調節器810,其額外地/替代地包含一IC裝置(例如,IC裝置100)。該功率調節器810可以耦合並且提供功率給系統800的各種器件,例如,該些器件包含,但是並不受限於PA模組802以及收發器804。於此些實施例中,該IC裝置100可以提供一用於功率切換應用的有效切換裝置,該些功率切換應用包含功率調節應用,例如,舉例來說,交流(Alternating Current,AC)-直流(Direct Current,DC)轉換器、DC-DC轉換器、DC-AC轉換器、以及類似物。 In some embodiments, system 800 can include a power conditioner 810 that additionally/alternatively includes an IC device (eg, IC device 100). The power conditioner 810 can couple and provide power to various devices of the system 800, for example, but not limited to the PA module 802 and the transceiver 804. In these embodiments, the IC device 100 can provide an effective switching device for a power switching application, the power switching application including a power conditioning application, such as, for example, alternating current (AC)-direct current (AC) Direct Current, DC) converters, DC-DC converters, DC-AC converters, and the like.

於各種實施例中,系統800可以特別使用於高射頻功率與頻率處的功率放大。舉例來說,系統800可以適用於陸地與衛星通信中的任何一或更多者、雷達系統,並且可能適用於各種工業與醫療應用中。更明確地說,於各種實施例中,系統800可以為下面之中的一選定裝置:雷達裝置、衛星通信裝置、行動手機、蜂巢式電話基地台、廣播無線電、或是電視放大器系統。 In various embodiments, system 800 can be used in particular for power amplification at high RF power and frequency. For example, system 800 can be adapted to any one or more of terrestrial and satellite communications, radar systems, and may be suitable for use in a variety of industrial and medical applications. More specifically, in various embodiments, system 800 can be one of the following: a radar device, a satellite communication device, a mobile handset, a cellular telephone base station, a broadcast radio, or a television amplifier system.

本文中雖然已經圖解及說明特定實施例以達說明的目的;不過,可以各式各樣適合達成相同目的的替代及/或等效實施例或施行方式來取代本文中所示與所述的實施例,其並沒有脫離本揭示內容的範疇。本申 請案希望涵蓋本文中討論的實施例的任何改變或變異。所以,顯見地,本文中所述的實施例不希望僅受限於申請專利範圍及其等效範圍。 The specific embodiments have been illustrated and described herein for illustrative purposes; however, various alternatives and/or equivalent embodiments or implementations may be substituted for the same purpose. For example, it does not depart from the scope of the present disclosure. Ben Shen The request is intended to cover any variations or variations of the embodiments discussed herein. Therefore, it is obvious that the embodiments described herein are not intended to be limited only by the scope of the claims and their equivalents.

100‧‧‧積體電路(IC)裝置 100‧‧‧Integrated circuit (IC) device

104‧‧‧基板 104‧‧‧Substrate

108‧‧‧堆疊 108‧‧‧Stacking

112‧‧‧GaN緩衝層 112‧‧‧GaN buffer layer

116‧‧‧氮化鋁鎵(AlGaN)層 116‧‧‧AlGaN layer

120‧‧‧AlN層 120‧‧‧AlN layer

124‧‧‧氮化銦鋁(InAlN)阻障層 124‧‧‧Indium Nitride (InAlN) barrier layer

126‧‧‧閘極絕緣體 126‧‧‧gate insulator

128‧‧‧閘極 128‧‧‧ gate

132‧‧‧源極 132‧‧‧ source

136‧‧‧汲極 136‧‧‧汲

Claims (21)

一種設備,其包括:一基板;一氮化鎵(GaN)緩衝層,其形成在該基板上;一氮化鋁鎵(AlGaN)層,其形成在該GaN緩衝層上,該AlGaN層的鋁濃度小於約15%;以及一氮化銦鋁(InAlN)阻障層,其形成在該AlGaN層上,其中,該AlGaN層比該InAlN阻障層薄。 An apparatus comprising: a substrate; a gallium nitride (GaN) buffer layer formed on the substrate; an aluminum gallium nitride (AlGaN) layer formed on the GaN buffer layer, the aluminum of the AlGaN layer a concentration of less than about 15%; and an indium aluminum nitride (InAlN) barrier layer formed on the AlGaN layer, wherein the AlGaN layer is thinner than the InAlN barrier layer. 根據申請專利範圍第1項的設備,其進一步包括:一閘極絕緣體,其形成在該InAlN阻障層上。 The apparatus of claim 1, further comprising: a gate insulator formed on the InAlN barrier layer. 根據申請專利範圍第2項的設備,其中,該設備進一步包括:一閘極,其形成在該閘極絕緣體上並且電容性耦合該InAlN阻障層。 The device of claim 2, wherein the device further comprises: a gate formed on the gate insulator and capacitively coupled to the InAlN barrier layer. 根據申請專利範圍第1項的設備,其中,該AlGaN層包含氮化銦鎵(AlxGa1-xN),其中,x代表鋁與鎵的相對數量。 The device of claim 1, wherein the AlGaN layer comprises indium gallium nitride (Al x Ga 1-x N), wherein x represents the relative amount of aluminum and gallium. 根據申請專利範圍第4項的設備,其中,該AlGaN層有固定的鋁含量並且x為約0.04。 The apparatus of claim 4, wherein the AlGaN layer has a fixed aluminum content and x is about 0.04. 根據申請專利範圍第1項的設備,其中,該AlGaN層的鋁濃度從位在該GaN緩衝層旁邊的該AlGaN層的一部分處的約0%緩變至位在該InAlN阻障層旁邊的該AlGaN層的一部分處的約15%。 The apparatus of claim 1, wherein the aluminum concentration of the AlGaN layer is gradually changed from about 0% at a portion of the AlGaN layer positioned beside the GaN buffer layer to the side of the InAlN barrier layer About 15% of a portion of the AlGaN layer. 根據申請專利範圍第1項的設備,其中,該AlGaN層的厚度為約40至60埃。 The apparatus of claim 1, wherein the AlGaN layer has a thickness of about 40 to 60 angstroms. 根據申請專利範圍第1項的設備,其中,該AlGaN層的厚度為約40 或50埃。 The device of claim 1, wherein the thickness of the AlGaN layer is about 40 Or 50 angstroms. 根據申請專利範圍第1項的設備,其進一步包括:一氮化鋁(AlN)層,其形成在該AlGaN層上,其中,該InAlN阻障層形成在AlN層上。 The apparatus of claim 1, further comprising: an aluminum nitride (AlN) layer formed on the AlGaN layer, wherein the InAlN barrier layer is formed on the AlN layer. 根據申請專利範圍第1項的設備,其中,該設備包括一高電子移動率電晶體(HEMT)。 The device of claim 1, wherein the device comprises a high electron mobility transistor (HEMT). 一種方法,其包括:形成一氮化鎵(GaN)緩衝層在一基板上;形成一氮化鋁鎵(AlGaN)層在該GaN緩衝層上,該AlGaN層的厚度介於約40至60埃之間;形成一氮化銦鋁(InAlN)阻障層在該AlGaN層上;以及形成一閘極、源極、以及汲極在該InAlN阻障層上。 A method comprising: forming a gallium nitride (GaN) buffer layer on a substrate; forming an aluminum gallium nitride (AlGaN) layer on the GaN buffer layer, the AlGaN layer having a thickness of between about 40 and 60 angstroms Forming an indium aluminum nitride (InAlN) barrier layer on the AlGaN layer; and forming a gate, a source, and a drain on the InAlN barrier layer. 根據申請專利範圍第11項的方法,其進一步包括:形成一閘極絕緣體在該InAlN阻障層上。 The method of claim 11, further comprising: forming a gate insulator on the InAlN barrier layer. 根據申請專利範圍第12項的方法,其中,形成該閘極包括:形成該閘極在該閘極絕緣體上。 The method of claim 12, wherein forming the gate comprises forming the gate on the gate insulator. 根據申請專利範圍第11項的方法,其中,該AlGaN層包含氮化銦鎵(AlxGa1-xN),其中,x為介於0與0.15之間的數值並且代表鋁與鎵的相對數量。 The method of claim 11, wherein the AlGaN layer comprises indium gallium nitride (Al x Ga 1-x N), wherein x is a value between 0 and 0.15 and represents the relative of aluminum and gallium Quantity. 根據申請專利範圍第14項的方法,其中,該AlGaN層有固定的鋁含量並且x為約0.04。 The method of claim 14, wherein the AlGaN layer has a fixed aluminum content and x is about 0.04. 根據申請專利範圍第11項的方法,其中,形成該AlGaN層包括: 形成該AlGaN層,其鋁濃度從位在該GaN緩衝層旁邊的該AlGaN層的一部分處的約0%緩變至位在該InAlN阻障層旁邊的該AlGaN層的一部分處的約15%。 The method of claim 11, wherein the forming the AlGaN layer comprises: The AlGaN layer is formed, the aluminum concentration of which is gradually changed from about 0% at a portion of the AlGaN layer positioned beside the GaN buffer layer to about 15% at a portion of the AlGaN layer beside the InAlN barrier layer. 根據申請專利範圍第11項的方法,其中,形成該AlGaN層包括:形成該AlGaN層使其厚度為約40至60埃。 The method of claim 11, wherein the forming the AlGaN layer comprises: forming the AlGaN layer to a thickness of about 40 to 60 angstroms. 一種系統,其包括:一收發器,用以傳送與接收射頻(RF)信號;以及一高電子移動率電晶體(HEMT),其被併入於該收發器裡面或是耦合該收發器,該HEMT包含:一基板;一氮化鎵(GaN)緩衝層,其形成在該基板上;一氮化鋁鎵(AlGaN)層,其形成在該GaN緩衝層上,該AlGaN層的鋁濃度小於約15%;以及一氮化銦鋁(InAlN)阻障層,其形成在該AlGaN層上。 A system comprising: a transceiver for transmitting and receiving radio frequency (RF) signals; and a high electron mobility transistor (HEMT) incorporated in or coupled to the transceiver The HEMT includes: a substrate; a gallium nitride (GaN) buffer layer formed on the substrate; and an aluminum gallium nitride (AlGaN) layer formed on the GaN buffer layer, the aluminum concentration of the AlGaN layer being less than about 15%; and an indium aluminum nitride (InAlN) barrier layer formed on the AlGaN layer. 根據申請專利範圍第18項的系統,其進一步包括:一RF功率放大器,其包含該HEMT。 A system according to claim 18, further comprising: an RF power amplifier comprising the HEMT. 根據申請專利範圍第18項的系統,其進一步包括:一低雜訊功率放大器,其包含該HEMT。 A system according to claim 18, further comprising: a low noise power amplifier comprising the HEMT. 根據申請專利範圍第18項的系統,其進一步包括:一功率調節器,其包含該HEMT。 A system according to claim 18, further comprising: a power conditioner comprising the HEMT.
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