CN115910782A - Method for manufacturing normally-off high electron mobility transistor - Google Patents
Method for manufacturing normally-off high electron mobility transistor Download PDFInfo
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- CN115910782A CN115910782A CN202211708231.9A CN202211708231A CN115910782A CN 115910782 A CN115910782 A CN 115910782A CN 202211708231 A CN202211708231 A CN 202211708231A CN 115910782 A CN115910782 A CN 115910782A
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Abstract
The invention discloses a method for manufacturing a normally-off high electron mobility transistor, which comprises the following steps: epitaxially growing a functional layer, a channel layer, a heterojunction layer, a cap layer and a passivation layer on a substrate in sequence; growing a silicon single crystal layer on the back of the substrate; a through-hole is formed through the substrate in a designated area of the substrate and electrodes and dielectric layers are deposited on the front and back surfaces of the substrate, respectively. According to the invention, the GaN/AlGaN structure is epitaxially grown on the silicon to form the high electron mobility transistor, the MOS device is formed on the back surface of the silicon substrate, and the scheme of the normally-off high electron mobility transistor is prepared in a cascading manner, so that the problems of gate current attenuation and low starting voltage can be effectively avoided.
Description
Technical Field
The invention relates to the technical field of transistors, in particular to a manufacturing method of a normally-off high-electron-mobility transistor.
Background
The silicon-based gallium nitride high electron mobility transistor can enable the two-dimensional electron gas (2 DEG) surface density in the AlGaN/GaN heterostructure to reach 10 by utilizing the strong voltage polarization effect of the nitride material of the wurtzite structure 13 cm -2 Magnitude while maintainingThe mobility is 2000cm 2 above/V · s, for these reasons, a high electron mobility transistor using an AlGaN/GaN heterostructure has excellent input and output characteristics, and its on-resistance is significantly lower than that of a silicon device and a silicon carbide device at equivalent withstand voltage, and is very suitable for a switching device of a power supply circuit. However, the switching device of the power circuit needs a normally-off device, the general high electron mobility transistor is a normally-on device, and there are various ways to implement the normally-off high electron mobility transistor, including ion implantation, etching the gate, etc., but these ways may either increase the on-resistance of the device, reduce the performance of the device, or the gate voltage ratio is low, which causes limitations for the circuit application.
Disclosure of Invention
The invention aims to provide a method for manufacturing a normally-off high electron mobility transistor aiming at the defects in the prior art, and the scheme of the normally-off high electron mobility transistor prepared by using a back silicon MOS device cascade mode can effectively avoid the problems of gate current attenuation and low turn-on voltage.
The purpose of the invention is realized by the following technical scheme:
a method for manufacturing a normally-off high electron mobility transistor comprises the following steps:
(1) Sequentially epitaxially growing a functional layer, a channel layer, a heterojunction layer, a cap layer and a passivation layer on a P-type (111) crystal orientation silicon substrate;
(2) The back of the substrate is grown with a P-type (111) crystal orientation silicon single crystal layer with the thickness of 1 nm-1000 nm;
(3) Forming a through hole penetrating through the substrate in a designated area on the substrate;
(4) Carrying out selective doping in a designated area of the epitaxial layer on the back surface of the substrate and carrying out heat treatment on the substrate at 300-500 ℃;
(5) Cleaning the back of the substrate and depositing an oxide film in another designated area on the epitaxial layer on the back of the substrate;
(6) Cleaning the back of the substrate, depositing an electrode on the oxide film in the step (5), and performing heat treatment at 200-500 ℃;
(7) Depositing a dielectric layer on the whole back surface of the substrate;
(8) Etching a designated area on the epitaxial layer on the front surface of the substrate;
(9) Depositing a metal electrode in the etching area in the step (8) and carrying out heat treatment at 400-500 ℃;
(10) Etching another appointed area on the front surface of the substrate and forming a groove;
(11) Cleaning the front surface of the substrate and depositing a dielectric layer in the groove in the step (10);
(12) Depositing a metal electrode on the dielectric layer on the front side of the substrate in the step (11) and carrying out heat treatment at 350-550 ℃;
(13) A dielectric layer deposited on the whole surface of the front surface of the substrate;
(14) Etching a designated area on the dielectric layer on the front side of the substrate in the step (13) and forming a groove;
(15) Depositing a metal electrode in the groove in the step (14) and carrying out heat treatment at the temperature of 200-400 ℃;
(16) Depositing a dielectric layer on the whole surface of the front surface of the substrate;
(17) Etching and forming a groove in a designated area on the dielectric layer on the front side of the substrate in the step (16);
(18) Depositing a metal electrode in the groove in the step (17) and carrying out heat treatment at the temperature of 200-400 ℃;
(19) Depositing a dielectric layer on the whole surface of the front surface of the substrate;
(20) Etching a designated area on the dielectric layer on the back side of the substrate in the step (7) and forming a groove;
(21) Depositing a metal electrode in the groove in the step (20) and carrying out heat treatment at the temperature of 200-400 ℃;
(22) Depositing a dielectric layer on the whole back surface of the substrate;
(23) Etching and forming a recess in a designated area on the dielectric layer on the back side of the substrate in step (22);
(24) Depositing a metal electrode in the groove in the step (23) and carrying out heat treatment at the temperature of 200-400 ℃;
(25) Depositing a dielectric layer on the whole back surface of the substrate;
(26) Etching and forming a groove in a designated area on the dielectric layer on the back side of the substrate in the step (25);
(27) Depositing a metal electrode in the groove in the step (26) and carrying out heat treatment at the temperature of 200-400 ℃;
(28) Depositing a dielectric layer on the whole back surface of the substrate;
(29) Etching and forming a groove in a designated area on the dielectric layer on the front side of the substrate in the step (19);
(30) And (5) depositing a metal electrode in the groove in the step (29) and carrying out heat treatment at the temperature of 200-400 ℃.
Further, in the step (1): the thickness of the P-type (111) crystal orientation silicon substrate is 100-1000 mu m; the functional layer is a low-temperature AlN buffer layer material or a low-temperature GaN buffer layer material, and the thickness is 1 nm-1000 nm; the channel layer is made of non-doped GaN material, and the thickness of the channel layer is 100 nm-5000 nm; the heterojunction layer is AlGaN, the distribution ratio of the Al component to the Ga component is 0.01-0.55, and the thickness is 1-1000 nm; the cap layer is an undoped GaN layer with the thickness of 1 nm-100 nm; the passivation layer is made of silicon nitride, silicon oxide or silicon oxynitride, and the thickness of the passivation layer is 1 nm-1000 nm.
Further, in the step (2): the epitaxial layer is a P-type (111) crystal orientation silicon single crystal, and the thickness is 1 nm-10000 nm; methods of regrowth include, but are not limited to, hydrogen reduction vapor phase epitaxy or direct thermal decomposition vapor phase epitaxy.
Further, in the step (3): one designated area is a continuous area or a combination of a plurality of discontinuous areas; the shape of the through-hole includes, but is not limited to, circular, square, and oval; methods of forming through-substrate vias include, but are not limited to, through-silicon-via processes; the through hole comprises an insulating dielectric material of a hole wall and a metal electrode material inside the hole wall; the insulating dielectric material of the hole wall comprises but is not limited to silicon oxide or silicon nitride, and the thickness is 10 nm-5000 nm; the metal electrode material includes but is not limited to one or more of aluminum, copper and gold.
Further, in the step (4): one designated area is a continuous area or a combination of a plurality of discontinuous areas; methods of selective doping include, but are not limited to, ion implantation processes; the depth of the doped region is 1 nm-10000 nm and is less than the thickness of the epitaxial layer in the step (2).
Further, in the step (5): the other designated area is a continuous area or a combination of a plurality of discontinuous areas; oxide film materials include, but are not limited to, silicon oxide or silicon nitride; the thickness of the oxide film is 1 nm-500 nm; methods of depositing the oxide film include, but are not limited to, high temperature thermal oxidation.
Further, in the step (6): the electrode material comprises one or more of Al, ni and polysilicon, and the thickness of the deposition layer is 10 nm-5000 nm; the deposition method of the electrode includes, but is not limited to, sputtering or evaporation.
Further, in the step (7): the dielectric layer includes but is not limited to silicon oxide and silicon nitride, and the thickness of the dielectric layer is 100nm to 50000nm.
Further, in the step (8): one designated area is a continuous area or a combination of a plurality of discontinuous areas, and the etching comprises ICP, wet etching or combination of ICP and wet etching in any order.
Further, in the step (9): the metal electrode material includes but is not limited to one or more of Al, ti, ni and Au; the thickness of the metal deposition layer is 10 nm-5000 nm; methods of depositing the metal electrode include, but are not limited to, sputtering or evaporation.
Further, in the step (10): one designated area may be a continuous area or a combination of a plurality of discontinuous areas; the etching includes ICP, wet etching or a combination of ICP and wet etching in any order.
Further, in the step (11): the dielectric layer includes but is not limited to silicon oxide or silicon nitride, and the thickness of the dielectric layer is 1nm to 500nm.
Further, in the step (12): the metal electrode material comprises one or more of Al, ti, ni and Au, and the thickness of the metal deposition layer is 10 nm-5000 nm; methods of depositing the metal electrode include, but are not limited to, sputtering and evaporation.
Further, in the step (13): the dielectric layer includes but is not limited to silicon oxide or silicon nitride, and the thickness of the dielectric layer is 100nm to 50000nm.
Further, in the step (14): one designated area is a continuous area or a combination of a plurality of discontinuous areas; the etching includes ICP, wet etching, or a combination of ICP and wet etching in any order.
Further, in the step (15): the metal electrode material comprises but is not limited to one or more of Ti, ni, al, cu and Au, and the thickness of the metal deposition layer is 10 nm-5000 nm; methods of depositing the metal electrode include, but are not limited to, sputtering and evaporation.
Further, in the step (16): the dielectric layer includes but is not limited to silicon oxide or silicon nitride, and the thickness of the dielectric layer is 100nm to 50000nm.
Further, in the step (17): one designated area may be a continuous area or a combination of a plurality of discontinuous areas; the etching includes ICP, wet etching or a combination of ICP and wet etching in any order.
Further, in the step (18): the metal electrode material comprises but is not limited to one or more of Ti, ni, al, cu and Au, and the thickness of the metal deposition layer is 10 nm-5000 nm; methods of depositing the metal electrode include, but are not limited to, sputtering or evaporation.
Further, in the step (19): the dielectric layer includes but is not limited to silicon oxide or silicon nitride, and the thickness of the dielectric layer is 100nm to 50000nm.
Further, in the step (20): one designated area is a continuous area or a combination of a plurality of discontinuous areas; the etching includes ICP, wet etching or a combination of ICP and wet etching in any order.
Further, in the step (21): the metal electrode material comprises but is not limited to one or more of Ti, ni, al, cu and Au, and the thickness of the metal deposition layer is 10 nm-5000 nm; methods of depositing the metal electrode include, but are not limited to, sputtering or evaporation.
Further, in the step (22): the dielectric layer includes but is not limited to silicon oxide or silicon nitride, and the thickness of the dielectric layer is 100nm to 50000nm.
Further, in the step (23): one designated area may be a continuous area or a combination of a plurality of discontinuous areas; the etching includes ICP, wet etching, or a combination of ICP and wet etching in any order.
Further, in the step (24): the metal electrode material comprises but is not limited to one or more of Ti, ni, al, cu and Au, and the thickness of the metal deposition layer is between 10nm and 5000nm; methods of depositing the metal electrode include, but are not limited to, sputtering or evaporation.
Further, in the step (25): the dielectric layer includes but is not limited to silicon oxide or silicon nitride, and the thickness of the dielectric layer is between 100nm and 50000nm.
Further, the step (26): one designated area may be a continuous area or a combination of a plurality of discontinuous areas; the etching includes ICP, wet etching or a combination of ICP and wet etching in any order.
Further, in the step (27): the metal electrode material comprises but is not limited to one or more of Ti, ni, al, cu and Au, and the thickness of the metal deposition layer is 10 nm-5000 nm; methods of depositing the metal electrode include, but are not limited to, sputtering or evaporation.
Further, in the step (28): the dielectric layer includes but is not limited to silicon oxide or silicon nitride, and the thickness of the dielectric layer is 100nm to 50000nm.
Further, in the step (29): one designated area may be a continuous area or a combination of a plurality of discontinuous areas; the etching includes ICP, wet etching or a combination of ICP and wet etching in any order.
Further, in the step (30): the metal electrode material comprises but is not limited to one or more of Ti, ni, al, cu and Au, and the thickness of the metal deposition layer is 10 nm-5000 nm; methods of depositing the metal electrode include, but are not limited to, sputtering or evaporation.
The invention has the beneficial effects that:
the traditional normally-off high electron mobility transistor is realized by using ion implantation, gate etching or p-type gate and the like, but the problems of gate current attenuation or low turn-on voltage and the like exist. The scheme of the normally-off high electron mobility transistor prepared by using the back silicon MOS device cascade mode can effectively avoid the problems of gate current attenuation and low starting voltage.
Drawings
FIG. 1 is a schematic process flow diagram of step 1 of the present invention;
FIG. 2 is a schematic process flow diagram of step 2 of the present invention;
FIG. 3 is a schematic process flow diagram of step 3 of the present invention;
FIG. 4 is a schematic process flow diagram of step 4 of the present invention;
FIG. 5 is a schematic process flow diagram of step 5 of the present invention;
FIG. 6 is a schematic process flow diagram of step 6 of the present invention;
FIG. 7 is a schematic process flow diagram of step 7 of the present invention;
FIG. 8 is a schematic process flow diagram of step 8 of the present invention;
FIG. 9 is a schematic process flow diagram of step 9 of the present invention;
FIG. 10 is a schematic process flow diagram illustrating step 10 of the present invention;
FIG. 11 is a schematic process flow diagram of step 11 of the present invention;
FIG. 12 is a schematic process flow diagram of step 12 of the present invention;
FIG. 13 is a schematic process flow diagram illustrating step 13 of the present invention;
FIG. 14 is a schematic process flow diagram of step 14 of the present invention;
FIG. 15 is a schematic process flow diagram of step 15 of the present invention;
FIG. 16 is a schematic process flow diagram of step 16 of the present invention;
FIG. 17 is a schematic process flow diagram of step 17 of the present invention;
FIG. 18 is a schematic process flow diagram of step 18 of the present invention;
FIG. 19 is a schematic process flow diagram illustrating step 19 of the present invention;
FIG. 20 is a schematic process flow diagram illustrating step 20 of the present invention;
FIG. 21 is a schematic process flow diagram of step 21 of the present invention;
FIG. 22 is a schematic process flow diagram of step 22 of the present invention;
FIG. 23 is a schematic process flow diagram of step 23 of the present invention;
FIG. 24 is a schematic view of the process flow of step 24 of the present invention;
FIG. 25 is a schematic process flow diagram of step 25 of the present invention;
FIG. 26 is a schematic process flow diagram illustrating step 26 of the present invention;
FIG. 27 is a schematic process flow diagram of step 27 of the present invention;
FIG. 28 is a schematic process flow diagram of step 28 of the present invention;
FIG. 29 is a schematic process flow diagram illustrating step 29 of the present invention;
FIG. 30 is a schematic process flow diagram illustrating step 30 of the present invention;
reference numerals are as follows:
101-silicon substrate, 102-low-temperature AlN functional layer, 103-non-doped GaN channel layer, 104-AlGaN heterojunction layer, 105-GaN cap layer, 106-in-situ silicon nitride passivation layer, 107-metal electrode, 108-silicon nitride dielectric layer, 109-metal electrode, 110, 111 and 112-silicon nitride dielectric layer; 201-silicon epitaxial layer (P type (111) crystal orientation silicon single crystal layer), 202-N type doping region, 203-silicon dioxide film, 204-gate electrode, 205, 206, 207, 208-silicon nitride dielectric layer; 301-silicon dioxide (via walls), 302- (inside the via) Al metal, 303, 304, 305, 306, 307-Al electrode, 308-device drain electrode, 309-device gate electrode, 310-device source electrode.
Detailed Description
For a further understanding of the invention, preferred embodiments of the invention are described below in conjunction with specific examples, but it should be understood that these descriptions are included only to further illustrate the features and advantages of the invention, and not to limit the claims of the invention.
This embodiment is an implementation of a normally-off high electron mobility transistor.
In this embodiment, the substrate material is selected to be P-type (111) crystal orientation single crystal silicon with a thickness of 650 μm. The preparation process of the normally-off high electron mobility transistor comprises the following steps:
(1) Epitaxial growth is sequentially carried out on a P-type (111) crystal orientation silicon substrate 101, and a low-temperature AlN functional layer 102 with the thickness of 20nm, a non-doped GaN channel layer 103 with the thickness of 500nm, an AlGaN heterojunction layer 104 with the thickness of 20nm and the Al component of 0.3, a non-doped GaN cap layer 105 with the thickness of 3nm and an in-situ silicon nitride passivation layer 106 with the thickness of 300nm are sequentially carried out;
(2) A P-type (111) crystal orientation silicon single crystal layer 201 (silicon epitaxial layer) with the thickness of 1000nm is regrown on the back surface of the substrate through hydrogen reduction method vapor phase epitaxy;
(3) Forming three circular through holes on the substrate by using a Through Silicon Via (TSV) process, wherein the hole wall insulating dielectric medium is silicon dioxide 301 with the thickness of 1000nm, and the metal electrode material in the hole wall is Al metal 302;
(4) Forming an N-type doped region 202 with the depth of 500nm in two regions on the back surface of the substrate by implanting B ions, and performing high-temperature heat treatment at 450 ℃;
(5) Cleaning the back of the substrate, and depositing a silicon dioxide film 203 with the thickness of 35nm between the N-type doped regions 202 in the step (4) by using a high-temperature thermal oxidation method;
(6) Cleaning the back of the substrate, depositing polycrystalline silicon 204 (a gate electrode) with the depth of 500nm on the silicon dioxide film in the step (5), and carrying out high-temperature heat treatment at 300 ℃;
(7) Depositing a silicon nitride dielectric layer 205 with the thickness of 1000nm on the whole back surface of the substrate;
(8) Etching two areas on the epitaxial layer on the front surface of the substrate by using an ICP (inductively coupled plasma) and a wet method in sequence;
(9) Depositing Ti/Al/Ni/Au electrodes 107 with the thickness ratio of 20nm/120nm/10nm/500nm in the two etching areas in the step (8), and performing high-temperature heat treatment at 450 ℃;
(10) Sequentially etching by using ICP (inductively coupled plasma) and a wet method between the two regions in the step (8) and forming a groove;
(11) Depositing a silicon nitride dielectric layer 108 with the thickness of 30nm in the groove in the step (10);
(12) Depositing a Ti/Au metal electrode 109 with the thickness ratio of 100nm/500nm on the silicon nitride dielectric layer on the front surface of the substrate in the step (11) by using a sputtering method, and performing high-temperature heat treatment at 500 ℃;
(13) And depositing a silicon nitride dielectric layer 110 with the thickness of 1000nm on the whole front surface of the substrate.
(14) Etching and forming a groove on the dielectric layer on the front surface of the substrate in the step (13) by using an ICP (inductively coupled plasma) method to expose one of the metal electrodes formed in the step (9) and one of the through holes formed in the step (3) and closest to the metal electrode;
(15) Depositing an Al electrode 303 with the thickness of 1000nm in the groove in the step (14) by using an evaporation method and carrying out high-temperature heat treatment at 300 ℃;
(16) Depositing a silicon nitride dielectric layer 111 with the thickness of 1000nm on the whole front surface of the substrate;
(17) Etching and forming a groove on the dielectric layer on the front surface of the substrate in the step (16) by using an ICP (inductively coupled plasma) method to expose the metal electrode formed in the step (12) and the through hole which is formed in the step (3) and is farthest from the electrode;
(18) Depositing an Al electrode 304 with the thickness of 1000nm in the groove in the step (17) by using an evaporation method and carrying out high-temperature heat treatment at 300 ℃;
(19) Depositing a silicon nitride dielectric layer 112 with the thickness of 1000nm on the whole front surface of the substrate;
(20) Etching and forming a groove on the dielectric layer on the back surface of the substrate in the step (7) by using an ICP method to expose the injection region formed in the step (4) and the through hole which is formed in the step (3) and is closest to the electrode;
(21) Depositing a 1000nm thick Al electrode 305 in the groove in the step (20) by using an evaporation method and carrying out high-temperature heat treatment at 300 ℃;
(22) Depositing a silicon nitride dielectric layer 206 with the thickness of 1000nm on the whole back surface of the substrate;
(23) Etching and forming a groove on the dielectric layer on the back surface of the substrate in the step (22) by using an ICP (inductively coupled plasma) method to expose the metal electrode formed in the step (6) and the through hole in the middle position formed in the step (3);
(24) Depositing an Al electrode 306 with the thickness of 1000nm in the groove in the step (23) by using an evaporation method and carrying out high-temperature heat treatment at 300 ℃;
(25) Depositing a silicon nitride dielectric layer 207 with the thickness of 1000nm on the whole back surface of the substrate;
(26) Etching and forming a groove on the dielectric layer on the back surface of the substrate in the step (25) by using an ICP method to expose the other injection region formed in the step (4) and the through hole which is formed in the step (3) and is farthest away from the electrode;
(27) Depositing an Al electrode 307 with the thickness of 1000nm in the groove in the step (25) by using an evaporation method and carrying out high-temperature heat treatment at 300 ℃;
(28) Depositing a silicon nitride dielectric layer 208 with the thickness of 5000nm on the whole back surface of the substrate;
(29) Etching a groove on the dielectric layer on the front surface of the substrate in the step (19) by using an ICP method to expose the other metal electrode formed in the step (9), the through hole which is formed in the step (3) and is farthest away from the electrode and the through hole in the middle position formed in the step (3), wherein the etching area of the through hole in the middle position and the rest of etching grooves are not in the same cross section;
(30) And (5) depositing an Al electrode with the thickness of 1000nm in the groove in the step (29) by using an evaporation method and carrying out high-temperature heat treatment at 300 ℃ to form a device drain electrode 308, a device gate electrode 309 and a device source electrode 310.
The scheme of the normally-off high electron mobility transistor prepared by using the cascade mode of the back silicon MOS device can effectively avoid the problems of gate current attenuation and low starting voltage.
Those skilled in the art to which the present invention pertains can also make appropriate alterations and modifications to the above-described embodiments, in light of the above disclosure. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and variations of the present invention should fall within the scope of the claims of the present invention. Furthermore, although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (10)
1. A method for manufacturing a normally-off high electron mobility transistor is characterized in that: the method comprises the following steps:
(1) A functional layer, a channel layer, a heterojunction layer, a cap layer and a passivation layer are epitaxially grown on a P-type (111) crystal orientation silicon substrate in sequence;
(2) The back of the substrate is grown with a P-type (111) crystal orientation silicon single crystal layer with the thickness of 1 nm-1000 nm;
(3) Forming a through hole penetrating through the substrate in a designated area on the substrate;
(4) Carrying out selective doping in a designated area of the epitaxial layer on the back surface of the substrate and carrying out heat treatment on the substrate at 300-500 ℃;
(5) Cleaning the back of the substrate and depositing an oxide film in another designated area on the epitaxial layer on the back of the substrate;
(6) Cleaning the back of the substrate, depositing an electrode on the oxide film in the step (5) and carrying out heat treatment at 200-500 ℃;
(7) Depositing a dielectric layer on the whole back surface of the substrate;
(8) Etching a designated area on the epitaxial layer on the front surface of the substrate;
(9) Depositing a metal electrode in the etching area in the step (8) and carrying out heat treatment at 400-500 ℃;
(10) Etching the other appointed area on the front surface of the substrate and forming a groove;
(11) Cleaning the front surface of the substrate and depositing a dielectric layer in the groove in the step (10);
(12) Depositing a metal electrode on the dielectric layer on the front side of the substrate in the step (11) and carrying out heat treatment at 350-550 ℃;
(13) A dielectric layer deposited on the whole surface of the front surface of the substrate;
(14) Etching and forming a groove in a designated area on the dielectric layer on the front surface of the substrate in the step (13);
(15) Depositing a metal electrode in the groove in the step (14) and carrying out heat treatment at the temperature of 200-400 ℃;
(16) Depositing a dielectric layer on the whole surface of the front surface of the substrate;
(17) Etching and forming a groove in a designated area on the dielectric layer on the front side of the substrate in the step (16);
(18) Depositing a metal electrode in the groove in the step (17) and carrying out heat treatment at the temperature of 200-400 ℃;
(19) Depositing a dielectric layer on the whole surface of the front surface of the substrate;
(20) Etching a designated area on the dielectric layer on the back side of the substrate in the step (7) and forming a groove;
(21) Depositing a metal electrode in the groove in the step (20) and carrying out heat treatment at the temperature of 200-400 ℃;
(22) Depositing a dielectric layer on the whole back surface of the substrate;
(23) Etching and forming a recess in a designated area on the dielectric layer on the back side of the substrate in step (22);
(24) Depositing a metal electrode in the groove in the step (23) and carrying out heat treatment at the temperature of 200-400 ℃;
(25) Depositing a dielectric layer on the whole back surface of the substrate;
(26) Etching and forming a groove in a designated area on the dielectric layer on the back side of the substrate in the step (25);
(27) Depositing a metal electrode in the groove in the step (26) and carrying out heat treatment at the temperature of 200-400 ℃;
(28) Depositing a dielectric layer on the whole back surface of the substrate;
(29) Etching and forming a groove in a designated area on the dielectric layer on the front side of the substrate in the step (19);
(30) And (29) depositing a metal electrode in the groove and carrying out heat treatment at 200-400 ℃.
2. The method of manufacturing a normally-off high electron mobility transistor according to claim 1, wherein: in the step (1): the thickness of the P-type (111) crystal orientation silicon substrate is 100-1000 μm; the functional layer is a low-temperature AlN buffer layer material or a low-temperature GaN buffer layer material, and the thickness is 1 nm-1000 nm; the channel layer is made of non-doped GaN material, and the thickness of the channel layer is 100 nm-5000 nm; the heterojunction layer is AlGaN, the distribution ratio of the Al component to the Ga component is 0.01-0.55, and the thickness is 1-1000 nm; the cap layer is an undoped GaN layer with the thickness of 1 nm-100 nm; the passivation layer is made of silicon nitride, silicon oxide or silicon oxynitride, and the thickness of the passivation layer is 1 nm-1000 nm.
3. The method of manufacturing a normally-off high electron mobility transistor according to claim 1, wherein: in the step (2): the epitaxial layer is a P-type (111) crystal orientation silicon single crystal, and the thickness is 1 nm-10000 nm; the regrowth method is hydrogen reduction method vapor phase epitaxy or direct thermal decomposition method vapor phase epitaxy.
4. The method of manufacturing a normally-off high electron mobility transistor according to claim 1, wherein: in the step (3): the through holes are round, square or oval; the method for forming the through hole penetrating through the substrate is a through silicon via process; the through hole comprises an insulating dielectric material of a hole wall and a metal electrode material inside the hole wall; the insulating dielectric material of the hole wall is silicon oxide or silicon nitride, and the thickness is 10 nm-5000 nm; the metal electrode material is one or more of aluminum, copper and gold.
5. The method of manufacturing a normally-off high electron mobility transistor according to claim 1, wherein: in the step (4): the method for selective doping is an ion implantation process; the depth of the doped region is 1 nm-10000 nm, and the depth of the doped region is less than the thickness of the epitaxial layer in the step (2).
6. The method of manufacturing a normally-off high electron mobility transistor according to claim 1, wherein: in the step (5): the material of the oxide film is silicon oxide or silicon nitride; the thickness of the oxide film is 1 nm-500 nm; the deposition method of the oxide film is high-temperature thermal oxidation.
7. The method of manufacturing a normally-off high electron mobility transistor according to claim 1, wherein: in the step (6): the electrode material is one or more of Al, ni and polysilicon, and the thickness of the deposition layer is 10 nm-5000 nm;
in the step (9): the metal electrode material is one or more of Al, ti, ni and Au; the thickness of the metal deposition layer is 10 nm-5000 nm;
in the step (12): the metal electrode material is one or more of Al, ti, ni and Au; the thickness of the metal deposition layer is 10 nm-5000 nm;
in the step (15): the metal electrode material is one or more of Al, ti, ni and Au; the thickness of the metal deposition layer is 10 nm-5000 nm;
in the step (18): the metal electrode material is one or more of Ti, ni, al, cu and Au; the thickness of the metal deposition layer is 10 nm-5000 nm;
in the step (21): the metal electrode material is one or more of Ti, ni, al, cu and Au; the thickness of the metal deposition layer is 10 nm-5000 nm;
in the step (24): the metal electrode material is one or more of Ti, ni, al, cu and Au; the thickness of the metal deposition layer is 10 nm-5000 nm;
in the step (27): the metal electrode material is one or more of Ti, ni, al, cu and Au; the thickness of the metal deposition layer is 10 nm-5000 nm;
in the step (30): the metal electrode material is one or more of Ti, ni, al, cu and Au; the thickness of the metal deposition layer is 10 nm-5000 nm;
the deposition method of the electrode is sputtering or evaporation.
8. The method of manufacturing a normally-off high electron mobility transistor according to claim 1, wherein: the dielectric layer is made of silicon oxide or silicon nitride.
9. The method of manufacturing a normally-off high electron mobility transistor according to claim 8, wherein:
the thickness of the dielectric layer in the step (7) is 100 nm-50000 nm;
the thickness of the dielectric layer in the step (11) is 1 nm-500 nm;
the thickness of the dielectric layer in the step (13) is 100 nm-50000 nm;
the thickness of the dielectric layer in the step (16) is 100 nm-50000 nm;
the thickness of the dielectric layer in the step (19) is 100 nm-50000 nm;
the thickness of the dielectric layer in the step (22) is 100 nm-50000 nm;
the thickness of the dielectric layer in the step (25) is 100 nm-50000 nm;
the thickness of the dielectric layer in the step (28) is 100 nm-50000 nm.
10. The method of manufacturing a normally-off high electron mobility transistor according to claim 1, wherein: the one designated area is a continuous area or a combination of a plurality of discontinuous areas; the other designated area is a continuous area or a combination of a plurality of discontinuous areas; the etching includes ICP, wet etching, or a combination of ICP and wet etching in any order.
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