CN108054143A - A kind of GaN-HEMT and the single chip integrated methods of Si-CMOS - Google Patents
A kind of GaN-HEMT and the single chip integrated methods of Si-CMOS Download PDFInfo
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- CN108054143A CN108054143A CN201711412047.9A CN201711412047A CN108054143A CN 108054143 A CN108054143 A CN 108054143A CN 201711412047 A CN201711412047 A CN 201711412047A CN 108054143 A CN108054143 A CN 108054143A
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- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000010354 integration Effects 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 230000002238 attenuated effect Effects 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 claims description 13
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000008367 deionised water Substances 0.000 claims description 8
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000005260 corrosion Methods 0.000 claims description 5
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- 238000005530 etching Methods 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 229910017083 AlN Inorganic materials 0.000 claims description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 2
- 229910052906 cristobalite Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910052682 stishovite Inorganic materials 0.000 claims description 2
- 229910052905 tridymite Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 238000011049 filling Methods 0.000 abstract description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 abstract 1
- 102000013275 Somatomedins Human genes 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 13
- 238000001534 heteroepitaxy Methods 0.000 description 2
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- 229910000679 solder Inorganic materials 0.000 description 2
- -1 Fig. 1 Chemical compound 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a kind of GaN HEMT and the single chip integrated methods of Si CMOS, and its step are as follows：Si CMOS disks and temporary carrier surface are cleaned, and carries out ephemeral key conjunction；Si CMOS substrates are subjected to attenuated polishing；Mutual linked hole is etched in Si CMOS backs；Somatomedin layer and interconnection window is etched in through hole；Filling metal is electroplated with the Si CMOS substrates back side in through-holes；Prepare patterned metal salient point；Patterned metal salient point is prepared on GaN HEMT disks；GaN HEMT and Si CMOS disks are aligned and are bonded；Temporary carrier and temporary adhesion material are removed, obtains GaN HEMT and Si CMOS single-chip integration disks.The present invention realizes the high density single-chip integration of GaN HEMT and Si CMOS, and the interconnection density order of magnitude is promoted, while solves the heat dissipation problem of high power device High Density Integration.
Description
Technical field
The invention belongs to semiconductor process technique fields, and in particular to a kind of GaN-HEMT and Si-CMOS is single chip integrated
Method.
Background technology
Wide bandgap semiconductor GaN HEMT devices (HEMTs) have high frequency, high-breakdown-voltage, Gao Gong
The excellent properties such as rate density, broadband, but there are the shortcomings of integrated level is low, power consumption is big.And Si-CMOS is in the integrated level and work(of circuit
In consumption there is significant advantage, GaN-HEMT and Si-CMOS is integrated by specific technological means on same substrate,
While reducing circuit additional parasitic, reduce the chip gross area, it is excellent to give full play to the respective performance of GaN-HE MT and Si-CMOS
Gesture improves the comprehensive performance of circuit to greatest extent.
Usually realize that the single chip integrated methods of GaN-HEMT and Si-CMOS have " flip chip bonding " and " hetero-epitaxy " etc.." upside-down mounting
Weldering " tips upside down on GaN-HEMT on Si-CMOS substrates by solder joint, is limited to equipment precision and salient point size, between solder joint
Spacing generally in more than 500um, directly limits integrated density and flexibility.And " hetero-epitaxy " due to need in Si substrates
Upper growth Ga N epitaxial layers, there are larger lattice mismatches and thermal mismatching between two kinds of materials of Si and GaN so that epitaxial growth
GaN is second-rate.There is also uncontrollable stress in epitaxial layer, to the preparation of subsequent device, there are numerous uncertain factors, shadows
Ring final device performance.
The content of the invention
It is an object of the invention to provide a kind of GaN-HEMT and the single chip integrated methods of Si-CMOS.
Realize the object of the invention technical solution be：A kind of GaN-HEMT and the single chip integrated methods of Si-CMOS, bag
Include following steps：
1) Si-CMOS disks and temporary carrier surface are cleaned, and is dried；
2) in Si-CMOS disks front and temporary carrier surface spin coating temporary adhesion material；
3) it is Si-CMOS disks and temporary carrier front is opposite, and heat pressurization and be bonded；
4) by the Si-CMOS wafer substrate attenuated polishings using temporary carrier as support；
5) via hole image is interconnected in the photoetching of the Si-CMOS wafer substrates back side, mutual unicom is then etched according to litho pattern
M1 layers of metals of Si-CMOS are exposed in hole；
6) one layer of dielectric insulation layer is grown in mutual linked hole；
7) litho pattern, and pass through litho pattern and perform etching or corrode again in mutual linked hole exposes interconnection window；
8) in mutual linked hole adhesion layer, diffusion impervious layer and Seed Layer are grown with Si-CMOS substrate backs；
9) in Si-CMOS substrate back litho patterns, and filled mutually with the plating of Si-CMOS substrate backs in mutual linked hole
Join metal；
10) corrosion is removed photoresist and is anti-carved at the Si-CMOS back sides, by adhesion layer at photoresist covering, diffusion impervious layer and
Seed Layer removes；
11) patterned metal salient point is prepared in plating metal；
12) GaN-HEMT disks are cleaned with diluted hydrochloric acid, then is dried with deionized water；
13) patterned metal salient point is prepared in GaN-HEMT disk surfaces；
14) GaN-HEMT and Si-CMOS are face-up aligned by respective alignment mark, and heat pressurize into
Line unit closes；
15) temporary carrier and temporary adhesion material are removed, obtains GaN-HEMT and Si-CMOS single-chip integration disks.
Further, temporary carrier is glass, sapphire, carborundum or aluminium nitride in step 1).
Further, step 1) is specially：Si-CMOS disks and temporary carrier surface are cleaned with diluted hydrochloric acid, then is used
Deionized water is rinsed, and is then placed in dryer and is dried.
Further, interim bonding temperature is at 110-200 DEG C in step 3), and bonding time was at 5-20 minutes.
Further, mutual linked hole is prepared in step 5) at the Si-CMOS back sides, preparation method is dry or wet.
Further, the dielectric insulation layer medium in step 6) is SiO2、Al2O3Or Si3N4, thickness 10-200nm.
Further, in step 9), mutual linked hole is filled using plating metal, plating metal is Cu or Au.
Further, the interconnection bump metal at the Si back sides is Au, Cu, Sn, In, Ti or Ni in step 11), and thickness is in 1-
20um, diameter is in 1-50um.
Further, the positive interconnection bump metals of GaN are Au, Cu, Sn, In, Ti or Ni in step 13), and thickness is in 1-
20um, diameter is in 1-50um.
Further, bonding temperature is at 150 DEG C -400 DEG C in step 14), and bonding pressure is in 400mbar-6000mbar, key
The time is closed at 10-200 minutes.
Compared with prior art, remarkable advantage of the invention is：(1) present invention is bonded by highdensity micro convex point and realized
The single-chip integration of GaN HMET and Si-CMOS and existing " flip chip bonding " are compared, and interconnection pitch are reduced to some tens of pm, mutually
Join orders of density to be promoted, greatly reduce the gross area of chip；(2) present invention puts the GaN-HEMT power devices of high heat
In stacked structure bottom, quickly heat is distributed in heat sink using the SiC substrate of high heat conductance, is solved under High Density Integration
Heat dissipation problem；(3) present invention realizes the high density single-chip integration of GaN-HEMT and Si-CMOS, and interconnection pitch is reduced to tens of micro-
Rice, the interconnection density order of magnitude are promoted.
Description of the drawings
Fig. 1 is temporary carrier sample schematic diagram.
Fig. 2 is Si-CMOS wafer sample schematic diagrames.
Fig. 3 is interim bonding schematic diagram.
Fig. 4 is Si-CMOS substrate thinning schematic diagrames.
Fig. 5 is the mutual linked hole schematic diagram of Si-CMOS back-etchings.
Fig. 6 is growth dielectric schematic diagram in mutual linked hole.
Fig. 7 is etching interconnection window schematic diagram.
Fig. 8 is plating filling interconnection metal schematic diagram.
Fig. 9 is that bonding salient point schematic diagram is prepared at the Si-CMOS back sides.
Figure 10 is GaN-HEMT sample schematic diagrames.
Figure 11 is to prepare bonding salient point schematic diagram in GaN-HEMT samples front.
Figure 12 is in alignment with bonding schematic diagram.
Figure 13 is GaN-HEMT and Si-CMOS single-chip integration sample schematic diagrames.
Specific embodiment
A kind of GaN-HEMT of the present invention and the single chip integrated methods of Si-CMOS, comprise the following steps：
1) Si-CMOS disks and temporary carrier surface are cleaned with diluted hydrochloric acid, then is rinsed with deionized water, then
Dryer is put into be dried；Temporary carrier be glass, sapphire, carborundum or aluminium nitride, such as Fig. 1, shown in 2.
2) in Si-CMOS disks front and temporary carrier surface spin coating temporary adhesion material；Temporary adhesion material is photoetching
Glue or high temperature wax；
3) it is Si-CMOS disks and temporary carrier front is opposite, it is bonded temporarily at 110-200 DEG C, bonding time 5-
20 minutes, as shown in Figure 3；
4) the Si-CMOS disk backing substrate attenuated polishings for supporting temporary carrier, as shown in Figure 4；
5) via hole image is interconnected in the photoetching of the Si-CMOS wafer substrates back side, wet etching is then passed through according to litho pattern
Or dry etching, mutual linked hole is prepared, exposes M1 layers of metals of Si-CMOS, as shown in Figure 5；
6) one layer of dielectric insulation layer, medium SiO are grown in mutual linked hole2、Al2O3Or Si3N4, thickness 10-200nm,
As shown in Figure 6；
7) litho pattern, and pass through litho pattern and perform etching or corrode again in mutual linked hole exposes Si-CMOS
M1 layers of metal, as shown in Figure 7；
8) adhesion layer, diffusion impervious layer and Seed Layer are prepared with Si-CMOS substrate backs in mutual linked hole；
9) in Si-CMOS substrate back litho patterns, and filled mutually with the plating of Si-CMOS substrate backs in mutual linked hole
Join metal, interconnection metal is Cu or Au；
10) corrosion is removed photoresist and is anti-carved at the Si-CMOS back sides, by adhesion layer at photoresist covering, diffusion impervious layer and
Seed Layer removes, as shown in Figure 8；
11) patterned metal salient point is prepared on plating patterns, metal species include Au, Cu, Sn, In, Ti, Ni, thickness
In 1-20um, diameter is in 1-50um, as shown in Figure 9；
12) GaN-HEMT disks are cleaned with diluted hydrochloric acid, then is dried with deionized water, GaN wafer substrates can be with
For silicon or carborundum, as shown in Figure 10；
13) prepare patterned metal salient point in GaN-HEMT disk surfaces, metal species include Au, Cu, Sn, In, Ti,
Ni, thickness is in 1-20um, and diameter is in 1-50um, as shown in figure 11；
14) GaN-HEMT and Si-CMOS are face-up aligned by respective alignment mark, and heat pressurize into
Line unit closes, bonding temperature at 150 DEG C -300 DEG C, bonding pressure in 400mbar-4000mbar, bonding time at 10-200 minutes,
As shown in figure 12；
15) temporary carrier and temporary adhesion material are removed, obtains GaN-HEMT and Si-CMOS single-chip integration disks, is such as schemed
Shown in 13.
Embodiment
1) Si-CMOS disks and temporary carrier surface of SiC 30s are cleaned with 10% hydrochloric acid, then with deionized water rinsing 5 times；
Dryer is then placed in be dried；
2) spin coating temporary adhesion material at high temperature wax is distinguished in Si-CMOS disks front and temporary carrier surface, after coating
Disk be individually placed to toast on 100 DEG C of hot plates 3 minutes, it is then that Si-CMOS disks and SiC slide glasses front is opposite, at 150 DEG C
The lower interim bonding of progress 10 minutes；
3) the Si-CMOS disks backing substrate that temporary carrier supports with wafer lapping machine is thinned, is ground to residual thickness
Then 100um is polished technique using chemical-mechanical polisher, residual thickness 50um after polishing；
4) the Si-CMOS disks back side after being thinned makes interconnection via hole image by lithography, then using photoresist as mask, according to
Litho pattern passes through Cl2Plasma dry etch etches mutual linked hole, exposes M1 layers of metals of Si-CMOS；
5) Al of 50nm thickness is grown in through-holes2O3Dielectric layer；
6) litho pattern again in through-holes, then using photoresist as mask, goes out according to litho pattern HF acid corrosions
Interconnect window；
7) 40nmWTi is grown in mutual linked hole as adhesion layer, 50nmPt as diffusion impervious layer and 50nmTi conducts
Seed Layer；
8) in Si-CMOS substrate back litho patterns, and filled mutually with the plating of Si-CMOS substrate backs in mutual linked hole
Join Ni metal, corrosion is removed photoresist and anti-carved at the Si-CMOS back sides, by adhesion layer, diffusion impervious layer at preamble photoresist covering
It is removed with Seed Layer；
9) the graphical Au salient points of 5um thickness, salient point diameter 10um are prepared using lift off techniques in plating metal；
10) GaN-HEMT disk surfaces 30s are cleaned with 10% hydrochloric acid, then with deionized water rinsing 5 times；It is then placed in drying
Machine is dried；
11) the graphical Sn salient points of 1um thickness, diameter 8um are prepared using electro-plating method in GaN-HEMT disk surfaces；
12) GaN-HEMT and Si-CMOS face-up by respective alignment mark are aligned, added at 200 DEG C
Pressure 1000mbar is bonded, bonding time 20 minutes；
13) SiC slide glasses are removed by solving bonder, then high temperature wax is removed using high temperature wax remover, is obtained
GaN-HEMT and Si-CMOS single-chip integration disks.
Claims (10)
1. a kind of GaN-HEMT and the single chip integrated methods of Si-CMOS, which is characterized in that comprise the following steps：
1) Si-CMOS disks and temporary carrier surface are cleaned, and is dried；
2) in Si-CMOS disks front and temporary carrier surface spin coating temporary adhesion material；
3) it is Si-CMOS disks and temporary carrier front is opposite, and heat pressurization and be bonded；
4) by the Si-CMOS wafer substrate attenuated polishings using temporary carrier as support；
5) via hole image is interconnected in the photoetching of the Si-CMOS wafer substrates back side, mutual linked hole is then etched according to litho pattern, revealed
Go out M1 layers of metals of Si-CMOS；
6) one layer of dielectric insulation layer is grown in mutual linked hole；
7) litho pattern, and pass through litho pattern and perform etching or corrode again in mutual linked hole exposes interconnection window；
8) in mutual linked hole adhesion layer, diffusion impervious layer and Seed Layer are grown with Si-CMOS substrate backs；
9) in Si-CMOS substrate back litho patterns, and fill with the plating of Si-CMOS substrate backs in mutual linked hole and interconnect gold
Belong to；
10) corrosion is removed photoresist and is anti-carved at the Si-CMOS back sides, by adhesion layer, diffusion impervious layer and seed at photoresist covering
Layer removal；
11) patterned metal salient point is prepared in plating metal；
12) GaN-HEMT disks are cleaned with diluted hydrochloric acid, then is dried with deionized water；
13) patterned metal salient point is prepared in GaN-HEMT disk surfaces；
14) GaN-HEMT and Si-CMOS face-up by respective alignment mark are aligned, and heat and pressurize into line unit
It closes；
15) temporary carrier and temporary adhesion material are removed, obtains GaN-HEMT and Si-CMOS single-chip integration disks.
2. a kind of GaN-HEMT according to claim 1 and the single chip integrated methods of Si-CMOS, which is characterized in that step
1) temporary carrier is glass, sapphire, carborundum or aluminium nitride in.
3. a kind of GaN-HEMT according to claim 1 and the single chip integrated methods of Si-CMOS, which is characterized in that step
1) it is specially：Si-CMOS disks and temporary carrier surface are cleaned with diluted hydrochloric acid, then is rinsed with deionized water, then
Dryer is put into be dried.
4. a kind of GaN-HEMT according to claim 1 and the single chip integrated methods of Si-CMOS, which is characterized in that step
3) interim bonding temperature is at 110-200 DEG C in, and bonding time was at 5-20 minutes.
5. a kind of GaN-HEMT according to claim 1 and the single chip integrated methods of Si-CMOS, which is characterized in that step
5) in, mutual linked hole is prepared at the Si-CMOS wafer substrates back side, preparation method is dry or wet.
6. a kind of GaN-HEMT according to claim 1 and the single chip integrated methods of Si-CMOS, which is characterized in that step
6) the dielectric insulation layer medium in is SiO2、Al2O3Or Si3N4, thickness 10-200nm.
7. a kind of GaN-HEMT according to claim 1 and the single chip integrated methods of Si-CMOS, which is characterized in that step
9) in, mutual linked hole is filled using plating metal, plating metal is Cu or Au.
8. a kind of GaN-HEMT according to claim 1 and the single chip integrated methods of Si-CMOS, which is characterized in that step
11) the interconnection bump metal at the Si back sides is Au, Cu, Sn, In, Ti or Ni in, and thickness is in 1-20um, and diameter is in 1-50um.
9. a kind of GaN-HEMT according to claim 1 and the single chip integrated methods of Si-CMOS, which is characterized in that step
13) the positive interconnection bump metals of GaN are Au, Cu, Sn, In, Ti or Ni in, and thickness is in 1-20um, and diameter is in 1-50um.
10. a kind of GaN-HEMT according to claim 1 and the single chip integrated methods of Si-CMOS, which is characterized in that step
14) in, bonding temperature is at 150 DEG C -400 DEG C, and bonding pressure is in 400mbar-6000mbar, and bonding time was at 10-200 minutes.
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| CN110600414A (en) * | 2019-08-01 | 2019-12-20 | 中国科学院微电子研究所 | Wafer heterogeneous alignment method and device |
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| CN113808963A (en) * | 2021-08-25 | 2021-12-17 | 西安电子科技大学 | Manufacturing method and device of gold-free interconnected gallium nitride CMOS |
| CN115910782A (en) * | 2022-12-29 | 2023-04-04 | 北京大学东莞光电研究院 | Method for manufacturing normally-off high electron mobility transistor |
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| CN112340694B (en) * | 2020-11-03 | 2023-05-12 | 中国电子科技集团公司第二十九研究所 | Preparation method of glass micro-channel radiator for gallium nitride power amplifier chip |
| CN113808963A (en) * | 2021-08-25 | 2021-12-17 | 西安电子科技大学 | Manufacturing method and device of gold-free interconnected gallium nitride CMOS |
| CN115910782A (en) * | 2022-12-29 | 2023-04-04 | 北京大学东莞光电研究院 | Method for manufacturing normally-off high electron mobility transistor |
| CN115910782B (en) * | 2022-12-29 | 2023-09-22 | 北京大学东莞光电研究院 | Method for manufacturing normally-off high electron mobility transistor |
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