CN111952282A - Transistor and preparation method thereof - Google Patents
Transistor and preparation method thereof Download PDFInfo
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- CN111952282A CN111952282A CN201910405081.6A CN201910405081A CN111952282A CN 111952282 A CN111952282 A CN 111952282A CN 201910405081 A CN201910405081 A CN 201910405081A CN 111952282 A CN111952282 A CN 111952282A
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 177
- 239000002184 metal Substances 0.000 claims abstract description 177
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 35
- 230000005669 field effect Effects 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 23
- 238000000059 patterning Methods 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 230000000149 penetrating effect Effects 0.000 abstract 2
- 229910002601 GaN Inorganic materials 0.000 description 14
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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Abstract
The application relates to the technical field of semiconductors, and discloses a transistor and a preparation method thereof, wherein the transistor comprises: a substrate; the buffer layer, the channel layer, the barrier layer, the first drain electrode, the first gate electrode, the first source electrode, the first drain metal lead region, the first gate metal lead region and the first source metal lead region are formed on one side of the substrate; the first dielectric layer is formed on the other side of the substrate, and the second drain electrode, the second gate electrode, the second source electrode, the second drain metal lead area, the second gate metal lead area and the second source metal lead area are positioned in the first dielectric layer; the first source electrode metal lead area and the second drain electrode metal lead area are electrically connected through a first through hole penetrating through the substrate; the first grid metal lead region and the second source metal lead region are electrically connected through a second through hole penetrating through the substrate. The transistor disclosed by the application shortens the length of the interconnection line, reduces the parasitic effect, reduces the chip area and reduces the cost.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and particularly to a transistor and a method for fabricating the same.
Background
Due to the excellent characteristics of wide band gap, high breakdown electric field, high electron mobility, high saturated electron drift velocity and the like, the High Electron Mobility Transistor (HEMT) based on the AlGaN (aluminum gallium nitride)/GaN (gallium nitride) heterojunction is very suitable for application occasions of high temperature, high voltage, high frequency, high power density and the like, and has good application prospect in the fields of microwave radio frequency, power electronics and the like.
The AlGaN/GaN heterojunction HEMT is a normally-on depletion mode device, and is prone to unsafe problems such as mis-turn-on in power electronic applications, which hinders the application of GaN HEMT (gallium nitride high electron mobility transistor) devices. For this reason, recessed gates, p-GaN gates, and under-gate fluorine ion implantation have been proposed to deplete the two-dimensional electron gas (2DEG) under the gate to achieve normally-off operation. These methods can achieve normally-off operation, but they have problems such as low and unstable threshold voltage and poor device reliability. The method for realizing the normally-off operation of the GaN transistor is also one of the methods for realizing the normally-off operation of the GaN transistor through high-voltage normally-on GaNHEMT and low-voltage normally-off Si MOSFET (silicon-based metal-oxide-semiconductor field effect transistor) Cascode cascade (cascade hybrid cascade), but the existing method has certain limitations.
In the prior art, as shown in fig. 1, an independent high-voltage normally-on GaN HEMT chip and an independent low-voltage normally-off Si MOSFET chip are cascaded, so that packaging difficulty is increased, a larger parasitic inductance is introduced, and performance and reliability of a device are reduced. Or as shown in fig. 2, the high-voltage normally-on GaN HEMT and the low-voltage normally-off Si MOSFET are monolithically integrated on the same plane of the Si substrate and are connected through the interconnection metal 17, so that although the length of the interconnection line 16 can be shortened and the parasitic effect can be reduced, the interconnection line occupies a larger chip area, which is not beneficial to reducing the cost.
Disclosure of Invention
The invention provides a transistor, which integrates a high-voltage normally-on gallium nitride high electron mobility transistor and a low-voltage normally-off silicon-based metal-oxide-semiconductor field effect transistor on the front and back surfaces of the same substrate in a single chip manner, and is beneficial to reducing the area of a chip, improving the utilization rate of a wafer and reducing the cost.
In order to achieve the above object, the present invention provides a transistor comprising:
a substrate;
a buffer layer, a channel layer and a barrier layer which are stacked in sequence are formed on one side of the substrate, and a first drain electrode, a first gate electrode, a first source electrode, a first drain metal lead region, a first gate metal lead region and a first source metal lead region which are used for forming a high electron mobility transistor are formed on one side of the barrier layer, which is far away from the channel layer; wherein the first drain electrode is electrically connected to the first drain metal lead region, the first gate electrode is electrically connected to the first gate metal lead region, and the first source electrode is electrically connected to the first source metal lead region;
a first dielectric layer, a second drain electrode, a second gate electrode, a second source electrode, a second drain metal lead region, a second gate metal lead region and a second source metal lead region which are positioned in the first dielectric layer and used for forming a semiconductor field effect transistor are formed on the other side of the substrate; wherein the second drain electrode is electrically connected to the second drain metal lead region, the second gate electrode is electrically connected to the second gate metal lead region, and the second source electrode is electrically connected to the second source metal lead region;
the first source electrode metal lead region is opposite to the second drain electrode metal lead region and is electrically connected with the second drain electrode metal lead region through a conductor filled in the first through hole of the substrate; the first grid metal lead region is opposite to the second source metal lead region and is electrically connected with the second source metal lead region through a conductor filled in the second through hole of the substrate.
According to the transistor provided by the invention, the high electron mobility transistor and the semiconductor field effect transistor are respectively formed on two sides of the substrate, wherein in the metal lead area, the first source metal lead area corresponds to the second drain metal lead area and is electrically connected through the first through hole; the first grid metal lead region corresponds to the second source metal lead region and is electrically connected with the second through hole. The transistor structure effectively utilizes two sides of the substrate, and the metal lead regions of the high electron mobility transistor and the semiconductor field effect transistor are communicated through the through holes, so that the length of the interconnection line is shortened.
Therefore, the transistor provided by the invention not only shortens the length of the interconnection line and reduces the parasitic effect, but also reduces the chip area, improves the wafer utilization rate and reduces the cost.
Preferably, the conductive body filled in the first via hole is made of a metal material; and/or the presence of a gas in the gas,
the electric conductor filled in the second through hole is made of a metal material.
Preferably, a dielectric layer is arranged between the side wall of the first via hole and the conductor filled in the first via hole; and/or the presence of a gas in the gas,
and a dielectric layer is arranged between the side wall of the second through hole and the electric conductor filled in the second through hole.
Preferably, the aperture of the first via hole and the aperture of the second via hole are 20-100 um.
Preferably, the surfaces of the high electron mobility transistor and the semiconductor field effect transistor are both provided with a passivation layer.
The invention also provides a preparation method of the transistor, which comprises the following steps:
forming a buffer layer, a channel layer and a barrier layer on one side of the substrate;
forming an electrode and a metal lead area on one side of the barrier layer, which is far away from the channel layer, and forming patterns of the electrode and the metal lead area through a composition process, wherein the patterns of the electrode and the metal lead area comprise a first drain electrode, a first gate electrode, a first source electrode, a first drain metal lead area, a first gate metal lead area and a first source metal lead area which are used for forming the high electron mobility transistor; wherein the first drain electrode is electrically connected to the first drain metal lead region, the first gate electrode is electrically connected to the first gate metal lead region, and the first source electrode is electrically connected to the first source metal lead region;
forming a first dielectric layer on the surface of one side of the substrate, which is far away from the buffer layer, forming a pattern of the first dielectric layer through a composition process, and forming through holes in the first dielectric layer and the substrate at positions corresponding to the first gate metal lead area and the first source metal lead area so as to expose the first gate metal lead area and the first source metal lead area;
and forming an electrode and a metal lead area of the semiconductor field effect transistor on one side of the first dielectric layer, which is far away from the substrate, and forming an electrode and metal lead area pattern through a composition process, wherein the electrode and metal lead area pattern comprises a second drain electrode, a second gate electrode, a second source electrode, a second drain metal lead area, a second gate metal lead area, a second source metal lead area and a conductor, wherein the second drain electrode, the second gate electrode, the second source metal lead area and the conductor are used for forming the semiconductor field effect transistor, and the conductor is positioned in the through hole and is used for electrically connecting the first source metal lead area with the second drain metal lead area and the first gate metal lead area with the second source metal lead area.
Preferably, before forming the first dielectric layer on the side of the substrate facing away from the buffer layer, the method further includes:
patterning a side of the substrate opposite to the buffer layer to form via holes at portions of the substrate corresponding to the first source metal lead region and the first gate metal lead region to expose the first source metal lead region and the first gate metal lead region;
forming a first dielectric layer on the surface of one side of the substrate, which is far away from the buffer layer, and forming a pattern of the first dielectric layer through a composition process:
and simultaneously filling a dielectric material in the through hole formed in the substrate, and patterning the dielectric material filled in the through hole formed in the substrate to form the through hole in the patterning process.
Preferably, before forming the first dielectric layer on the surface of the substrate on the side away from the buffer layer, the method further includes:
and depositing a passivation layer on the surface of the high electron mobility crystal.
Preferably, after the semiconductor field effect transistor is formed, the method further includes:
and depositing a passivation layer on the surface of the semiconductor field effect transistor.
The invention also provides an electronic device comprising a transistor as described in any of the above.
Drawings
Fig. 1 is a schematic structural diagram of a transistor in the prior art;
FIG. 2 is a schematic diagram of another prior art transistor structure;
FIG. 3 is a schematic diagram of a structure of a transistor cell region according to the present application;
FIG. 4 is a schematic diagram of a metal wiring region of a transistor according to the present application;
FIG. 5 is a simplified top view of a transistor according to the present application;
fig. 6 is a flow chart of a method for manufacturing a transistor according to the present application.
In the figure:
1-a substrate; 2-a buffer layer; 3-a channel layer; 4-barrier layer; 5-a first drain electrode; 6-a first gate electrode; 7-a first source electrode; 8-a second drain electrode; 9-a second gate electrode; 10-a second source electrode; heavily doping the 11-N + type drain region; doping a 12-P well; heavily doping a 13-N + source region; heavily doping a 14-P + source region; 15-a first dielectric layer; 16-an interconnection line; 17-an interconnect metal; 18-a first drain metal lead region; 19-a first gate metal lead region; 20-a first source metal lead region; 21-a second drain metal lead region; 22-a second source metal lead region; 23-a second gate metal lead region; 24-a first via; 25-a second via; 26-an electrical conductor; 27-a dielectric layer; 28-cellular region.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 3 and fig. 4, the present invention provides a transistor, including: a substrate 1;
a buffer layer 2, a channel layer 3 and a barrier layer 4 which are stacked in sequence are formed on one side of a substrate 1, and a first drain electrode 5, a first gate electrode 6, a first source electrode 7, a first drain metal lead region 18, a first gate metal lead region 19 and a first source metal lead region 20 which are used for forming a high electron mobility transistor are formed on one side of the barrier layer 4 which is away from the channel layer 3; wherein the first drain electrode 5 is electrically connected to the first drain metal lead region 18, the first gate electrode 6 is electrically connected to the first gate metal lead region 19, and the first source electrode 7 is electrically connected to the first source metal lead region 20;
a first dielectric layer 15 and a second drain electrode 8, a second gate electrode 9, a second source electrode 10, a second drain metal lead region 21, a second source metal lead region 22 and a second gate metal lead region 23 which are positioned in the first dielectric layer 15 and used for forming a semiconductor field effect transistor are formed on the other side of the substrate 1; wherein the second drain electrode 8 is electrically connected to the second drain metal lead region 21, the second gate electrode 9 is electrically connected to the second gate metal lead region 23, and the second source electrode 10 is electrically connected to the second source metal lead region 22;
wherein, the first source metal lead region 20 is opposite to the second drain metal lead region 21 and is electrically connected through the conductor 26 filled in the first via hole 24 of the substrate 1; the first gate metal lead region 19 is opposite to the second source metal lead region 22 and is electrically connected through a conductor 26 filled in a second via 25 of the substrate 1.
In the transistor provided by the invention, a high electron mobility transistor and a semiconductor field effect transistor are respectively formed on two sides of a substrate 1, wherein, in a metal lead area, a first source metal lead area 20 corresponds to a second drain metal lead area 21 and is electrically connected through a first through hole 24; the first gate metal lead region 19 corresponds to the second source metal lead region 22 and is electrically connected through the second via 25. The transistor structure effectively utilizes two sides of the substrate 1, and metal lead regions of the gallium nitride high electron mobility transistor and the semiconductor field effect transistor are communicated through the through holes, so that the length of the interconnection line is shortened.
Therefore, the transistor provided by the invention not only shortens the length of the interconnection line and reduces the parasitic effect, but also reduces the chip area, improves the wafer utilization rate and reduces the cost.
Specifically, the substrate 1 in the invention can be an N-type Si substrate, the buffer layer 2 can be gallium nitride, gallium aluminum nitride with aluminum composition change, aluminum nitride, or a combination or a periodic combination thereof, the thickness of the buffer layer 2 can be 100nm to 6um, the material of the barrier layer 4 can be gallium aluminum nitride, the thickness of the barrier layer 4 is 10 to 30nm, and the aluminum composition is 10 to 30%.
Specifically, the conductive body 26 filled in the first via hole 24 is a metal material; and/or the conductive body 26 filled in the second via 25 is a metal material. The metal material is used as a good conductive medium, so that the conductive effect can be greatly facilitated, and the preparation of the transistor is facilitated.
Further, a dielectric layer is arranged between the side wall of the first via hole 24 and the conductive body 26 filled in the first via hole 24; and/or a dielectric layer is arranged between the side wall of the second via hole 25 and the conductive body 26 filled in the second via hole 25, and the dielectric layer 27 can better avoid the conduction between the conductive body 26 and the side wall of the substrate 1.
Preferably, the aperture of the first via hole 24 and the second via hole 25 is 20-100 um.
Specifically, as an implementable solution, the transistor provided by the present invention further includes an N-type heavily doped layer and a P-type doped layer located on a side of the first dielectric layer 15 facing the substrate 1, as shown in fig. 3, a portion corresponding to the second drain electrode 8 has an N + type heavily doped drain region 11, a portion corresponding to the second source electrode 10 has an N + source region heavily doped 13 and a P + source region heavily doped source region 14, and portions corresponding to the second source electrode 10 and the second gate electrode 9 have a P-well doped 12.
Specifically, as an alternative embodiment, as shown in fig. 5, taking a semiconductor field effect transistor as an example, the second drain metal lead region 21, the second gate metal lead region 23 and the second source metal lead region 22 in the metal lead region are respectively located at two sides of the cell region 28; correspondingly, the metal wiring regions of the high electron mobility transistors on the other side of the substrate 1 are disposed correspondingly.
Based on the same invention concept, the invention also provides a preparation method of the transistor, as shown in fig. 6, comprising the following steps:
s101: forming a buffer layer 2, a channel layer 3 and a barrier layer 4 on one side of a substrate 1;
s102: forming an electrode and a metal lead region of the high electron mobility transistor on a side of the barrier layer 4 facing away from the channel layer 3, and forming a pattern of the electrode and the metal lead region by a patterning process, wherein the pattern of the electrode and the metal lead region includes a first drain electrode 5, a first gate electrode 6, a first source electrode 7, a first drain metal lead region 18, a first gate metal lead region 19, and a first source metal lead region 20 for forming the high electron mobility transistor; wherein the first drain electrode 5 is electrically connected to the first drain metal lead region 18, the first gate electrode 6 is electrically connected to the first gate metal lead region 19, and the first source electrode 7 is electrically connected to the first source metal lead region 20;
s103: forming a first dielectric layer 15 on the surface of one side of the substrate 1, which is far away from the buffer layer 2, forming a pattern of the first dielectric layer 15 through a composition process, and forming through holes in the first dielectric layer 15 and the part of the substrate 1, which corresponds to the first gate metal lead area 19 and the first source metal lead area 20, so as to expose the first gate metal lead area 19 and the first source metal lead area 20;
s104: and forming an electrode and a metal lead area of the semiconductor field effect transistor on the side of the first dielectric layer 15, which is far away from the substrate 1, and forming an electrode and metal lead area pattern through a patterning process, wherein the electrode and metal lead area pattern comprises a second drain electrode 8, a second gate electrode 9, a second source electrode 10, a second drain metal lead area 21, a second gate metal lead area 23 and a second source metal lead area 22 for forming the semiconductor field effect transistor, and a conductor 26 which is positioned in the through hole and is filled to electrically connect the first source metal lead area 20 with the second drain metal lead area 21 and the first gate metal lead area 19 with the second source metal lead area 22.
According to the preparation method of the transistor, in the preparation process, the high electron mobility transistor and the semiconductor field effect transistor are respectively formed on two sides of the substrate 1, the through hole is formed in the substrate 1, and the metal lead area of the high electron mobility transistor is communicated with the metal lead area of the semiconductor field effect transistor, so that the length of an interconnection line is shortened, and the parasitic effect is reduced; but also is beneficial to reducing the area of the chip and the cost.
Before a first dielectric layer 15 is formed on the surface of one side of the substrate 1, which is far away from the buffer layer 2, the substrate 1 needs to be thinned, and in the process of thinning the substrate 1, the substrate 1 is thinned to 50-500 um by adopting a chemical mechanical polishing process generally.
Specifically, as an alternative embodiment, before forming the first dielectric layer 15 on the side of the substrate 1 facing away from the buffer layer 2, the method further includes:
patterning a side of the substrate 1 away from the buffer layer 2 to form via holes at portions of the substrate 1 corresponding to the first source metal lead region 20 and the first gate metal lead region 19 to expose the first source metal lead region 20 and the first gate metal lead region 19;
when a first dielectric layer 15 is formed on the surface of the substrate 1 on the side away from the buffer layer 2, and the pattern of the first dielectric layer 15 is formed through the composition process:
and simultaneously filling a dielectric material in the via hole formed in the substrate 1, and patterning the dielectric layer 27 filled in the via hole formed in the substrate 1 to form the via hole in the patterning process.
In this embodiment, before the first dielectric layer 15 is formed, the first via hole 24 and the second via hole 25 may be formed, and when the first dielectric layer 15 is formed later, the first via hole 24 and the second via hole 25 may be filled with the material of the first dielectric layer 15, and then the first via hole 24 and the second via hole 25 may be subjected to a patterning process to form a via hole and fill a conductor. The above scheme is mainly convenient for filling the first via hole 24 and the second via hole 25 by using the material of the first dielectric layer 15 as the dielectric layer 27 when the first dielectric layer 15 is formed. Or after the first via hole 24 and the second via hole 25 are formed, the dielectric material is filled in the two via holes, and then the first dielectric layer 15 is formed.
Further, as an optional embodiment, before forming the first dielectric layer 15 on the surface of the substrate 1 on the side away from the buffer layer 2, the method further includes: the passivation layer is deposited on the surface of the high electron mobility crystal, so that the reliability and the stability of the high electron mobility crystal can be improved.
Further, as an optional embodiment, after forming the semiconductor field effect transistor, the method further includes: the passivation layer is deposited on the surface of the semiconductor field effect transistor, so that the reliability and the stability of the semiconductor field effect transistor can be improved.
Further, when forming the semiconductor field effect transistor, a via hole may be formed by etching at a position on the substrate corresponding to the second drain metal lead region 21 and the second source metal lead region 22, and the via hole may be filled with a conductive material and a dielectric material, and then an electrode may be formed on the first dielectric layer 15 to form the semiconductor field effect transistor; alternatively, an electrode may be formed on the first dielectric layer 15, a via hole may be formed in the substrate at a position corresponding to the second drain metal lead region 21 and the second source metal lead region 22, and a conductive material and a dielectric material may be filled in the via hole.
Based on the same inventive concept, the present application also provides an electronic device including a transistor having any of the above characteristics.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A transistor, comprising:
a substrate;
a buffer layer, a channel layer and a barrier layer which are stacked in sequence are formed on one side of the substrate, and a first drain electrode, a first gate electrode, a first source electrode, a first drain metal lead region, a first gate metal lead region and a first source metal lead region which are used for forming a high electron mobility transistor are formed on one side of the barrier layer, which is far away from the channel layer; wherein the first drain electrode is electrically connected to the first drain metal lead region, the first gate electrode is electrically connected to the first gate metal lead region, and the first source electrode is electrically connected to the first source metal lead region;
a first dielectric layer, a second drain electrode, a second gate electrode, a second source electrode, a second drain metal lead region, a second gate metal lead region and a second source metal lead region which are positioned in the first dielectric layer and used for forming a semiconductor field effect transistor are formed on the other side of the substrate; wherein the second drain electrode is electrically connected to the second drain metal lead region, the second gate electrode is electrically connected to the second gate metal lead region, and the second source electrode is electrically connected to the second source metal lead region;
the first source electrode metal lead region is opposite to the second drain electrode metal lead region and is electrically connected with the second drain electrode metal lead region through a conductor filled in the first through hole of the substrate; the first grid metal lead region is opposite to the second source metal lead region and is electrically connected with the second source metal lead region through a conductor filled in the second through hole of the substrate.
2. The transistor of claim 1, wherein the conductive body filled in the first via is a metal material; and/or the presence of a gas in the gas,
the electric conductor filled in the second through hole is made of a metal material.
3. The transistor of claim 1, wherein a dielectric layer is disposed between a sidewall of the first via and the conductor filled in the first via; and/or the presence of a gas in the gas,
and a dielectric layer is arranged between the side wall of the second through hole and the electric conductor filled in the second through hole.
4. The transistor of claim 1, wherein the first and second vias have an aperture of 20-100 um.
5. The transistor of claim 1, wherein the surfaces of the high electron mobility transistor and the semiconductor field effect transistor are each provided with a passivation layer.
6. A method of forming a transistor as claimed in any one of claims 1 to 5, comprising:
forming a buffer layer, a channel layer and a barrier layer on one side of a substrate;
forming an electrode and a metal lead area of the high electron mobility transistor on one side of the barrier layer, which is far away from the channel layer, and forming a pattern of the electrode and the metal lead area through a composition process, wherein the pattern of the electrode and the metal lead area comprises a first drain electrode, a first gate electrode, a first source electrode, a first drain metal lead area, a first gate metal lead area and a first source metal lead area which are used for forming the high electron mobility transistor; wherein the first drain electrode is electrically connected to the first drain metal lead region, the first gate electrode is electrically connected to the first gate metal lead region, and the first source electrode is electrically connected to the first source metal lead region;
forming a first dielectric layer on the surface of one side of the substrate, which is far away from the buffer layer, forming a pattern of the first dielectric layer through a composition process, and forming through holes in the first dielectric layer and the substrate at positions corresponding to the first gate metal lead area and the first source metal lead area so as to expose the first gate metal lead area and the first source metal lead area;
and forming an electrode and a metal lead area of the semiconductor field effect transistor on one side of the first dielectric layer, which is far away from the substrate, and forming an electrode and metal lead area pattern through a composition process, wherein the electrode and metal lead area pattern comprises a second drain electrode, a second gate electrode, a second source electrode, a second drain metal lead area, a second gate metal lead area, a second source metal lead area and a conductor, wherein the second drain electrode, the second gate electrode, the second source metal lead area and the conductor are used for forming the semiconductor field effect transistor, and the conductor is positioned in the through hole and is used for electrically connecting the first source metal lead area with the second drain metal lead area and the first gate metal lead area with the second source metal lead area.
7. The method for manufacturing a transistor according to claim 6, wherein before forming the first dielectric layer on the side of the substrate facing away from the buffer layer, the method further comprises:
patterning a side of the substrate opposite to the buffer layer to form via holes at portions of the substrate corresponding to the first source metal lead region and the first gate metal lead region to expose the first source metal lead region and the first gate metal lead region;
forming a first dielectric layer on the surface of one side of the substrate, which is far away from the buffer layer, and forming a pattern of the first dielectric layer through a composition process:
and simultaneously filling a dielectric material in the through hole formed in the substrate, and patterning the dielectric material filled in the through hole formed in the substrate to form the through hole in the patterning process.
8. The method for manufacturing a transistor according to claim 6, wherein before forming the first dielectric layer on a surface of the substrate on a side away from the buffer layer, the method further comprises:
and depositing a passivation layer on the surface of the high electron mobility crystal.
9. The method for manufacturing a transistor according to claim 6, further comprising, after forming the semiconductor field effect transistor:
and depositing a passivation layer on the surface of the semiconductor field effect transistor.
10. An electronic device comprising the transistor according to any one of claims 1 to 5.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115910782A (en) * | 2022-12-29 | 2023-04-04 | 北京大学东莞光电研究院 | Method for manufacturing normally-off high electron mobility transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012144100A1 (en) * | 2011-04-22 | 2012-10-26 | 次世代パワーデバイス技術研究組合 | Nitride semiconductor device |
| US20130240898A1 (en) * | 2012-03-15 | 2013-09-19 | International Rectifier Corporation | Group III-V and Group IV Composite Switch |
| US20140091366A1 (en) * | 2012-09-28 | 2014-04-03 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| US20150162424A1 (en) * | 2013-12-06 | 2015-06-11 | International Re'ctifier Corporation | Dual-Gated Group III-V Merged Transistor |
| EP2991104A2 (en) * | 2014-08-29 | 2016-03-02 | International Rectifier Corporation | Monolithic integrated composite group iii-v and group iv semiconductor device and ic |
-
2019
- 2019-05-16 CN CN201910405081.6A patent/CN111952282A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012144100A1 (en) * | 2011-04-22 | 2012-10-26 | 次世代パワーデバイス技術研究組合 | Nitride semiconductor device |
| US20130240898A1 (en) * | 2012-03-15 | 2013-09-19 | International Rectifier Corporation | Group III-V and Group IV Composite Switch |
| US20140091366A1 (en) * | 2012-09-28 | 2014-04-03 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| US20150162424A1 (en) * | 2013-12-06 | 2015-06-11 | International Re'ctifier Corporation | Dual-Gated Group III-V Merged Transistor |
| EP2991104A2 (en) * | 2014-08-29 | 2016-03-02 | International Rectifier Corporation | Monolithic integrated composite group iii-v and group iv semiconductor device and ic |
Non-Patent Citations (1)
| Title |
|---|
| 施敏: "《半导体器件物理》", 30 June 2008, 西安交通大学出版社 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115910782A (en) * | 2022-12-29 | 2023-04-04 | 北京大学东莞光电研究院 | Method for manufacturing normally-off high electron mobility transistor |
| CN115910782B (en) * | 2022-12-29 | 2023-09-22 | 北京大学东莞光电研究院 | Method for manufacturing normally-off high electron mobility transistor |
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