CN109888011A - Semiconductor structure and its manufacturing method - Google Patents
Semiconductor structure and its manufacturing method Download PDFInfo
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- CN109888011A CN109888011A CN201910184346.4A CN201910184346A CN109888011A CN 109888011 A CN109888011 A CN 109888011A CN 201910184346 A CN201910184346 A CN 201910184346A CN 109888011 A CN109888011 A CN 109888011A
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- heterojunction structure
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Abstract
The present invention relates to a kind of semiconductor structures, comprising: substrate and the buffer layer on the substrate；Doped layer on the buffer layer source region and drain region；The first heterojunction structure on the buffer layer and between the doped layer；Grid on first heterojunction structure and positioned on first heterojunction structure and being located at least one heterojunction structure of the grid opposite sides.The semiconductor structure and its manufacturing method that the application is proposed reduce the conducting resistance of device by forming multiple heterojunction structures to form the conducting channel of a plurality of parallel connection.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure and its manufacturing method.
Background technique
As the representative of third generation semiconductor material, gallium nitride (GaN) has many excellent characteristics, high critical breakdown potential
Field, high electron mobility, high two-dimensional electron gas and good high temperature operation capability etc..The third generation based on gallium nitride is partly led
Application has been obtained in body device, such as high electron mobility transistor (HEMT), hetero-structure field effect transistor (HFET),
Especially high-power and high-frequency field is needed to have a clear superiority in radio frequency, microwave etc..
For HEMT HFET device, the channel conducting from source electrode to drain electrode mainly passes through AlGaN (gallium nitride
Aluminium) and the interface GaN two-dimensional electron gas (2DEG) Lai Shixian.But since AlGaN and GaN is all close to insulator, have compared with
Big contact resistance, the conducting resistance for resulting in entire device is larger, limits the use scope of device.
Summary of the invention
The application proposes a kind of semiconductor structure, comprising:
Substrate and the buffer layer on the substrate；
Doped layer on the buffer layer source region and drain region；
The first heterojunction structure on the buffer layer and between the doped layer；
Grid on first heterojunction structure and it is located on first heterojunction structure and is located at the grid
At least one heterojunction structure of pole opposite sides.
In one embodiment, at least one described heterojunction structure includes ion doping portion, the ion doping portion and institute
Doped layer is stated to be in contact.
In one embodiment, the ion be n-type silicon ion or be n-type silicon ion and N-shaped oxonium ion mixing from
Son.
In one embodiment, the doped layer of the source region be equipped with source electrode, the drain region doped layer on
Equipped with drain electrode.
In one embodiment, the medium for reducing electric leakage of the grid is equipped between the grid and the first heterojunction structure
Layer.
Correspondingly, the application proposes a kind of manufacturing method of semiconductor structure, comprising:
Substrate is provided, forms buffer layer over the substrate；
The first heterojunction structure is formed on the buffer layer, forms at least one hetero-junctions on first heterojunction structure
Structure；
Source region and drain region heterojunction structure is performed etching, until exposing portion of buffer layer, and sudden and violent
Doped layer is formed on the portion of buffer layer of exposing；
The heterojunction structure in etching grid region, until exposing the first heterojunction structure of part, to form gate window, and
Grid is formed in the gate window.
In one embodiment, source region and drain region heterojunction structure is performed etching, until exposing portion
The step of point buffer layer includes:
A layer photoresist is coated on the heterojunction structure surface on top；
Source region and drain region are defined by exposing, developing；
The heterojunction structure of the drain region of the source region is performed etching.
In one embodiment, the heterojunction structure in etching grid region, the step until exposing the first heterojunction structure of part
Suddenly include:
A layer photoresist is coated on the heterojunction structure surface on top；
Area of grid is defined by exposing, developing；
The heterojunction structure of the area of grid is performed etching.
In one embodiment, the doped layer is n-type doping layer, and doping concentration is greater than 2 × 1019cm-3。
The semiconductor structure and its manufacturing method that the application is proposed, it is a plurality of to be formed by forming multiple heterojunction structures
Conducting channel in parallel, reduces the conducting resistance of device.
Detailed description of the invention
The semiconductor structure schematic diagram that Fig. 1 is proposed by one embodiment；
The semiconductor structure schematic diagram that Fig. 2 is proposed by one embodiment；
Fig. 3 is the flow chart of semiconductor structure manufacturing method；
The schematic diagram for the semiconductor structure manufacturing method that Fig. 4-Fig. 7 is proposed by one embodiment.
Specific embodiment
Semiconductor structure proposed by the present invention and its manufacturing method are made below in conjunction with the drawings and specific embodiments further
It is described in detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing
It is all made of very simplified form and uses non-accurate ratio, only to convenient, lucidly the aid illustration present invention is implemented
The purpose of example.
In the present invention, in " forming layer on another layer ", rectangular stratification on another layer may mean that, but different
Given layer directly physically or electrically contacts (for example, may exist other one or more layers between the two layers) with another layer.However,
In some embodiments, " ... it is upper to be formed " it can be connect with expression layer and the direct physics of at least part of another layer of top surface
Touching.
In embodiment as shown in Figure 1, the semiconductor structure includes that substrate 10, buffer layer 20, doped layer 30, first are different
Matter structure 40, grid 50, the second heterojunction structure 60, third heterojunction structure 70, source electrode 80 and drain electrode 90.The substrate 10 include but
It is not limited to the materials such as sapphire, silicon carbide, silicon, diamond, gallium nitride and aluminium nitride.The buffer layer 20 is located at the substrate 10
On, the buffer layer 20 can be GaN, InN, AlN, AlGaN, the nitride such as InGaN, with a thickness of 10nm-10um is greater than.It is described
Doped layer 30 is located at the source region and drain region of the buffer layer 20, and the doped layer 30 is N-shaped GaN doping.The source
Pole 80 is located on the doped layer 30 of the source region, and the drain electrode 90 is located on the doped layer 30 of the drain region.It is described
First heterojunction structure 40 is located on the buffer layer 20, and between the doped layer 30.The grid 50 is located at described the
On one heterojunction structure 40.Second heterojunction structure 60 is located on first heterojunction structure 50, and is located at the grid 50
Opposite sides.The third heterojunction structure 70 is located on second heterojunction structure 60, and is located at the two sides of the grid 50.
The heterojunction structure includes channel layer and barrier layer, and the barrier layer is located at the top of the channel layer.The ditch
Road layer material can be identical as 20 material of buffer layer, with a thickness of 10nm-200nm.The barrier layer can be AlGaN,
One or more of superpositions of the alloy materials such as InAlN, AlN, ScAlN, with a thickness of 3nm-100nm.The channel layer is close to institute
The end surface for stating barrier layer is formed with two-dimensional electron gas, provides conducting channel.First heterojunction structure, the second heterojunction structure
It can have identical material with the channel layer of third heterojunction structure, same thickness can also be different materials respectively, different thick
Degree.The barrier layer of first heterojunction structure, the second heterojunction structure and third heterojunction structure can have identical material, identical thickness
Degree, can also be different materials, different-thickness respectively.In the present embodiment, there are three heterojunction structures for tool, that is, there are three two dimensions
Electron gas is connected in parallel to each other between three two-dimensional electron gas, can effectively reduce conducting resistance.Grid is located at the first hetero-junctions simultaneously
On structure, and the second heterojunction structure and third heterojunction structure are divided into two parts respectively, three two dimensions can control by grid
The on-off of electron gas.It will be appreciated by persons skilled in the art that the heterojunction structure of other quantity also belongs to the protection of the application
Range.
In another embodiment, first heterojunction structure, the second heterojunction structure, at least one in third heterojunction structure are different
Matter structure has ion doping portion, and the ion doping portion is in contact with the doped layer.As shown in Fig. 2, described second is heterogeneous
Structure 60 and third heterojunction structure 70 include ion doping portion 67, and the ion doping 67 is in contact with the doped layer 30.Institute
Stating ion is N-shaped ion, can be silicon ion, be also possible to the hybrid ionic of silicon ion and oxonium ion.By to heterojunction structure
Carry out ion doping, the contact resistance that can be further reduced between two-dimensional electron gas and doped layer.Those skilled in the art can
With understanding, the position in the ion doping portion and quantity can change according to actual needs.
In another embodiment, there is also dielectric layers between the grid and the first heterojunction structure, for reducing grid
Leakage current.The dielectric layer can be silica or silicon nitride, and thickness is less than 100nm.
Above-described embodiment is illustrated by taking three heterojunction structures as an example, it will be appreciated by persons skilled in the art that packet
Scheme containing two and more than two heterojunction structures is within the scope of protection of this application.
Correspondingly, the application also proposes a kind of semiconductor structure manufacturing method, as shown in Figure 3, comprising:
S10: substrate is provided, forms buffer layer over the substrate.
As shown in figure 4, the substrate 10 includes but is not limited to sapphire, silicon carbide, silicon, diamond, gallium nitride and nitridation
The materials such as aluminium.The buffer layer 20 is located on the substrate 10, the buffer layer 20 can be GaN, InN, AlN, AlGaN,
The nitride such as InGaN, with a thickness of 10nm-10um.
S20: forming the first heterojunction structure on the buffer layer, and it is different to form at least one on first heterojunction structure
Matter structure；
Specifically, can be formed on the buffer layer 20 by the method for metal organic chemical deposition (MOCVD) multiple
Heterojunction structure.The heterojunction structure includes channel layer and barrier layer, and the channel layer materials can be with 20 material of buffer layer
It is identical, with a thickness of 10nm-200nm.The barrier layer can be the alloy materials such as AlGaN, InAlN, AlN, ScAlN one kind or
Several superposition, with a thickness of 3nm-100nm.The channel layer is formed with Two-dimensional electron close to the end surface of the barrier layer
Gas provides conducting channel.In the present embodiment, as shown in figure 5, shown heterojunction structure is three, respectively the first heterojunction structure
40, the second heterojunction structure 60 and third heterojunction structure 70.First heterojunction structure 40, the second heterojunction structure 60 and third are heterogeneous
The channel layer of structure 70 can have identical material, and same thickness can also be different materials, different-thickness respectively.Described
The barrier layer of one heterojunction structure 40, the second heterojunction structure 60 and third heterojunction structure 70 can have identical material, same thickness,
It can also be different materials, different-thickness respectively.
S30: performing etching source region and drain region heterojunction structure, until exposing portion of buffer layer, and
Doped layer is formed on the buffer layer exposed.
Specifically, the heterojunction structure surface on top coats a layer photoresist, source region is defined by exposing, developing
And drain region, and the heterojunction structure of the drain region of source region is performed etching, until exposing the part buffer layer.
The etching can be dry plasma etch.
Doped layer 30, the doped layer 30 can be formed on the buffer layer exposed by the method for MOCVD
Source region and drain region on the buffer layer 20, the doped layer 30 are that N-shaped GaN doping either N-shaped InGaN mixes
It is miscellaneous, doping, the ion doping concentration of the doped layer 30 can be formed by carrying out ion implanting mode to the doped layer 30
Greater than 2 × 1019cm-3.After the doped layer 30 is formed, remaining photoresist is removed, the structure of formation is as shown in Figure 6.
S40: the heterojunction structure in etching grid region, until exposing the first heterojunction structure of part, to form gate window,
And grid is formed in the gate window.
Specifically, the heterojunction structure on the top coats a layer photoresist again, grid is defined by exposing, developing
Region, and the heterojunction structure of area of grid is performed etching, until exposing the first heterojunction structure of part 40, described first is heterogeneous
It is formd in structure 40 to form the reserved gate window of grid, it then can be using the method for metal evaporation in the grid window
Grid 50 is formed in mouthful, the grid can be ni au or metal laminated, the structure of the formation such as Fig. 7 institute of platinum/gold composition
Show.
In the present embodiment, the method formation source electrode on the doped layer and the leakage respectively of metal evaporation can be passed through
Pole, the source electrode and drain electrode can be the alloy of any a variety of compositions in titanium, aluminium, nickel, gold.
In another embodiment, it is formed before grid, one layer of dielectric layer can be deposited in the gate window, to reduce
The electric leakage of grid.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (9)
1. a kind of semiconductor structure characterized by comprising
Substrate and the buffer layer on the substrate；
Doped layer on the buffer layer source region and drain region；
The first heterojunction structure on the buffer layer and between the doped layer；
Grid on first heterojunction structure and it is located on first heterojunction structure and is located at the grid phase
To at least one heterojunction structure of two sides.
2. semiconductor structure according to claim 1, which is characterized in that at least one described heterojunction structure includes that ion is mixed
Miscellaneous portion, the ion doping portion are in contact with the doped layer.
3. semiconductor structure according to claim 2, which is characterized in that the ion is n-type silicon ion or is n-type silicon
The hybrid ionic of ion and N-shaped oxonium ion.
4. semiconductor structure according to claim 1, which is characterized in that the doped layer of the source region is equipped with source
Pole, the drain region doped layer be equipped with drain electrode.
5. semiconductor structure according to claim 1, which is characterized in that be equipped between the grid and the first heterojunction structure
For reducing the dielectric layer of electric leakage of the grid.
6. a kind of manufacturing method of semiconductor structure characterized by comprising
Substrate is provided, forms buffer layer over the substrate；
The first heterojunction structure is formed on the buffer layer, forms at least one heterojunction structure on first heterojunction structure；
Source region and drain region heterojunction structure is performed etching, until exposing portion of buffer layer, and is being exposed
Portion of buffer layer on form doped layer；
The heterojunction structure in etching grid region, until exposing the first heterojunction structure of part, to form gate window, and described
Grid is formed in gate window.
7. semiconductor structure manufacturing method according to claim 6, which is characterized in that source region and drain region
Heterojunction structure perform etching, until the step of exposing portion of buffer layer includes:
A layer photoresist is coated on the heterojunction structure surface on top；
Source region and drain region are defined by exposing, developing；
The heterojunction structure of the drain region of the source region is performed etching.
8. semiconductor structure manufacturing method according to claim 6, which is characterized in that the hetero-junctions in etching grid region
Structure, until the step of exposing the first heterojunction structure of part includes:
A layer photoresist is coated on the heterojunction structure surface on top；
Area of grid is defined by exposing, developing；
The heterojunction structure of the area of grid is performed etching.
9. semiconductor structure manufacturing method according to claim 6, which is characterized in that the doped layer is n-type doping layer,
Doping concentration is greater than 2 × 1019cm-3。
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| CN201910184346.4A CN109888011A (en) | 2019-03-12 | 2019-03-12 | Semiconductor structure and its manufacturing method |
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| CN201910184346.4A CN109888011A (en) | 2019-03-12 | 2019-03-12 | Semiconductor structure and its manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021012340A1 (en) * | 2019-07-19 | 2021-01-28 | 中国电子科技集团公司第五十五研究所 | Gan high-electron-mobility transistor having splicing sub-device and manufacture method therefor |
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| CN102130159A (en) * | 2011-01-06 | 2011-07-20 | 西安电子科技大学 | High electron mobility transistor |
| US20150028346A1 (en) * | 2011-12-21 | 2015-01-29 | Massachusetts Institute Of Technology | Aluminum nitride based semiconductor devices |
| CN108649071A (en) * | 2018-05-17 | 2018-10-12 | 苏州汉骅半导体有限公司 | Semiconductor devices and its manufacturing method |
| CN109285881A (en) * | 2017-07-19 | 2019-01-29 | 吴绍飞 | High electron mobility transistor |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130159A (en) * | 2011-01-06 | 2011-07-20 | 西安电子科技大学 | High electron mobility transistor |
| US20150028346A1 (en) * | 2011-12-21 | 2015-01-29 | Massachusetts Institute Of Technology | Aluminum nitride based semiconductor devices |
| CN109285881A (en) * | 2017-07-19 | 2019-01-29 | 吴绍飞 | High electron mobility transistor |
| CN108649071A (en) * | 2018-05-17 | 2018-10-12 | 苏州汉骅半导体有限公司 | Semiconductor devices and its manufacturing method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021012340A1 (en) * | 2019-07-19 | 2021-01-28 | 中国电子科技集团公司第五十五研究所 | Gan high-electron-mobility transistor having splicing sub-device and manufacture method therefor |
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