CN117976621B - Through-hole gallium nitride high electron mobility transistor and manufacturing method thereof - Google Patents
Through-hole gallium nitride high electron mobility transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN117976621B CN117976621B CN202410389720.5A CN202410389720A CN117976621B CN 117976621 B CN117976621 B CN 117976621B CN 202410389720 A CN202410389720 A CN 202410389720A CN 117976621 B CN117976621 B CN 117976621B
- Authority
- CN
- China
- Prior art keywords
- hole
- metal
- etching
- layer
- electron mobility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 69
- 238000005530 etching Methods 0.000 claims abstract description 67
- 238000004140 cleaning Methods 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 67
- 239000002184 metal Substances 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 33
- 229910002704 AlGaN Inorganic materials 0.000 claims description 13
- 238000011065 in-situ storage Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000009713 electroplating Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 7
- 238000011161 development Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 4
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims description 2
- 239000006227 byproduct Substances 0.000 abstract description 16
- 238000004506 ultrasonic cleaning Methods 0.000 abstract description 8
- 238000011049 filling Methods 0.000 abstract description 6
- 238000001465 metallisation Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000012459 cleaning agent Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012864 cross contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011086 high cleaning Methods 0.000 description 1
- 239000013072 incoming material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000012188 paraffin wax Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H01L29/66462—
-
- H01L29/778—
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention relates to the technical field of transistors, in particular to a through-hole gallium nitride transistor with high electron mobility and a manufacturing method thereof, comprising the following steps: and manufacturing an etching barrier layer on the front surface of the wafer, patterning, sequentially etching from top to bottom to obtain deep holes, removing residues, and performing metallization hole filling. Because the key structures such as the source, the drain and the grid which influence the characteristics of the device are not manufactured, the cleaning has a very large process window, and the ultrasonic cleaning mode can be adopted to ensure that the hole wall and the hole bottom by-products are completely removed.
Description
Technical Field
The invention relates to the technical field of transistors, in particular to a through-hole gallium nitride transistor with high electron mobility and a manufacturing method thereof.
Background
The GaN High Electron Mobility Transistor (HEMT) has the technical characteristics of high electron mobility, high two-dimensional electron gas concentration and high breakdown electric field, has outstanding advantages in the technical field of high frequency and high voltage, and has gradually become the first choice technology of a radio frequency/microwave power amplifier.
The GaN HEMT process is divided into a front side process and a back side process. The front-side process mainly comprises the process steps of ohmic contact, device isolation, schottky contact, medium passivation, hole opening, wiring and the like; the back surface process mainly comprises the process steps of wafer thinning, through hole manufacturing, scribing channel manufacturing and the like.
The front side process is responsible for forming gate, source and drain electrodes and realizing interconnection of the electrodes, and the back side process realizes interconnection of a front side device and a back side metal grounding surface. The through hole is a necessary element of microstrip transmission and is also a direct path of transistor grounding, and the importance is very outstanding: the quality of the through hole process is directly related to the realization of the functions of the device, the performance of the device and whether the long-term reliability of the device is over-closed.
The typical manufacturing process of the back hole of the GaN HEMT at present mainly comprises the steps of substrate etching, gaN/AlGaN etching, hole cleaning, hole metallization and the like, and the technical key points of the manufacturing process comprise: and controlling the etching depth and consistency of the through holes, and cleaning byproducts at the bottom and the wall of the holes. The via etching process requires the sequential etching of a substrate crystal of approximately hundred microns thick and a GaN/AlGaN layer of one to two microns thick, where the substrate material thickness fluctuates up to several microns or even ten microns, presenting a significant challenge to etch uniformity. In addition, the substrate material is hard and brittle, the etching difficulty is high, high-density fluorine-based plasma is usually adopted for etching, the etching bias power is high, the physical and chemical reaction in the etching process is strong, and common photoresist or medium cannot bear high-strength consumption for a long time, so that a metal hard mask is usually selected to serve as an etching barrier layer in the process of etching the substrate, and a large amount of byproducts are generated in the etching process and are attached to the hole wall and the hole bottom. In order not to affect the subsequent etching of the GaN/AlGaN layer, it must be removed in time. The etching of the GaN/AlGaN layer generally employs a chlorine-based plasma which also has a strong etching capability for the front metal, so that it is necessary to precisely control the etching depth to ensure that the GaN/AlGaN layer is completely etched without excessive loss of the front metal layer. In the GaN/AlGaN etching process, part of the back metal is inevitably consumed, and a large amount of unstable byproducts are formed at the bottom of the hole in the process, so that the unstable byproducts need to be removed before the hole is metallized.
Aiming at the technical difficulties, the industry mainly has the following measures: through process design and process optimization, the etching selection ratio of the substrate and GaN is improved, so that the interface is stopped on the GaN layer after the substrate is etched, the consumption of the GaN layer is less, the hole wall and hole bottom byproducts are soaked and cleaned by adopting a customized cleaning agent after the metal hard mask is removed, and an ultrasonic cleaning method which needs to be overlapped for a certain time can be effectively removed if necessary. Ultrasonic cleaning may damage transistors and may only be used in a limited manner, such a means has a narrow process window and extremely challenges process control capability. In the subsequent GaN/AlGaN etching process, as the barrier layer is consumed to a certain extent during the substrate etching, the GaN thicknesses at different positions have larger difference, the selection ratio of the chlorine-based plasma to GaN and front metal is not high, the consumption situation of the front metal at each point position inevitably has certain difference, and the process also involves the selection problem of a process window, namely: the method ensures the complete etching of GaN/AlGaN and controls the over etching degree. The above requirements have been incorporated into the GJB548C-2021 method for testing microelectronic devices and procedure method 2010.2, which is becoming more and more stringent. At the same time, a large amount of byproducts are generated in the GaN/AlGaN etching process and adhere to the periphery of the hole bottom, and the properties of the GaN/AlGaN etching process are very unstable and must be completely removed before hole metallization. The byproduct removal mode is still custom cleaning agent soaking cleaning, ultrasonic cleaning is overlapped to a certain extent if necessary, and the problem brought by the method is nearly consistent with the byproduct cleaning process after the substrate etching.
In summary, the currently adopted back surface through hole manufacturing process has extremely high requirement on etching consistency, the by-product generated in the etching process has high cleaning difficulty, the cleaning means are limited, the transistor is potentially damaged in the cleaning process with extremely high probability, and the potential failure possibility of the device is formed. Because the process window is narrow, the requirements on the incoming material state and the process control capability are extremely high, various problems are unavoidable in engineering practice, and the yield of the GaN high electron mobility transistor and the circuit thereof is restricted.
Disclosure of Invention
The invention aims to provide a through-hole gallium nitride high-electron mobility transistor and a manufacturing method thereof, which solve the technical problems that the manufacturing process of a back through hole has extremely high requirement on etching consistency and the cleaning difficulty of byproducts generated in the etching process is high in the prior art.
The invention discloses a method for manufacturing a through-hole gallium nitride transistor with high electron mobility, which comprises the following steps:
and manufacturing an etching barrier layer on the front surface of the wafer, patterning, sequentially etching from top to bottom to obtain deep holes, removing residues, and performing metallization hole filling.
Because the key structures such as the source, the drain and the grid which influence the characteristics of the device are not manufactured, the cleaning has a very large process window, and the ultrasonic cleaning mode can be adopted to ensure that the hole wall and the hole bottom by-products are completely removed.
Further, the deep holes are obtained by sequentially etching in-situ SiN, alGaN/GaN and a substrate layer from top to bottom, and the etching of the substrate layer is 80-110 mu m.
Further, the in-situ SiN, alGaN/GaN and substrate layers are etched by ICP-RIE.
Further, the substrate layer material may be silicon carbide, silicon, sapphire, gallium nitride, and diamond.
Further, the seed layer metal is sputtered on the surface of the wafer, and then a patterned etching barrier layer is manufactured.
Further, the seed layer metal is TiW/Au, wherein the thickness of TiW is 200-500A, and the thickness of Au is 1000-2000A.
Further, the etching barrier layer is patterned metal Ni, and the thickness is 5-10 mu m.
Furthermore, the metallization hole filling is specifically performed by seed layer sputtering, electroplating hole filling, metal polishing and metal patterning.
Further, the metal of the filling hole is Au or Cu.
Further, after metal patterning, source drain metal and gate metal are prepared.
Further, after the preparation of the gate metal is completed, the remaining front-side process is continued.
Further, the residual front side process comprises a second dielectric growth, field plate manufacturing, a first metal wiring, a third dielectric growth, a second metal wiring and a front side protection layer.
Further, the front side process is completed and then the back side process is performed.
Further, the back side process includes substrate thinning, back side metal fabrication and debonding.
Further, the thinning process of the back wafer comprises two sections: the first section is used for polishing and thinning the substrate until the through hole metal is slightly exposed, and the second section is used for introducing etching liquid corresponding to the through hole metal into the polishing liquid while continuing to thin the substrate until the thickness of the substrate is thinned to the target thickness, and meanwhile, the through hole metal and the substrate are almost in the same horizontal plane, so that the subsequent process is convenient to develop.
Further, the back side wafer is thinned to 75-100 μm.
A through-hole GaN high electron mobility transistor is prepared by the method.
Compared with the prior art, the invention has the following beneficial effects:
1. The method is characterized in that the through hole process is arranged in front of the source, drain and grid electrodes, so that the damage to the transistor caused by the cleaning process of the through hole etching byproducts is completely avoided, the cleaning process window is wide, and the cleaning effect is fully ensured;
2. The invention introduces a solid electroplating hole filling process, improves the current carrying capacity of the source electrode, effectively reduces the source electrode resistance, and is beneficial to improving the high-frequency characteristic of the device;
3. partial stress is released in advance by the through hole technology, so that the consistency of the device performance and the final device performance after the front process is improved, and the test screening cost is reduced;
4. The first through hole technology does not increase the photoetching mask plate, the number of the steps is equivalent to that of the post through hole technology, and after the technical deficiency of the post through hole is avoided, the first through hole technology is beneficial to improving the manufacturing yield of the gallium nitride high electron mobility transistor, so that the manufacturing cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 shows the epitaxial structure of GaN prior to processing by the process of the invention;
FIG. 2 is a schematic illustration of the wafer front side electroplating etch stop layer and patterning;
FIG. 3 is a plasma etched deep hole;
FIG. 4 is a metallized via;
FIG. 5 is a source drain metal patterning;
FIG. 6 is an etch in-situ SiN;
FIG. 7 shows the completion of source drain metal fabrication;
FIG. 8 is a grown SiN used as a protection and passivation layer;
FIG. 9 is a diagram of the fabrication of a gate metal;
FIG. 10 is a wafer flip-chip bonded to a carrier by a bonding material after the front side process is completed;
FIG. 11 is a substrate grinding thinning;
FIG. 12 is a view of the fabrication of a backside metal;
Fig. 13 is a debonding.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments.
Example 1
The method for manufacturing the through-hole gallium nitride high electron mobility transistor by adopting the device in the embodiment is as shown in fig. 1-13, and comprises the following steps:
A. From fig. 1, it can be seen that from bottom to top: the in-situ growth SiN layer has the thickness of 10-30nm, the growth mode is MOCVD, the in-situ growth SiN layer is used for protecting the surface of a semiconductor, seed layer metal, preferably TiW/Au, is sputtered on the surface of a wafer, wherein the TiW has the thickness of 200-500A and the Au has the thickness of 1000-2000A; the method comprises the steps of firstly electroplating metal Ni on the whole surface, then adopting positive photoresist exposure and development to define a pattern, and then corroding the exposed metal Ni and seed layer metal below the exposed metal Ni; or adopting a mode of negative photoresist exposure and development and then electroplating metal Ni, and removing the negative photoresist blocking the holes after electroplating;
B. etching in-situ SiN, preferably ICP-RIE etching, with F-based plasma at an etching rate of 100-300A/min;
C. etching AlGaN/GaN, preferably ICP-RIE etching, adopting Cl-based plasma with etching rate of 150-300 nm/min, and placing in deionized water for ultrasonic cleaning after etching is completed until byproducts are completely removed;
D. Etching the substrate by ICP-RIE, adopting etching gas corresponding to the substrate material, etching the substrate at the etching rate of 0.8-1.2 mu m/min, and etching the target depth of 80-110 mu m, wherein the etching uniformity is +/-5%, and placing the substrate in deionized water for ultrasonic cleaning until byproducts are completely removed after etching;
E. Corroding metal Ni by adopting a mixed solution of nitric acid and hydrogen peroxide, wherein the corrosion rate is 0.5-1 mu m/min;
F. corroding Au by adopting a special KI corrosive liquid for Au;
G. The TiW is corroded by adopting a heated hydrogen peroxide solution, the heating temperature of the hydrogen peroxide is 40-50 ℃, the ICP-RIE equipment for etching the through holes is provided with a plurality of chambers, etching processes in different atmospheres are respectively carried out in different chambers, cross contamination is avoided, and as key structures which influence the characteristics of devices such as sources, leaks and grids are not manufactured, the cleaning has a very large process window, and an ultrasonic cleaning mode can be adopted to ensure that the hole walls and hole bottom byproducts are completely removed;
H. sputtering seed layer metal again, electroplating metal to fill deep holes, wherein the hole filling metal is Au or Cu;
I. Exposing and developing the polished metal, and corroding to obtain patterned metal;
J. uniformly coating negative photoresist with the thickness of 1.6-2.0 mu m, and exposing and developing to obtain a source drain pattern;
K. etching in-situ SiN, preferably ICP-RIE etching, with F-based plasma at an etching rate of 100-150A/min;
evaporating source and drain metals, typically Ti/Al series multilayer metals, after being cleaned by HCl, wherein the total thickness is 2500-3500A;
M, annealing rapidly by an annealing furnace after stripping to form ohmic contact, wherein typical annealing conditions are 830-870 ℃ and 20-60s;
Growing a layer of medium for protecting the surface of the transistor, wherein the medium is preferably silicon nitride, the growth mode is PECVD, and the thickness of the medium is 800-2000A;
O, device isolation, preferably adopting a plane isolation mode of ion implantation, wherein the ions are F, B, N and the like;
P, medium open pore, expose the metal pattern of source drain;
q, manufacturing a gate electrode, firstly adopting positive photoresist for exposure and development, then etching SiN to define a gate foot, then adopting negative photoresist for exposure and development, evaporating gate metal, and stripping to form the structure shown in figure 9, wherein typical metal is Ni/Pt/Au, and the total thickness is 5000-8000A;
r, sequentially completing a secondary medium process, a field plate process, a first layer metal wiring process, a third medium process and a second layer metal wiring process, reversely bonding, and then transferring to a back surface process, wherein the bonding between the wafer and the sapphire carrier is realized by special materials such as paraffin, and the materials can resist high temperature above 200 ℃ and acid-base corrosion and provide protection for front devices;
S, thinning the wafer to 75-100 mu m, wherein the thinning is carried out in two sections: the first section is used for polishing and thinning the substrate until the through hole metal is slightly exposed, and the second section is used for introducing etching liquid corresponding to the through hole metal into the polishing liquid while continuing to thin the substrate until the thickness of the substrate is thinned to the target thickness, and meanwhile, the through hole metal and the substrate are almost in the same horizontal plane, so that the subsequent process is convenient to develop;
sputtering a seed layer, electroplating Au, and forming a film with the thickness of 5-8 mu m;
Manufacturing a scribing channel, manufacturing back metal according to design requirements, interconnecting the back metal and the through hole metal, and corroding to form the scribing channel for subsequent cutting and scribing;
V, jie Jian, after the back surface process is finished, the wafer is de-bonded, and then film transfer, cutting and piece picking are carried out.
The above is an embodiment exemplified in this example, but this example is not limited to the above-described alternative embodiments, and a person skilled in the art may obtain various other embodiments by any combination of the above-described embodiments, and any person may obtain various other embodiments in the light of this example. The above detailed description should not be construed as limiting the scope of the present embodiments, which is defined in the claims and the description may be used to interpret the claims.
Claims (6)
1. A method for manufacturing a through-hole gallium nitride transistor with high electron mobility is characterized in that: the method comprises the following steps:
Providing a wafer with a substrate layer, an AlGaN/GaN layer and an in-situ SiN layer structure from bottom to top, and sputtering seed layer metal on the surface of the wafer;
Manufacturing an etching barrier layer on the front surface of the wafer, patterning, sequentially etching the in-situ SiN layer, the AlGaN/GaN layer and the substrate layer from top to bottom to obtain deep holes, removing residues, and sputtering seed layer metal again;
Then electroplating metal to fill deep holes, performing exposure and development after metal polishing, obtaining patterned metal through corrosion, uniformly coating negative photoresist, and obtaining source-drain patterns after exposure and development;
Etching the in-situ SiN layer, evaporating source and drain metal after cleaning, and rapidly annealing by an annealing furnace after stripping to form ohmic contact;
Growing a layer of medium for protecting the surface of the transistor, isolating the device, and forming a hole in the medium to expose the source-drain metal pattern;
then firstly adopting positive photoresist to expose and develop, then etching a medium to define gate feet, then adopting negative photoresist to expose and develop, evaporating gate metal, and stripping to form gate metal;
and after the preparation of the gate metal is finished, continuing the residual front-side process and then transferring to the back-side process.
2. A method of fabricating a through-hole gan high electron mobility transistor according to claim 1, wherein: the etching of the substrate layer is 80-110 mu m.
3. A method of fabricating a through-hole gan high electron mobility transistor according to claim 1, wherein: the seed layer metal is TiW/Au, wherein the thickness of TiW is 200-500A, and the thickness of Au is 1000-2000A.
4. A method of fabricating a through-hole gan high electron mobility transistor according to claim 1, wherein: the etching barrier layer is patterned metal Ni, and the thickness is 5-10 mu m.
5. A method of fabricating a through-hole gan high electron mobility transistor according to claim 1, wherein: the thinning process of the back wafer comprises two sections: the first section is to expose the substrate to the through hole metal through polishing, and the second section is to introduce etching liquid corresponding to the through hole metal into the polishing liquid while continuing to thin the substrate until the thickness of the substrate is thinned to the target thickness.
6. A through-hole gallium nitride high electron mobility transistor, characterized by: a method of fabricating a through-hole gan high electron mobility transistor according to any of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410389720.5A CN117976621B (en) | 2024-04-02 | 2024-04-02 | Through-hole gallium nitride high electron mobility transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410389720.5A CN117976621B (en) | 2024-04-02 | 2024-04-02 | Through-hole gallium nitride high electron mobility transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117976621A CN117976621A (en) | 2024-05-03 |
| CN117976621B true CN117976621B (en) | 2024-05-31 |
Family
ID=90851908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410389720.5A Active CN117976621B (en) | 2024-04-02 | 2024-04-02 | Through-hole gallium nitride high electron mobility transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117976621B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001308108A (en) * | 2000-04-19 | 2001-11-02 | Oki Electric Ind Co Ltd | Field effect transistor and its manufacturing method |
| JP2011124246A (en) * | 2009-12-08 | 2011-06-23 | Mitsubishi Electric Corp | Heterojunction field effect transistor and method of manufacturing the same |
| CN107591452A (en) * | 2017-10-10 | 2018-01-16 | 无锡新洁能股份有限公司 | A kind of wafer scale power semiconductor and preparation method thereof |
| CN112349660A (en) * | 2020-10-23 | 2021-02-09 | 中国电子科技集团公司第二十九研究所 | Silicon-based micro-channel radiator with embedded heating structure, application method and preparation method |
| CN113394282A (en) * | 2021-06-01 | 2021-09-14 | 上海新微半导体有限公司 | Preparation method of GaN-based HEMT device based on pre-through hole etching |
| CN115910782A (en) * | 2022-12-29 | 2023-04-04 | 北京大学东莞光电研究院 | Method for manufacturing normally-off high electron mobility transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220102344A1 (en) * | 2020-09-25 | 2022-03-31 | Intel Corporation | Gallium nitride (gan) three-dimensional integrated circuit technology |
-
2024
- 2024-04-02 CN CN202410389720.5A patent/CN117976621B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001308108A (en) * | 2000-04-19 | 2001-11-02 | Oki Electric Ind Co Ltd | Field effect transistor and its manufacturing method |
| JP2011124246A (en) * | 2009-12-08 | 2011-06-23 | Mitsubishi Electric Corp | Heterojunction field effect transistor and method of manufacturing the same |
| CN107591452A (en) * | 2017-10-10 | 2018-01-16 | 无锡新洁能股份有限公司 | A kind of wafer scale power semiconductor and preparation method thereof |
| CN112349660A (en) * | 2020-10-23 | 2021-02-09 | 中国电子科技集团公司第二十九研究所 | Silicon-based micro-channel radiator with embedded heating structure, application method and preparation method |
| CN113394282A (en) * | 2021-06-01 | 2021-09-14 | 上海新微半导体有限公司 | Preparation method of GaN-based HEMT device based on pre-through hole etching |
| CN115910782A (en) * | 2022-12-29 | 2023-04-04 | 北京大学东莞光电研究院 | Method for manufacturing normally-off high electron mobility transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117976621A (en) | 2024-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7146784B2 (en) | Nitride structures with gold-free contacts and methods of forming such structures | |
| JP5970736B2 (en) | Manufacturing method of semiconductor device | |
| US9136396B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN103137476A (en) | GaN high voltage HFET with passivation plus gate dielectric multilayer structure | |
| US10096550B2 (en) | Nitride structure having gold-free contact and methods for forming such structures | |
| US10566428B2 (en) | Method for forming gate structures for group III-V field effect transistors | |
| US9165839B2 (en) | Plasma protection diode for a HEMT device | |
| CN111710651B (en) | Integrated GaN device and preparation method thereof | |
| CN110690284A (en) | Gallium nitride-based field effect transistor and preparation method thereof | |
| CN109920757B (en) | Back section process for improving reliability of compound semiconductor device | |
| JP2005276978A (en) | Ohmic electrode structure, manufacturing method thereof, semiconductor manufacturing device, and semiconductor device | |
| CN115312389A (en) | Method for manufacturing semiconductor device having vertical structure and semiconductor device | |
| US20050250336A1 (en) | Semiconductor device and method for fabricating the same | |
| CN117976621B (en) | Through-hole gallium nitride high electron mobility transistor and manufacturing method thereof | |
| US20050258459A1 (en) | Method for fabricating semiconductor devices having a substrate which includes group III-nitride material | |
| CN105810607A (en) | Method and system for realizing P-type nitride enhanced HEMT (High Electron Mobility Transistor) through in-situ etching monitoring | |
| JPH01268072A (en) | Manufacture of junction type field effect transistor | |
| CN109585326B (en) | Compound testing method for vertical leakage current and Hall effect of gallium nitride epitaxial wafer | |
| CN106549049B (en) | A kind of method that electrochemical etching p-type nitride realizes enhanced HEMT | |
| CN115498034B (en) | GaN HEMT device and preparation method thereof | |
| JP2006286951A (en) | Method of manufacturing semiconductor device | |
| CN116093147A (en) | Preparation method of GaN HEMT low-temperature gold-free ohmic contact | |
| WO2021243482A1 (en) | Gallium nitride-based chip, chip manufacturing method, gallium nitride power device, and circuit | |
| CN108766888A (en) | A kind of Y gate semiconductor devices manufacturing method and semiconductor devices | |
| CN109755308B (en) | Semiconductor structure and method for manufacturing high electron mobility transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |