JP2001308108A - Field effect transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide structure that maintains the sufficient strength of a substrate in a filed effect transistor having a via hole. SOLUTION: The via hole is formed, where the via hole passes through the insulation region of a semiconductor layer and a buffer layer from the surface side of the semiconductor layer having an active region and the insulation one to a semiconductor substrate. A conductive layer is formed, where the conductive layer connects the semiconductor substrate to an electrode on the semiconductor layer via the via hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a field effect transistor, and more particularly to a field effect transistor having via holes and a method of manufacturing the same.

[0002]

2. Description of the Related Art Via-hole structures are widely used in field-effect transistors used for high-frequency and high-power applications in order to reduce source inductance. This type of field effect transistor is disclosed in, for example, the document “GaAs
Fundamentals of field effect transistors, 213 pages, 1992 (1
992), published by the Institute of Electronics, Information and Communication Engineers.

FIG. 6 is a sectional view of a conventional field effect transistor having a via hole structure. In FIG.
A source electrode 2, a gate electrode 3, and a drain electrode 4 are formed on a surface of a GaAs substrate 1 having a source / drain region (not shown). A ground electrode is formed on the back surface of the substrate 1. Further, a hole (via hole portion 6) penetrating from the back side to the front side of the substrate 1 is formed,
The ground electrode 5 is in contact with the source electrode via the via hole 6.

In the field effect transistor having this structure, the distance between the source electrode 2 and the ground electrode (earth) 5 can be shortened by grounding the source via the via hole 6 formed so as to penetrate the substrate. Therefore, the source inductance can be reduced.

[0005]

However, in the above-described via hole structure, a substrate having a thickness of about 600 μm is usually polished from the rear surface side to form a hole penetrating from the front surface to the rear surface of the substrate. Dozens of μ
It is necessary to reduce the thickness to about m. Thinned substrates have low mechanical strength, which leads to reduced yield due to wafer cracking.
Since handling becomes difficult, careful manual work is required, which leads to an increase in work time.

[0006]

According to the present invention, a semiconductor substrate having one conductivity type, a buffer layer formed on the semiconductor substrate, and an active region and an insulating region formed on the buffer layer are provided. A plurality of electrodes formed on the active region of the semiconductor layer; a via hole extending from the surface side of the semiconductor layer through the insulating region and the buffer layer to the semiconductor substrate; -A field effect transistor having a conductive layer that electrically connects the semiconductor substrate and any of the plurality of electrodes via holes is obtained.

Further, according to the present invention, a step of forming a buffer layer on a semiconductor substrate of one conductivity type, a step of forming a semiconductor layer having an active region and an insulating region on the buffer layer, Forming a plurality of electrodes on the active region of the layer; forming via holes from the surface side of the semiconductor layer through the insulating region and the buffer layer to the semiconductor substrate; Forming a conductive layer that electrically connects the semiconductor substrate and any one of the plurality of electrodes via a hole.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the sizes, shapes, and arrangements of the various components are only schematically shown to the extent that the present invention can be understood, and therefore, the present invention is not limited to the illustrated examples.

First Embodiment A method for manufacturing a field effect transistor according to a first embodiment of the present invention will be described with reference to FIG.

[0010] First, as shown in FIG.
0 μm n-type (Si-doped, 110 ¹⁹cm^-3) GaAs
An undoped GaAs buffer having a thickness of 1 μm on a substrate 1
Layer 2, GaAs / AlGaAs / InGaAs layer
HEMT (High Electron M
obiliity Transistor) Structure Thin Film 3
To MBE (Molecular Beam Ep)
It grows by the (itaxy) method. HEMT structure part film
The thickness is generally less than 200 nm. continue,
As shown in FIG. 1B, the gate electrode 6 and the source electrode 5
And a transistor portion having a drain electrode 7
Form passive elements such as wires and capacitors (insulating film 4)
I do. Insulated to cover these electrodes, wiring and passive elements
The film 4 is formed.

As shown in FIG. 1 (c), a photoresist 8 is formed on the insulating film 4, and the photoresist 8 on a region where a via hole 9 is to be formed is removed by photolithography to form a resist pattern. Next, by dry etching using CCl ₄ , the n-type G
Via holes 9 are formed to reach the aAs substrate 1.

Subsequently, as shown in FIG.
e / Ni / Au laminated film is deposited and lifted off,
An ohmic electrode 10 for n-type GaAs is formed at the bottom of the hole 9 (exposed portion of the n-type GaAs substrate 1).

As shown in FIG. 1E, after a contact hole 11 is formed in the insulating film 4 on the source electrode 5, a laminated film 12 of Ti / Au (thickness: 100 nm / 200 nm) is formed on the entire surface. . Subsequently, after forming a resist pattern (not shown) by photolithography, an Au plating layer 14 is formed to a thickness of 1 μm by electrolytic plating.
After removing the resist pattern, unnecessary portions of Ti / Au
The laminated film 12 is removed by an ion milling method. Thus, conduction between the source electrode 5 and the via hole 9 is obtained.

Finally, a laminated film of Ti / Au (thickness: 100 nm / 200 nm) is formed on the back surface of the substrate 1 to form a ground electrode 13. In the first embodiment, n-type Ga
The As substrate 1 will be used as a part of the ground electrode 13.

Although the description has been given by taking the HEMT as an example of the basic element, a MESFET (Metal Semiconductor) is used.
to Field Effect Transist
or HBT (Hetero Bipolar Tr)
It can be applied to any device such as an anistor.

Also, undoped GaAs having a thickness of 1 μm has been described as an example of the buffer layer, but GaAs / AlGaAs is used.
A similar via hole structure can be formed for any buffer structure such as an s laminated film. In addition, as a method of etching a via hole, CCl ₄
Has been described as an example dry etching using but, BCl ₃
A similar process can be performed by dry etching using another gas or wet etching.

Also, as an example of a metal connecting source electrode 5 and via hole 9, a 1 μm thick Au plating layer formed by electrolytic plating on a Ti / Au laminated film has been described. The thickness, film thickness and forming method are not limited to these.

As a substrate to be used, a Si-doped n-type (11
0 ¹⁹ cm ⁻³ ) GaAs has been described as an example. The doping amount of the substrate is preferably high in order to reduce the influence of resistance, and is not limited to this concentration and dopant.

As described above, in the field effect transistor according to the first embodiment, the n-type GaAs substrate 1 itself can be used as a part of the ground electrode 13 on the back surface. Thus, the via hole 9 only needs to penetrate the HEMT structure portion and the buffer layer portion, so that the etching depth can be reduced and the substrate need not be thinned. Therefore, wafer cracking can be prevented by maintaining the mechanical strength of the substrate, and an improvement in yield can be expected.
Further, since the handling becomes easy, it is expected that the working time can be shortened.

[Second Embodiment] A field effect transistor according to a second embodiment of the present invention will be described with reference to FIG.

In FIG. 2, this field effect transistor is different from the first embodiment in that p-type GaAs 21 is used. The other points are the same as those of the first embodiment, and the same components are denoted by the same reference numerals.

In FIG. 2, a p-type (Z
n-doped, 110 ¹⁹ cm ^-3 ) undoped GaAs buffer layer 2, GaAs / AlGaAs on GaAs substrate 21
HEMT structured thin film 3 composed of s / InGaAs
Are sequentially grown by the MBE method. As in the first embodiment, after forming a transistor portion having a gate electrode 6, a source electrode 5 and a drain electrode 7, and other passive element portions such as wirings and capacitors, the p-type G
Via holes 9 are formed to reach the aAs substrate. Subsequently, the AuZn / Au multilayer film is deposited and lifted off, and an ohmic electrode 10 for the p-type GaAs substrate is formed at the bottom of the via hole 9.

Hereinafter, as in the first embodiment, Au for obtaining conduction between the source electrode 5 and the via hole 9 is used.
The / Ti wiring 12 and the Au plating layer 14 are formed, and a Ti / Au laminated film is formed on the back surface of the substrate 21 to form the ground electrode 13. In the second embodiment, the p-type GaAs substrate 21 is used as a part of the ground electrode 13.

FIG. 3 shows a band diagram between the field effect transistor portion and the substrate in the case of the first embodiment and in the case of the second embodiment. In the first embodiment, since the n-type GaAs substrate is used, the potential of the undoped GaAs buffer layer is raised, and the band has a curved profile. The degree to which the band bends depends on the purity of the undoped GaAs buffer layer. The more the band is bent, the shallower the threshold voltage of the field effect transistor and the lower the drain current. On the other hand, when the band curvature is small, the threshold voltage of the field effect transistor is deep and the drain current is large. The purity of the undoped GaAs buffer layer is MB
It largely depends on the state of the device at the time of E growth. In the second embodiment, the potential in the undoped GaAs buffer layer monotonically increases toward the p-type GaAs substrate side, and is not easily affected by the purity in the buffer layer because no curved point is generated. It will be.

In the present embodiment, an example was described in which Zn-doped p-type (110 ¹⁹ cm ^-3 ) GaAs was used as a substrate.
The doping amount of the substrate is preferably high in order to reduce the influence of resistance, and is not limited to this concentration and dopant.

As described above, in the second embodiment, the p-type GaAs substrate 21 itself can be used as a part of the ground electrode 13 on the back surface. Since the p-type substrate has a higher resistivity at the same concentration than the n-type substrate, according to the second embodiment, the potential between the field-effect transistor portion and the substrate is higher than that of the first embodiment. The distribution is stable, and the uniformity and controllability of the field effect transistor characteristics can be improved.

Third Embodiment A GaAs field effect transistor according to a third embodiment will be described with reference to FIG.

Referring to FIG. 4, this field-effect transistor differs from the first embodiment in that an n-type AlGaAs etching stopper layer 22 is formed between an n-type GaAs 1 and an undoped GaAs buffer layer 3. The other points are the same as those of the first embodiment, and the same components are denoted by the same reference numerals.

In FIG. 4, a 600 μm thick n-type (S
i-doped, 110 ¹⁹ cm ⁻³ ) n-type AlGaAs (Si-doped, 110 ¹⁹ cm ⁻³ ) having a thickness of 1 μm on a GaAs substrate 1.
^-3 ) Etching stopper layer 22, 1 μm thick undoped GaAs buffer layer 2, GaAs / AlGaAs / I
HEMT structured thin film 3 composed of nGaAs layer,
It grows sequentially by the MBE method.

In the third embodiment, via holes 9
Partial etching is performed by selective etching. In the selective etching, AlGaAs is not etched and GaAs is etched.
The etching is performed under such a condition that only s is etched, and can be performed by dry etching using BCl ₃ or wet etching using citric acid / hydrogen peroxide solution.

As described above, since the n-type GaAs substrate 1 is provided with the n-type AlGaAs etching stopper layer 22, the selective etching is used to accurately etch the via holes 9 in the n-type AlGaAs. It can be stopped at the stopper layer. The AlGaAs layer used as the etching stopper layer is doped with n-type, thereby forming a ground electrode 1 integrated with the n-type GaAs substrate 1.
3 can be used.

As described above, in the third embodiment, the etching depth of the via hole can be accurately controlled. In the case of the first and second embodiments, it is necessary to perform over-etching at the time of etching in order to ensure that via holes reach the n-type or p-type substrate. Get deeper. Bahia
In order to form wiring metal inside the hole, the via
The hole is formed as shallow as possible.

In the third embodiment, since the depth of the via hole can be accurately controlled, the diameter of the via hole can be reduced as compared with the first and second embodiments. .

Fourth Embodiment A field effect transistor according to a fourth embodiment will be described with reference to FIG.

In the fourth embodiment, a 600 μm thick n-type
(Si-doped, 110¹⁹cm^-3) On the GaAs substrate 1
1 μm thick p-type GaAs layer 2 (Be-doped, 110^{1 9}
cm ^-3), 1 μm thick n-type AlGaAs layer 3 (Si
Soup, 110^{1 9}cm^-3), 1 μm thick undoped Ga
As buffer layer, GaAs / AlGaAs / InGaAs
The HEMT structure thin film 5 composed of
It grows by E method.

As in the first embodiment, the gate electrode 5
8. After forming a transistor portion having a source electrode 57 and a drain electrode, and a passive element portion such as a wiring and a capacitor, a via hole portion 59 of the source electrode 57 is formed. The via hole of the source electrode 57 is formed by using non-selective etching so as to reach the n-type GaAs substrate 51.

In the via hole 59, AuGe / Ni /
After depositing and lifting off the Au laminated film to form an ohmic electrode 63 for the n-type GaAs substrate 51, a contact hole 61 is formed in the insulating film 56 on the source electrode 57. Hereinafter, similarly to the first embodiment, Ti for obtaining conduction between the source electrode 57 and the via hole 59 is used.
/ Au laminated metal wiring 64 and Au plating layer 66 are formed.

Further, in the fourth embodiment, via holes 60 for obtaining conduction between the gate electrode 58 and the n-type AlGaAs layer 53 are formed. This via hole 60
The n-type AlGaAs layer 5 is formed by using selective etching.
It is formed so as to stop at 3. The AuGe / Ni / Au laminated film is deposited and lifted off in the via hole 60, and n
An ohmic electrode 63 for the type AlGaAs is formed.

Subsequently, after a contact hole 62 is formed in the insulating film 56 on the gate electrode 58, Ti / Au for obtaining conduction between the gate electrode 58 and the via hole 60 is used.
The laminated metal wiring 64 and the Au plating layer 66 are formed.

Finally, the back surface of the n-type GaAs substrate 51 is
A laminated film of i / Au is formed to be a ground electrode 65. In the third embodiment, the n-type GaAs substrate 51 is used as a part of the ground electrode 65. Further, a structure in which a reverse pn junction diode is introduced between the gate electrode 58 and the ground electrode 65 can be realized.

In a device using a field-effect transistor, a surge may enter the gate electrode and the transistor may be destroyed. In order to prevent this, a method of introducing a diode between the gate electrode and the ground is often used. In this case, since the surge escapes to the ground through the diode, the transistor portion can be protected from electrostatic breakdown. However, since it is necessary to arrange a diode at the same time as a transistor on the substrate surface, there is a problem that the chip area cannot be reduced. In the fourth embodiment, a reverse pn junction diode is formed between a gate electrode and a ground electrode using a via hole structure, so that it is not necessary to form a diode on the substrate surface, and the chip area is reduced. be able to.

[0042]

As described above, according to the present invention,
From the surface side of the semiconductor layer having an active region and an insulating region,
Via holes are formed through the insulating region of the semiconductor layer and the buffer layer to reach the semiconductor substrate. Then, a conductive layer for connecting the semiconductor substrate and the electrode on the semiconductor layer through the via hole is formed.

According to the present invention, it is not necessary to reduce the thickness of the substrate by polishing it from the back surface side, so that the strength of the substrate can be maintained. Therefore, cracking of the semiconductor substrate can be prevented, and the yield can be improved. Further, the handling becomes easy, so that the working time in the manufacturing process can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a step of manufacturing a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a field-effect transistor according to a second embodiment of the present invention.

FIG. 3 is a graph showing a band diagram of a field effect transistor according to the first and second embodiments of the present invention.

FIG. 4 is a sectional view showing a field-effect transistor according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing a field-effect transistor according to a fourth embodiment of the present invention.

FIG. 6 is a cross-sectional view of a conventional field-effect transistor having a via-hole structure.

[Explanation of symbols]

 Reference Signs List 1 n-type GaAs substrate 2 undoped GaAs buffer layer 3 HEMT structured thin film 4 insulating film 5 source electrode 6 gate electrode 7 drain electrode 8 photoresist 9 via hole 10 ohmic electrode 11 contact hole 12 Ti / Au wiring 13 ground electrode 14 Au plating layer 21 p-type GaAs substrate 22 n-type AlGaAs etching stopper layer

Claims (8)

[Claims] A semiconductor layer of one conductivity type; a buffer layer formed on the semiconductor substrate; a semiconductor layer formed on the buffer layer, having an active region and an insulating region; A plurality of electrodes formed on the region,
A via hole extending from the front surface side of the semiconductor layer to the semiconductor substrate through the insulating region and the buffer layer; and electrically connecting the semiconductor substrate and any of the plurality of electrodes via the via hole. A field-effect transistor having a conductive layer to be connected. 2. The field effect transistor according to claim 1, wherein said buffer layer is an undoped semiconductor layer. 3. The field effect transistor according to claim 1, wherein said one conductivity type is n-type. 4. The field effect transistor according to claim 1, wherein said one conductivity type is p-type. 5. A step of forming a buffer layer on a semiconductor substrate of one conductivity type; a step of forming a semiconductor layer having an active region and an insulating region on the buffer layer; Forming a plurality of electrodes; forming a via hole from the surface of the semiconductor layer to the semiconductor substrate through the insulating region and the buffer layer; and forming the via hole through the via hole. Forming a conductive layer for electrically connecting a semiconductor substrate to any one of the plurality of electrodes. 6. The method for manufacturing a field-effect transistor according to claim 5, wherein said buffer layer is an undoped semiconductor layer. 7. The method for manufacturing a field-effect transistor according to claim 5, wherein said one conductivity type is n-type. 8. The method for manufacturing a field-effect transistor according to claim 5, wherein said one conductivity type is a p-type.