CN112185959B - CMOS inverter monolithically integrated with GaN HEMT power electronic device and preparation method - Google Patents

CMOS inverter monolithically integrated with GaN HEMT power electronic device and preparation method Download PDF

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CN112185959B
CN112185959B CN202010887541.6A CN202010887541A CN112185959B CN 112185959 B CN112185959 B CN 112185959B CN 202010887541 A CN202010887541 A CN 202010887541A CN 112185959 B CN112185959 B CN 112185959B
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nmos
pmos
electrode
drain electrode
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CN112185959A (en
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刘志宏
王泽宇
张进成
朱肖肖
宋昆璐
赵胜雷
周弘
张苇杭
段小玲
郝跃
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Xidian University
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Abstract

The invention relates to a CMOS inverter monolithically integrated with a GaN HEMT power electronic device and a preparation method thereof, wherein the CMOS inverter comprises: the substrate, the composite buffer layer, the channel layer, the composite barrier layer, the P-InGaN layer, the PMOS source electrode, the PMOS drain electrode, the PMOS insulating dielectric layer 54, the PMOS gate electrode, the NMOS source electrode, the NMOS drain electrode, the NMOS insulating dielectric layer, the NMOS gate electrode and the interconnection metal. The CMOS inverter is used for preparing the P-InGaN layer on the composite barrier layer, so that holes can be generated, two-dimensional electron gas between the composite barrier layer and the channel layer is exhausted, and two-dimensional hole gas is formed at the interface of the CMOS inverter and the composite barrier layer, thereby forming a conductive channel of the PMOS device and improving the output current of the PMOS device.

Description

CMOS inverter monolithically integrated with GaN HEMT power electronic device and preparation method
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a CMOS inverter monolithically integrated with a GaN HEMT power electronic device and a preparation method thereof.
Background
Group III nitride-based High Electron Mobility Transistors (HEMTs) are widely used in electrical devices due to their good material properties and excellent quality factor. The GaN system material, namely the III nitride material, has a series of excellent physical characteristics including large forbidden bandwidth, high critical breakdown electric field, high mobility and high electron saturation speed, and the polarization coefficient of the III nitride material is relatively high, so that the two-dimensional electron gas concentration of the III nitride heterojunction interface is very high, and the excellent material characteristics enable a GaN High Electron Mobility Transistor (HEMT) to have excellent performances such as high breakdown voltage, low on-resistance, low gate charge, high switching speed, high energy conversion efficiency and the like, and become a core device applied to fields such as electric automobiles, power grids, high-speed rails, consumer electronic power modules and the like.
The normally-off GaN HEMT device structure is typically realized by inserting a layer of p-type nitride material under the gate, which may be p-GaN, p-InGaN, or p-AlGaN. On the other hand, the trend toward miniaturization of power electronics systems has created an urgent need for GaN power electronics that monolithically integrate CMOS drive circuitry. However, the conventional method requires a separate Si CMOS driving circuit module, which increases the system volume and complexity of system design, and thus has a great significance in GaN CMOS driving circuits monolithically integrated with GaN HEMT power electronics. PMOS is reported in the literature by using a p-GaN gate material of a normally-off GaN HEMT, but p-type impurity concentration ionization energy of p-GaN is higher, hole concentration is lower, hole mobility is also lower, resulting in lower PMOS output current of p-GaN.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a CMOS inverter monolithically integrated with a GaN HEMT power electronic device and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
the embodiment of the invention provides a CMOS inverter monolithically integrated with a GaN HEMT power electronic device, comprising:
a substrate;
a composite buffer layer located on the substrate;
a channel layer on the composite buffer layer;
a composite barrier layer on the channel layer;
a P-InGaN layer positioned on the composite barrier layer;
the PMOS source electrode is positioned on the P-InGaN layer;
a PMOS drain electrode located on the P-InGaN layer;
a PMOS insulating medium layer, one end of which covers a part of the PMOS source electrode, the other end of which covers a part of the PMOS drain electrode, and forming a groove structure with the bottom embedded in the P-InGaN layer;
the PMOS gate electrode is positioned on the PMOS insulating medium layer;
an NMOS source electrode embedded in the P-InGaN layer and located on the composite barrier layer;
an NMOS drain electrode embedded in the P-InGaN layer and located on the composite barrier layer;
an NMOS insulating dielectric layer which is positioned on the P-InGaN layer between the NMOS source electrode and the NMOS drain electrode and covers part of the NMOS source electrode and part of the NMOS drain electrode;
an NMOS gate electrode positioned on the NMOS insulating dielectric layer;
and an interconnection metal, one end of which covers a part of the PMOS drain electrode and the other end of which covers a part of the NMOS source electrode, and forming an isolation groove embedded in the P-InGaN layer, the composite barrier layer and the channel layer.
In one embodiment of the present invention, the composite buffer layer includes a nucleation layer, a transition layer, a core buffer layer, and a back barrier layer, wherein,
the nucleation layer is located on the substrate, the transition layer is located on the nucleation layer, the core buffer layer is located on the transition layer, and the back barrier layer is located on the core buffer layer.
In one embodiment of the invention, the composite barrier layer includes an isolation layer, a core barrier layer, and a cap layer, wherein the isolation layer is located on the channel layer, the core barrier layer is located on the isolation layer, and the cap layer is located on the core barrier layer.
In one embodiment of the invention, the material of the P-InGaN layer comprises an Mg-doped InGaN layer, wherein the doping concentration of Mg is 10 17 -10 20 cm -3 The thickness of the P-InGaN layer is 5-150nm.
In one embodiment of the present invention, the materials of the PMOS source electrode, the PMOS drain electrode, the NMOS source electrode, and the NMOS drain electrode include one or more of titanium, aluminum, nickel, gold, and tantalum, and the thicknesses are 10-500nm.
In one embodiment of the present invention, the PMOS gate electrode includes a gate header and a gate leg, wherein the gate leg is located in a recessed structure of the PMOS insulating dielectric layer, the gate header is located on the PMOS insulating dielectric layer and on the gate leg,
the width of the grid head is larger than the distance between the PMOS source electrode and the PMOS drain electrode;
the height of the PMOS gate electrode is 50-800nm.
In one embodiment of the present invention, the width of the NMOS gate electrode is greater than the spacing between the NMOS source electrode and the NMOS drain electrode;
the height of the NMOS gate electrode is 50-800nm.
In one embodiment of the invention, further comprises P + An InGaN layer, said P + An InGaN layer is located on the P-InGaN layer.
In one embodiment of the invention, the P + The material of the InGaN layer comprises an Mg-doped InGaN layer, wherein the Mg doping concentration is 10 17 -10 20 cm -3 The P is + The thickness of the InGaN layer is 1-20nm.
Another embodiment of the present invention provides a method for manufacturing a CMOS inverter monolithically integrated with a GaN HEMT power electronic device, comprising the steps of:
s1, sequentially epitaxially growing a composite buffer layer, a channel layer and a composite barrier layer on a substrate;
s2, epitaxially growing a P-InGaN layer on the composite barrier layer;
s3, etching the P-InGaN layer, the composite barrier layer and part of the channel layer to form an interconnection metal groove;
s4, etching the P-InGaN layer on one side of the interconnection metal groove to form an NMOS source electrode groove and an NMOS drain electrode groove;
s5, depositing electrode metal in the NMOS source electrode groove and the NMOS drain electrode groove to form an NMOS source electrode and an NMOS drain electrode;
s6, electrode metal is deposited on the P-InGaN layer at the other side of the interconnection metal groove, and a PMOS source electrode and a PMOS drain electrode are formed;
s7, etching a part of the P-InGaN layer to form a PMOS gate electrode groove;
s8, growing insulating dielectric materials on the P-InGaN layer between the NMOS source electrode and the NMOS drain electrode, part of the NMOS source electrode, part of the NMOS drain electrode, part of the PMOS gate electrode groove and part of the PMOS source electrode and part of the PMOS drain electrode to form a PMOS insulating dielectric layer and an NMOS insulating dielectric layer; one end of the PMOS insulating medium layer covers a part of the PMOS source electrode, the other end covers a part of the PMOS drain electrode, and a groove structure with the bottom embedded in the P-InGaN layer is formed; the NMOS insulating dielectric layer is positioned on the P-InGaN layer between the NMOS source electrode and the NMOS drain electrode and covers part of the NMOS source electrode and part of the NMOS drain electrode;
s9, growing gate electrode metal on the PMOS insulating medium layer and the NMOS insulating medium layer to form a PMOS gate electrode and an NMOS gate electrode, wherein the width of the PMOS gate electrode is larger than the distance between the PMOS source electrode and the PMOS drain electrode, and the width of the NMOS gate electrode is larger than the distance between the NMOS source electrode and the NMOS drain electrode;
and S10, growing interconnection metal in the interconnection metal groove.
Compared with the prior art, the invention has the beneficial effects that:
1. the CMOS inverter of the invention prepares the P-InGaN layer on the composite barrier layer, can generate holes, deplete the two-dimensional electron gas between the composite barrier layer and the channel layer, and form two-dimensional hole gas at the interface of the composite barrier layer to form a conductive channel of the PMOS, thereby improving the output current of the PMOS device.
2. In the CMOS inverter, the NMOS source electrode and the NMOS drain electrode are respectively formed in the grooves of the P-InGaN layer, then the NMOS gate electrode is formed between the NMOS source electrode and the NMOS drain electrode, the PMOS source electrode and the PMOS drain electrode are formed on the P-InGaN layer, and then the PMOS gate electrode is formed in the groove structure between the PMOS source electrode and the PMOS drain electrode, so that the spacing between the gate electrode and the source electrode and the spacing between the gate electrode and the drain electrode in the NMOS device and the PMOS device are reduced to the greatest extent, the on-resistance of the device is reduced, and the frequency performance of the device is improved; meanwhile, larger distances are kept between the surface of the gate electrode metal and the gate head metal of the gate electrode and between the surface of the drain electrode metal and the gate head metal of the gate electrode in the NMOS device and the PMOS device in the vertical direction, the parasitic capacitance of the device is reduced, and the negative influence of the parasitic capacitance of the gate source and the gate drain on the working frequency of the device is restrained.
Drawings
Fig. 1 is a schematic structural diagram of a CMOS inverter monolithically integrated with a GaN HEMT power electronic device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another CMOS inverter monolithically integrated with a GaN HEMT power electronic device according to an embodiment of the present invention;
fig. 3 a-3 j are schematic process diagrams of a method for fabricating a CMOS inverter monolithically integrated with a GaN HEMT power electronic device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of a CMOS inverter monolithically integrated with a GaN HEMT power electronic device according to an embodiment of the present invention.
The CMOS inverter includes: substrate 1, composite buffer layer 2, channel layer 3, composite barrier layer 4, P-InGaN layer 5, PMOS source electrode 51, PMOS drain electrode 52, PMOS insulating dielectric layer 54, PMOS gate electrode 53, NMOS source electrode 71, NMOS drain electrode 72, NMOS insulating dielectric layer 74, NMOS gate electrode 73, and interconnect metal 6.
Specifically, the composite buffer layer 2 is located on the substrate 1; the channel layer 3 is positioned on the composite buffer layer 2; a composite barrier layer 4 is located on the channel layer 3; a P-InGaN layer 5 is located on the composite barrier layer 4. Wherein, the composite buffer layer 2, the channel layer 3 and the composite barrier layer 4 are all III-nitride epitaxial layers.
In a specific embodiment, the material of the substrate 1 comprises one or more of high-resistance silicon, semi-insulating silicon carbide, semi-insulating sapphire, semi-insulating diamond, semi-insulating aluminum nitride; the thickness of the substrate 1 is 50-1500 μm. When the material of the substrate 1 is high-resistance silicon, the resistivity is 1000-30000 omega cm, and the crystal orientation is <111>.
In a specific embodiment, the composite buffer layer 2 comprises a nucleation layer 21, a transition layer 22 and a core buffer layer 23, wherein the nucleation layer 21 is located on the substrate 1, the transition layer 22 is located on the nucleation layer 21, and the core buffer layer 23 is located on the transition layer 22. Specifically, the material of the nucleation layer 21 may be AlN, and the thickness of the nucleation layer 21 is 50-300nm; the material of the transition layer 22 can be a plurality of layers of AlGaN with different components, and also can be an AlGaN/GaN superlattice layer, and the thickness of the transition layer 22 is 0.5-1.5 mu m; the material of the core buffer layer 23 includes one or more of gallium nitride GaN, aluminum gallium nitride AlGaN, and aluminum nitride AlN, and the thickness of the core buffer layer 23 is 0.5-2 μm.
In one particular embodiment, the composite buffer layer 2 includes a nucleation layer 21, a transition layer 22, a core buffer layer 23, and a back barrier layer 24, wherein the nucleation layer 21 is located on the substrate 1, the transition layer 22 is located on the nucleation layer 21, the core buffer layer 23 is located on the transition layer 22, and the back barrier layer 24 is located on the core buffer layer 23. Specifically, the materials and thicknesses of the nucleation layer 21, the transition layer 22, and the core buffer layer 23 are described above; the material of the back barrier layer 24 comprises one or more of AlGaN, inGaN, and AlN, and the thickness of the back barrier layer 24 is 2-100nm.
In a specific embodiment, the material of the channel layer 3 includes one or more of unintentionally doped gallium nitride GaN, indium gallium nitride InGaN, aluminum nitride AlN, aluminum gallium nitride AlGaN, and the thickness of the channel layer 3 is 10-500nm.
In a specific embodiment, the composite barrier layer 4 includes a core barrier layer 42, where the core barrier layer 42 is located on the channel layer 3, and the material includes one or more of aluminum gallium nitride AlGaN, indium aluminum nitride InAlN, and aluminum nitride AlN; when the core barrier layer 42 is made of AlGaN, the content of Al is 0.2-0.4, and the thickness is 10-20nm; when the material of the core barrier layer 42 is InAlN, the content of In is 0.1-0.2, and the thickness is 5-30nm; when the core barrier layer 42 is aluminum nitride AlN, its thickness is 2-10nm.
In a specific embodiment, the composite barrier layer 4 comprises an isolation layer 41 and a core barrier layer 42, wherein the isolation layer 41 is located on the channel layer 3 and the core barrier layer 42 is located on the isolation layer 41. The material of the isolation layer 41 may be AlN with a thickness of 0.5-1.5nm.
In a specific embodiment, the composite barrier layer 4 comprises an isolation layer 41, a core barrier layer 42 and a cap layer 43, wherein the isolation layer 41 is located on the channel layer 3, the core barrier layer 42 is located on the isolation layer 41, and the cap layer 43 is located on the core barrier layer 42.
In one embodiment, the material of the P-InGaN layer 5 comprises a Mg-doped InGaN layer having an In content of 0.08, a Ga content of 0.92, and a Mg doping concentration of 10 17 -10 20 cm -3 The thickness of the P-InGaN layer 5 is 5-150nm.
Specifically, the PMOS source electrode 51 is located on the P-InGaN layer 5; the PMOS drain electrode 52 is located on the P-InGaN layer 5; one end of the PMOS insulating dielectric layer 54 covers a portion of the PMOS source electrode 51, and the other end covers a portion of the PMOS drain electrode 52, and forms a recess structure with the bottom embedded in the P-InGaN layer 5; PMOS gate electrode 53 is located on PMOS insulating dielectric layer 54. The PMOS source electrode 51, the PMOS drain electrode 52, and the PMOS gate electrode 53 form a PMOS device; two-dimensional hole gas is formed at the interface of the P-InGaN layer 5 and the composite barrier layer 4, mainly as a conductive channel of PMOS.
It will be appreciated that the P-InGaN layer 5 between the PMOS source electrode 51 and the PMOS drain electrode 52 is etched to form a recess, the PMOS insulating dielectric layer 54 also forms a recess structure in the recess, the bottom of the recess structure is located on the etched P-InGaN layer 5, one side of the recess structure contacts the side of the P-InGaN layer 5 and the side of the PMOS source electrode 51, and the other side of the recess structure contacts the side of the P-InGaN layer 5 and the side of the PMOS drain electrode 52.
In one embodiment, PMOS gate electrode 53 includes gate header 531 and gate leg 532, wherein gate leg 532 is located in a recessed structure of PMOS insulating dielectric layer 54, and gate header 531 is located on PMOS insulating dielectric layer 54 and on gate leg 532; the width of the gate 531 is greater than the distance between the PMOS source electrode 51 and the PMOS drain electrode 52, i.e., the gate 531 is wider and the gate foot 532 is thinner, the width of the gate 531 being sufficient to cover the recess of the PMOS insulating dielectric layer 54. The PMOS gate electrode 53 is a metal electrode, or oxide/metal electrode, with a height of 50-800nm.
The NMOS source electrode 71 is embedded in the P-InGaN layer 5 and is located on the composite barrier layer 4; the NMOS drain electrode 72 is embedded in the P-InGaN layer 5 and is located on the composite barrier layer 4; an NMOS insulating dielectric layer 74 is located on the P-InGaN layer 5 between the NMOS source electrode 71 and the NMOS drain electrode 72 and covers a portion of the NMOS source electrode 71 and a portion of the NMOS drain electrode 72; the NMOS gate electrode 73 is located on the NMOS insulating dielectric layer 74. NMOS source electrode 71, NMOS drain electrode 72, NMOS gate electrode 73 form an NMOS device; a two-dimensional electron gas is formed at the cross section between the channel layer 3 and the composite barrier layer 4, mainly as a conductive channel of the NMOS device.
It is understood that the NMOS source electrode 71 and the NMOS drain electrode 72 have NMOS source and drain electrode recesses below, the P-InGaN layer 5 at the NMOS source and drain electrode recesses is removed, and the NMOS source and drain electrode recesses are filled with NMOS source and drain electrode metals, thereby forming the NMOS source and drain electrodes 71 and 72. Specifically, the depths of the NMOS source electrode groove and the NMOS drain electrode groove are both 30-200nm.
In one particular embodiment, the width of NMOS gate electrode 73 is greater than the spacing between NMOS source electrode 71 and NMOS drain electrode 72, i.e., the gate width of NMOS gate electrode 73 covers the channel of NMOS insulating dielectric layer 74. The NMOS gate electrode 73 is a metal electrode, or oxide/metal electrode, with a height of 50-800nm.
In one embodiment, the materials of PMOS source electrode 51, PMOS drain electrode 52, NMOS source electrode 71, NMOS drain electrode 72 each include one or more of titanium, aluminum, nickel, gold, tantalum, e.g., the materials of PMOS source electrode 51, PMOS drain electrode 52, NMOS source electrode 71, NMOS drain electrode 72 are titanium/aluminum/nickel/gold electrodes, or titanium/aluminum electrodes, or tantalum/aluminum electrodes; the thickness of the PMOS source electrode 51, the PMOS drain electrode 52, the NMOS source electrode 71 and the NMOS drain electrode 72 is 10-500nm.
In one embodiment, the thickness of both PMOS insulating dielectric layer 54 and NMOS insulating dielectric layer 74 is 50-150nm.
Specifically, the interconnect metal 6 has one end covering a portion of the PMOS drain electrode 52 and the other end covering a portion of the NMOS source electrode 71, and forms an isolation recess embedding the P-InGaN layer 5, the composite barrier layer 4, and the channel layer 3.
It will be appreciated that the middle portions of the P-InGaN layer 5 and the composite barrier layer 4 are completely etched away to form two portions for respectively manufacturing the NMOS device and the PMOS device, the channel layer 3 is etched away to form a recess, and the interconnect metal 6 forms a recess structure in the recess, the bottom of which is located on the channel layer 3, one side surface is in contact with the side surface of the channel layer 3, the side surface of the composite barrier layer 4, the side surface of the P-InGaN layer 5, and the side surface of the PMOS drain electrode 52, and the other side surface is in contact with the side surface of the channel layer 3, the side surface of the composite barrier layer 4, the side surface of the P-InGaN layer 5, and the side surface of the NMOS source electrode 71.
In a specific embodiment, the thickness of the interconnect metal 6 is 20-50nm. The depth of the isolation groove formed by the P-InGaN layer 5, the composite barrier layer 4 and the channel layer 3 under the interconnect metal 6 is 200-400nm.
Further, the PMOS source electrode 51 is connected to the power supply terminal V through a metal wire DD The PMOS gate electrode 53 and the NMOS gate electrode 73 are connected to the input terminal V through metal wiring IN The PMOS drain electrode 52 and the NMOS source electrode 71 are connected to the output terminal V through the interconnection metal 6 OUT NMOS drain electrode 72 is formed of metalThe connection is connected to the ground GND.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another CMOS inverter monolithically integrated with a GaN HEMT power electronic device according to an embodiment of the present invention, the CMOS inverter including: substrate 1, composite buffer layer 2, channel layer 3, composite barrier layer 4, P-InGaN layer 5, P + InGaN layer 8, PMOS source electrode 51, PMOS drain electrode 52, PMOS insulating dielectric layer 54, PMOS gate electrode 53, NMOS source electrode 71, NMOS drain electrode 72, NMOS insulating dielectric layer 74, NMOS gate electrode 73, and interconnect metal 6.
Wherein P is + An InGaN layer 8 is located on the P-InGaN layer 5. P (P) + The material of the InGaN layer 8 comprises a Mg-doped InGaN layer, wherein the Mg doping concentration is 10 17 -10 20 cm -3 ，P + The thickness of the InGaN layer 8 is 1-20nm.
Accordingly, in the PMOS device, P between the PMOS source electrode 51 and the PMOS drain electrode 52 + The InGaN layer 8 is etched away and the P-InGaN layer 5 is etched away to form a recess in which the PMOS insulating dielectric layer 54 also forms a recess structure with a bottom on the etched P-InGaN layer 5, one side of the recess structure being opposite to the side of the P-InGaN layer 5, P + The side of the InGaN layer 8, the side of the PMOS source electrode 51, the other side of the recess structure is in contact with the side of the P-InGaN layer 5, P + Side of InGaN layer 8 side contact of PMOS drain electrode 52. In the NMOS device, the NMOS source electrode 71 and the NMOS drain electrode 72 have an NMOS source recess and an NMOS drain electrode recess below, P at the NMOS source electrode recess and at the NMOS drain electrode recess + The InGaN layer 8 and the P-InGaN layer 5 are removed and the NMOS source recess and the NMOS drain recess are filled with NMOS source metal and NMOS drain metal, thereby forming an NMOS source electrode 71 and an NMOS drain electrode 72.
The CMOS inverter of the embodiment prepares the P-InGaN layer on the composite barrier layer, can generate holes, deplete two-dimensional electron gas between the composite barrier layer and the channel layer, and form two-dimensional hole gas at the interface of the composite barrier layer, thereby forming a conductive channel of the PMOS and improving the output current of the PMOS device.
In the CMOS inverter of the embodiment, the NMOS source electrode and the NMOS drain electrode are respectively formed in the grooves of the P-InGaN layer, then the NMOS gate electrode is formed between the NMOS source electrode and the NMOS drain electrode, the PMOS source electrode and the PMOS drain electrode are formed on the P-InGaN layer, and then the PMOS gate electrode is formed in the groove structure between the PMOS source electrode and the PMOS drain electrode, so that the spacing between the gate electrode and the source electrode and the spacing between the gate electrode and the drain electrode in the NMOS device and the PMOS device are reduced to the greatest extent, the on-resistance of the device is reduced, and the frequency performance of the device is improved; meanwhile, larger distances are kept between the surface of the gate electrode metal and the gate head metal of the gate electrode and between the surface of the drain electrode metal and the gate head metal of the gate electrode in the NMOS device and the PMOS device in the vertical direction, the parasitic capacitance of the device is reduced, and the negative influence of the parasitic capacitance of the gate source and the gate drain on the working frequency of the device is restrained.
The device structure formed by the embodiment has the advantages of compatibility with the existing GaN HEMT power electronic device material structure and manufacturing process, high device on-state current, low on-resistance, high switching speed, high device working frequency and good threshold voltage stability, reduces the source-drain interval, reduces the access resistance of a transistor, and simultaneously keeps small parasitic capacitance between a source electrode and a grid electrode and between a drain electrode and the grid electrode, thereby improving the frequency response characteristic of the device, and being applicable to the fields of microwave, millimeter wave and terahertz gallium nitride devices, circuits, chips, systems and the like.
Example two
On the basis of the first embodiment, please refer to fig. 3 a-3 j, and fig. 3 a-3 j are schematic process diagrams of a method for manufacturing a CMOS inverter monolithically integrated with a GaN HEMT power electronic device according to an embodiment of the present invention. The preparation method comprises the following steps:
s1, epitaxially growing a composite buffer layer 2, a channel layer 3 and a composite barrier layer 4 on a substrate 1 in sequence, see FIG. 3a.
Specifically, the composite buffer layer 2, the channel layer 3, and the composite barrier layer 4 are all group iii nitride epitaxial layers.
S2, epitaxially growing a P-InGaN layer 5 on the composite barrier layer 4, see FIG. 3b.
Specifically, the material of the P-InGaN layer 5 includes an Mg-doped InGaN layer In which the content of indium In is 0.08, the content of gallium Ga is 0.92, and the doping concentration of Mg is 10 17 -10 20 cm -3 The thickness of the P-InGaN layer 5 is 5-150nm.
S3, etching the P-InGaN layer 5, the composite barrier layer 4 and part of the channel layer 3 to form an interconnection metal groove 60, please refer to FIG. 3c.
Specifically, photoresist is spin-coated on the surface of the P-InGaN layer 5, and a photoetching machine is used for exposing and developing the metal interconnection area so as to expose the metal interconnection area; then, the P-InGaN layer 5, the composite barrier layer 4 and a part of the channel layer 3 of the metal interconnection region are etched to form interconnection metal grooves 60.
S4, etching the P-InGaN layer 5 on one side of the interconnection metal groove 60 to form an NMOS source electrode groove 710 and an NMOS drain electrode groove 720, see FIG. 3d.
Specifically, spin-coating photoresist on the surface of the P-InGaN layer, and exposing and developing the NMOS source electrode region and the NMOS drain electrode region by using a photoetching machine to expose the NMOS source electrode region and the NMOS drain electrode region; then, the P-InGaN layer 5 of the NMOS source electrode region and the NMOS drain electrode region is etched using the photoresist as a mask, forming a source electrode recess 710 and a drain electrode recess 720.
S5, electrode metal is deposited in the NMOS source electrode recess 710 and the NMOS drain electrode recess 720 to form an NMOS source electrode 71 and an NMOS drain electrode 72, see FIG. 3e.
Specifically, the depths of the NMOS source electrode groove and the NMOS drain electrode groove are both 30-200nm.
S6, electrode metal is deposited on the P-InGaN layer 5 at the other side of the interconnection metal groove 60 to form a PMOS source electrode 51 and a PMOS drain electrode 52, see FIG. 3f.
Specifically, photoresist is spin-coated on the surface of the P-AlGaN layer 5, a photo-etching machine is used to expose and develop the PMOS source electrode region and the PMOS drain electrode region, and then PMOS source electrode metal and PMOS drain electrode metal are deposited on the PMOS source electrode region and the PMOS drain electrode region respectively with the photoresist as a mask, so as to form a PMOS source electrode 51 and a PMOS drain electrode 52.
S7, etching a part of the P-InGaN layer 5 to form a PMOS gate electrode groove 530, see FIG. 3g.
Specifically, a portion of the P-InGaN layer 5 is etched with the PMOS source electrode 51 and the PMOS drain electrode 52 as masks, and a PMOS gate electrode recess 530 is formed between the PMOS source electrode 51 and the PMOS drain electrode 52.
S8, growing insulating dielectric materials on the P-InGaN layer 5 between the NMOS source electrode 71 and the NMOS drain electrode 72, on part of the NMOS source electrode 71, on part of the NMOS drain electrode 72, in the PMOS gate electrode groove 530, on part of the PMOS source electrode 51 and part of the PMOS drain electrode 52 to form a PMOS insulating dielectric layer 54 and an NMOS insulating dielectric layer 74; wherein one end of the PMOS insulating dielectric layer 54 covers a portion of the PMOS source electrode 51, and the other end covers a portion of the PMOS drain electrode 52, and forms a recess structure with the bottom embedded in the P-InGaN layer 5; an NMOS insulating dielectric layer 74 is located on the P-InGaN layer 5 between the NMOS source electrode 71 and the NMOS drain electrode 72 and covers a portion of the NMOS source electrode 71 and a portion of the NMOS drain electrode 72, see fig. 3h.
Specifically, first, an oxide insulating layer is grown on the surface of a device; then, photoresist is coated, and the photoresist outside the PMOS insulating dielectric layer region and the NMOS insulating dielectric layer region is exposed and developed by using a photoetching machine, so that the oxidation insulating layers outside the PMOS insulating dielectric layer region and the NMOS insulating dielectric layer region are exposed, and the exposed oxidation insulating layers are etched and removed, so that the PMOS insulating dielectric layer 54 and the NMOS insulating dielectric layer 74 are formed.
S9, growing gate electrode metal on the PMOS insulating dielectric layer 54 and the NMOS insulating dielectric layer 74 to form the PMOS gate electrode 53 and the NMOS gate electrode 73, wherein the width of the PMOS gate electrode 53 is larger than the distance between the PMOS source electrode 51 and the PMOS drain electrode 52, and the width of the NMOS gate electrode 73 is larger than the distance between the NMOS source electrode 71 and the NMOS drain electrode 72, see fig. 3i.
S10, growing the interconnect metal 6 in the interconnect metal groove 60, please refer to fig. 3j.
Specifically, the interconnect metal 6 is grown in the interconnect metal trench 60 such that one end of the interconnect metal 6 covers a portion of the PMOS drain electrode 52 and the other end covers the NMOS source electrode 71A part of the substrate is provided with an isolation groove embedded in the P-InGaN layer 5, the composite barrier layer 4 and the channel layer 3; and the PMOS source electrode 51 is led out through a metal wire to serve as a power supply end V DD PMOS gate electrode 53 and NMOS gate electrode 73 are led out as input terminal V IN PMOS drain electrode 52 and NMOS source electrode 71 are led out as output terminal V OUT The NMOS drain electrode 72 is led out as the ground GND.
Then, a passivation layer 9 is grown on the surface of the device to protect the device, thereby completing the preparation of the device, and the prepared device structure is shown in fig. 1 of the first embodiment, which is not described in detail.
Further, when employing the inclusion P of FIG. 2 in embodiment one + In the case of the CMOS inverter structure of InGaN layer 8, the corresponding P is required for the preparation of interconnect metal 6, PMOS insulating dielectric layer 54, NMOS source electrode 71, NMOS drain electrode 72 + The InGaN layer 8 is etched away to form a film comprising P + CMOS inverter of InGaN layer 8.
The preparation method of the embodiment does not use a heavy-doped III-nitride material regeneration technology, and has simple manufacturing process and lower process cost.
The CMOS inverter of the embodiment prepares the P-InGaN layer on the composite barrier layer, can generate holes, deplete two-dimensional electron gas between the composite barrier layer and the channel layer, and form two-dimensional hole gas at the interface of the composite barrier layer, thereby forming a conductive channel of the PMOS and improving the output current of the PMOS device.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (10)

1. A CMOS inverter monolithically integrated with a GaN HEMT power electronic device, comprising:
a substrate (1);
a composite buffer layer (2) located on the substrate (1);
a channel layer (3) located on the composite buffer layer (2);
a composite barrier layer (4) on the channel layer (3);
a P-InGaN layer (5) on the composite barrier layer (4);
a PMOS source electrode (51) located on the P-InGaN layer (5);
-a PMOS drain electrode (52) located on the P-InGaN layer (5);
a PMOS insulating dielectric layer (54) having one end covering a portion of the PMOS source electrode (51) and the other end covering a portion of the PMOS drain electrode (52) and forming a recess structure with a bottom embedded in the P-InGaN layer (5);
a PMOS gate electrode (53) located on the PMOS insulating dielectric layer (54);
an NMOS source electrode (71) embedded in the P-InGaN layer (5) and located on the composite barrier layer (4);
an NMOS drain electrode (72) embedded in the P-InGaN layer (5) and located on the composite barrier layer (4);
an NMOS insulating dielectric layer (74) which is positioned on the P-InGaN layer (5) between the NMOS source electrode (71) and the NMOS drain electrode (72) and covers part of the NMOS source electrode (71) and part of the NMOS drain electrode (72);
an NMOS gate electrode (73) located on the NMOS insulating dielectric layer (74);
and an interconnection metal (6) with one end covering a part of the PMOS drain electrode (52) and the other end covering a part of the NMOS source electrode (71) and forming an isolation groove embedded in the P-InGaN layer (5), the composite barrier layer (4) and the channel layer (3).
2. A CMOS inverter monolithically integrated with a GaN HEMT power electronic device as claimed in claim 1, wherein said composite buffer layer (2) comprises a nucleation layer (21), a transition layer (22), a core buffer layer (23) and a back barrier layer (24), wherein,
the nucleation layer (21) is located on the substrate (1), the transition layer (22) is located on the nucleation layer (21), the core buffer layer (23) is located on the transition layer (22), and the back barrier layer (24) is located on the core buffer layer (23).
3. The CMOS inverter monolithically integrated with the GaN HEMT power electronic device of claim 1, wherein the composite barrier layer (4) comprises an isolation layer (41), a core barrier layer (42), and a cap layer (43), wherein the isolation layer (41) is located on the channel layer (3), the core barrier layer (42) is located on the isolation layer (41), and the cap layer (43) is located on the core barrier layer (42).
4. A CMOS inverter monolithically integrated with a GaN HEMT power electronic device as claimed in claim 1, wherein the material of the P-InGaN layer (5) comprises a Mg doped InGaN layer, wherein the Mg doping concentration is 10 17 -10 20 cm -3 The thickness of the P-InGaN layer (5) is 5-150nm.
5. The CMOS inverter monolithically integrated with the GaN HEMT power electronic device of claim 1, wherein the PMOS source electrode (51), the PMOS drain electrode (52), the NMOS source electrode (71), and the NMOS drain electrode (72) each comprise one or more of titanium, aluminum, nickel, gold, and tantalum, each having a thickness of 10-500nm.
6. The CMOS inverter monolithically integrated with a GaN HEMT power electronic device of claim 1, wherein said PMOS gate electrode (53) comprises a gate head (531) and a gate foot (532), wherein said gate foot (532) is located in a recessed structure of said PMOS insulating dielectric layer (54), said gate head (531) is located on said PMOS insulating dielectric layer (54) and on said gate foot (532),
the width of the gate head (531) is larger than the distance between the PMOS source electrode (51) and the PMOS drain electrode (52);
the height of the PMOS gate electrode (53) is 50-800nm.
7. The CMOS inverter monolithically integrated with the GaN HEMT power electronic device of claim 1, wherein the NMOS gate electrode (73) has a width greater than the spacing between the NMOS source electrode (71) and the NMOS drain electrode (72);
the NMOS gate electrode (73) has a height of 50-800nm.
8. The CMOS inverter monolithically integrated with the GaN HEMT power electronic device of claim 1, further comprising P + -an InGaN layer (8), said P + -an InGaN layer (8) is located on the P-InGaN layer (5).
9. The CMOS inverter monolithically integrated with the GaN HEMT power electronic device of claim 8, wherein P + The material of the InGaN layer (8) comprises an Mg-doped InGaN layer, wherein the doping concentration of Mg is 10 17 -10 20 cm -3 The P is + The thickness of the InGaN layer (8) is 1-20nm.
10. The preparation method of the CMOS inverter monolithically integrated with the GaN HEMT power electronic device is characterized by comprising the following steps:
s1, sequentially epitaxially growing a composite buffer layer (2), a channel layer (3) and a composite barrier layer (4) on a substrate (1);
s2, epitaxially growing a P-InGaN layer (5) on the composite barrier layer (4);
s3, etching the P-InGaN layer (5), the composite barrier layer (4) and part of the channel layer (3) to form an interconnection metal groove (60);
s4, etching the P-InGaN layer (5) on one side of the interconnection metal groove (60) to form an NMOS source electrode groove (710) and an NMOS drain electrode groove (720);
s5, depositing electrode metal in the NMOS source electrode groove (710) and the NMOS drain electrode groove (720) to form an NMOS source electrode (71) and an NMOS drain electrode (72);
s6, electrode metal is deposited on the P-InGaN layer (5) at the other side of the interconnection metal groove (60) to form a PMOS source electrode (51) and a PMOS drain electrode (52);
s7, etching a part of the P-InGaN layer (5) to form a PMOS gate electrode groove (530);
s8, growing insulating dielectric materials on the P-InGaN layer (5) between the NMOS source electrode (71) and the NMOS drain electrode (72), part of the NMOS source electrode (71), part of the NMOS drain electrode (72), part of the PMOS gate electrode groove (530) and part of the PMOS source electrode (51) and part of the PMOS drain electrode (52) to form a PMOS insulating dielectric layer (54) and an NMOS insulating dielectric layer (74); wherein one end of the PMOS insulating medium layer (54) covers a part of the PMOS source electrode (51), the other end covers a part of the PMOS drain electrode (52), and a groove structure with the bottom embedded in the P-InGaN layer (5) is formed; the NMOS insulating dielectric layer (74) is positioned on the P-InGaN layer (5) between the NMOS source electrode (71) and the NMOS drain electrode (72) and covers part of the NMOS source electrode (71) and part of the NMOS drain electrode (72);
s9, growing gate electrode metal on the PMOS insulating medium layer (54) and the NMOS insulating medium layer (74) to form a PMOS gate electrode (53) and an NMOS gate electrode (73), wherein the width of the PMOS gate electrode (53) is larger than the distance between the PMOS source electrode (51) and the PMOS drain electrode (52), and the width of the NMOS gate electrode (73) is larger than the distance between the NMOS source electrode (71) and the NMOS drain electrode (72);
and S10, growing interconnection metal (6) in the interconnection metal groove (60).
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