CN104051522A - Enhanced nitride semiconductor device and manufacturing method thereof - Google Patents
Enhanced nitride semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN104051522A CN104051522A CN201410312838.4A CN201410312838A CN104051522A CN 104051522 A CN104051522 A CN 104051522A CN 201410312838 A CN201410312838 A CN 201410312838A CN 104051522 A CN104051522 A CN 104051522A
- Authority
- CN
- China
- Prior art keywords
- layer
- nitride
- grid
- barrier layer
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 176
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 66
- 239000002131 composite material Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000012212 insulator Substances 0.000 claims abstract description 27
- 238000002161 passivation Methods 0.000 claims abstract description 27
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 101
- 229910052759 nickel Inorganic materials 0.000 claims description 50
- 238000010276 construction Methods 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 29
- 239000011248 coating agent Substances 0.000 claims description 16
- 238000000576 coating method Methods 0.000 claims description 16
- -1 nitride compound Chemical class 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910000480 nickel oxide Inorganic materials 0.000 abstract description 17
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 abstract description 17
- 230000005669 field effect Effects 0.000 abstract description 5
- 230000003139 buffering effect Effects 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 229910002601 GaN Inorganic materials 0.000 description 16
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910002704 AlGaN Inorganic materials 0.000 description 3
- 229910004541 SiN Inorganic materials 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical group [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
Abstract
The invention discloses an enhanced nitride semiconductor device and a manufacturing method of the enhanced nitride semiconductor device. The device comprises a substrate, a nitride nucleating layer, a nitride buffering layer, a nitride channel layer, a nitride barrier layer, a drain electrode, a source electrode, a passivation medium layer and a grid electrode, wherein the nitride nucleating layer, the nitride buffering layer, the nitride channel layer and the nitride barrier layer are sequentially arranged on the substrate; the drain electrode and the source electrode make contact with the nitride barrier layer; the passivation medium layer is arranged on the area, except for the source electrode and the drain electrode, of the nitride barrier layer, and the grid electrode is of a three-layer composite structure and is formed by etching away the passivation medium layer on the area of the grid electrode; the grid electrode can be of a groove structure. The first layer of the grid electrode is insulator nickel oxide, the second layer is p-type semiconductor nickel oxide, and the third layer is a metal layer, so that two-dimensional electron gas below the grid electrode is exhausted when the grid voltage is zero, the enhanced metal insulator semiconductor field effect transistor structure is achieved, and meanwhile low electric leakage and high breakdown voltages are achieved.
Description
Technical field
The invention belongs to microelectronics technology, relate to a kind of manufacture method of semiconductor device and the semiconductor device making by the method, the reinforced metal insulator semiconductor field effect transistor (MISFET) that is specifically related to a kind of manufacture method of III nitride semiconductor devices and makes.
Background technology
Gallium nitride semiconductor material has the remarkable advantages such as energy gap is large, electronics saturation drift velocity is high, disruptive field intensity is high, high temperature resistant, compare with second generation Semiconductor GaAs with first generation semiconductor silicon, be more suitable in making high temperature, high pressure, high frequency and powerful electronic device, have broad application prospects, therefore become the focus of current semicon industry research.
GaN high electron mobility transistor (HEMT) is a kind of gallium nitride device that utilizes the two-dimensional electron gas formation at AlGaN/GaN heterojunction place, can be applied to high frequency, high pressure and powerful field.A kind of as field-effect transistor, gallium nitride HEMT mainly contains two types of depletion device and enhancement devices.Because two-dimensional electron gas has higher mobility and saturation drift velocity, the characteristic of conventionally utilizing Two-dimensional electron gas channel often to open is made the gallium nitride HEMT device of depletion type, is applicable to the high frequency applications such as radio communication.In other specific applications, as fields such as power switch and digital circuits, conventionally need to use the gallium nitride HEMT device of enhancement mode.
Yet with respect to depletion type gallium nitride HEMT device, enhancement type gallium nitride HEMT device is but not easy to realize.Realize the gallium nitride HEMT device of enhancement mode, in the time of need to finding way to make zero grid voltage, the concentration of AlGaN/GaN heterojunction place, gate electrode below two-dimensional electron gas is reduced to enough low.Way is that an etching is carried out in gate regions, and the thickness of attenuate grid below aluminum gallium nitride barrier layer, to reduce the concentration of grid below two-dimensional electron gas.Second method is selective retention p-type nitride below grid, lifts the Fermi level at AlGaN/GaN heterojunction place by p-type nitride, forms depletion region, realizes enhancement device.
These two kinds of methods have weak point.In first method, threshold voltage is generally no more than 1V, does not reach 3 required～5V of practical application.Therefore,, in order to improve threshold voltage, also needing increases dielectric layer in addition as alundum (Al2O3).But there is the interfacial state of higher density in alundum (Al2O3) dielectric layer and aluminum gallium nitride barrier layer interface, can increase the current collapse of device, the efficiency of device is affected greatly.In the second approach, when retaining p-type nitride, need to etch away grid below other All Rangeses in addition.Accurate control to etch thicknesses is a more insoluble problem.And the defect that etching causes, and the magnesium atom producing in p-type gallium nitride, all can cause current collapse effect.In addition, the hole concentration that the ionization of p-type gallium nitride produces is generally no more than 1E18cm
-3.So low hole concentration so that the two-dimensional electron gas of grid below all exhausts, cannot make two-dimensional electron gas conducting channel turn-off completely deficiency.So just be difficult to realize real enhancement device.
Therefore, for above-mentioned technical problem, be necessary to provide a kind of nitride compound semiconductor device with structure improved enhancement mode, to overcome above-mentioned defect.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of enhancement mode nitride compound semiconductor device and manufacture method thereof of the compound grid structure being formed by nickel oxide.
Nickel oxide is a kind of special oxide, can be by regulating the ratio of nickel and oxygen to change its electrology characteristic.Under the different proportion condition of nickel and oxygen, nickel oxide can be insulator, can be metal, can be also P type semiconductor.By P type nickel oxide, insulator oxide nickel, metal level and other dielectric layers, form reasonably composite structuredly as grid, can form conductor insulator semiconductor fet (MISFET), and realize enhancement mode MISFET structure.
For achieving the above object, the invention provides a kind of manufacture method of enhancement mode nitride compound semiconductor device, comprise the steps:
1, provide a substrate;
2, on above-mentioned substrate, form successively nitride nucleating layer, nitride resilient coating, nitride channel layer and nitride barrier layer layer;
3, formation contacts with above-mentioned nitride barrier layer layer drain electrode and source electrode;
4, the area deposition passivation dielectric layer except source electrode and drain electrode on above-mentioned nitride barrier layer layer, etches away the passivation dielectric layer at area of grid place, at the grid of area of grid place formation composite construction;
Wherein, described grid is between described source electrode and drain electrode, and the grid of this composite construction at least comprises three layers that arrange successively, and being respectively ground floor is insulator oxide nickel, and the second layer is p-type semiconductor oxide nickel, and the 3rd layer is metal level.
Each nickel oxide layer in this composite construction grid can be made by methods such as thermal oxidation, ALD, CVD, MOCVD, PVD, and dissimilar nickel oxide layer can be made by diverse ways.
Preferably, after etching away the passivation dielectric layer at area of grid place, described in continuation etching, nitride barrier layer layer forms groove, then in groove, forms grid, and the bottom of described groove is not less than the conducting channel of described nitride channel layer and the two-dimensional electron gas formation of place, nitride barrier layer bed boundary.
Preferably, above described nitride barrier layer layer, below composite construction grid, can also first deposit insulating medium layer, as SiN, SiO
2, SiON, SiAlN, Al
2o
3, HfO
2deng.
Preferably, after forming nitride channel layer, first form nitride insert layer, then form nitride barrier layer layer.
Preferably, on described nitride barrier layer layer, first form nitride and emit layer, then form drain electrode and the source electrode that emits layer to contact with above-mentioned nitride;
Further, at above-mentioned nitride, emit on layer the area deposition passivation dielectric layer except source electrode and drain electrode, etch away the passivation dielectric layer at area of grid place, continue nitride described in etching and emit a layer formation groove, in groove, form grid, the bottom of described groove is not run through described nitride and is emitted layer again.
Preferably, described passivation dielectric layer is one or more in silicon dioxide, silicon nitride, sial nitrogen.
The present invention also provides a kind of enhancement mode nitride compound semiconductor device being prepared by said method, comprising:
Substrate;
Be located at successively nitride nucleating layer, nitride resilient coating, nitride channel layer and nitride barrier layer layer on described substrate;
The drain electrode and the source electrode that contact with described nitride barrier layer layer;
Be located on described nitride barrier layer layer and remove source electrode and the passivation dielectric layer of drain electrode with exterior domain, etch away the grid of the composite construction forming after the passivation dielectric layer at area of grid place;
Wherein, described grid is between described source electrode and drain electrode, and the grid of this composite construction at least comprises three layers that arrange successively, and being respectively ground floor is insulator oxide nickel, and the second layer is p-type semiconductor oxide nickel, and the 3rd layer is metal level.
Preferably, on the nitride barrier layer layer below area of grid, be provided with groove, form the grid of composite construction in described groove, the bottom of described groove is not less than the conducting channel of described nitride channel layer and the two-dimensional electron gas formation of place, nitride barrier layer bed boundary.
Preferably, can first metallization medium layer under nickel oxide, as SiN, SiO
2, SiON, SiAlN, Al
2o
3, HfO
2deng.
Preferably, between described nitride channel layer and nitride barrier layer layer, be provided with nitride insert layer.
Preferably, be provided with nitride and emit layer on described nitride barrier layer layer, described drain electrode and source electrode emit layer to contact with nitride;
Further, the nitride below area of grid emits on layer and is provided with groove, forms the grid of three-layer composite structure in described groove, and the bottom of described groove is not run through described nitride and emitted layer.
Preferably, described passivation dielectric layer is one or more in silicon dioxide, silicon nitride, sial nitrogen.
From technique scheme, can find out, p-type semiconductor oxide nickel of the present invention can lift the Fermi level in the Two-dimensional electron gas channel of grid below, exhaust the two-dimensional electron gas of grid below or greatly reduce the concentration of two-dimensional electron gas, realize the normal pass device under zero grid voltage; Insulator oxide nickel can reduce electric leakage of the grid, improves the disruptive field intensity of grid, improves the puncture voltage of device; By forming grid groove structure, can attenuate nitride barrier layer layer, reduce the concentration of the two-dimensional electron gas of nitride barrier layer layer and the formation of nitride channel layer interface, the threshold voltage that improves device makes it to forward transfer, thereby realize, has the enhancement device that higher threshold voltage is convenient to practical application.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing relevant of the present invention in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the cross-sectional view of the enhancement mode nitride compound semiconductor device of the embodiment of the present invention 1;
Fig. 2 is the cross-sectional view of the enhancement mode nitride compound semiconductor device of the embodiment of the present invention 2;
Fig. 3 is the cross-sectional view of the enhancement mode nitride compound semiconductor device of the embodiment of the present invention 3;
Fig. 4 is the cross-sectional view of the enhancement mode nitride compound semiconductor device of the embodiment of the present invention 4;
Fig. 5 is the cross-sectional view of the enhancement mode nitride compound semiconductor device of the embodiment of the present invention 5;
Fig. 6 is the cross-sectional view of the enhancement mode nitride compound semiconductor device of the embodiment of the present invention 6.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is described in detail, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work, belongs to the scope of protection of the invention.
Embodiment 1
In present embodiment, described device is to have the enhancement mode MIS device that forms successively the composite construction grid of insulator oxide nickel, p-type semiconductor oxide nickel and burning nickel from substrate direction.By reference to the accompanying drawings 1, this semiconductor device comprises: substrate 1; Nitride nucleating layer 21 on substrate 1; Nitride resilient coating 22 on nitride nucleating layer 21; Nitride channel layer 23 on nitride resilient coating 22; Nitride barrier layer layer 24 on nitride channel layer 23; The grid that on nitride barrier layer layer 24, area of grid forms; The source electrode 31 contacting with above-mentioned nitride barrier layer layer 24 and drain electrode 32.Wherein, above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.
Above-mentioned grid consists of the nickel oxide layer with composite construction, from substrate direction, comprises that successively insulator oxide nickel 51, p-type semiconductor oxide nickel 52 and burning nickel 53,53 can be also other metal levels; The nickel oxide of above-mentioned composite construction can be by regulating the ratio of oxygen and nickel to realize.On nitride barrier layer layer 24, can comprise passivation dielectric layer 4, comprising one or more combination in silicon nitride, silicon dioxide, sial nitrogen.
The manufacture method of above-mentioned semiconductor device, comprises the following steps:
Substrate 1 is provided; On substrate 1, form nitride nucleating layer 21; On nitride nucleating layer 21, form nitride resilient coating 22; On nitride resilient coating 22, form nitride channel layer 23; On nitride channel layer 23, form nitride barrier layer layer 24; On nitride barrier layer layer 24, form the source electrode 31 and the drain electrode 32 that contact; Area deposition passivation dielectric layer 4 on above-mentioned nitride barrier layer layer 24 except source electrode 31 and drain electrode 32; Etch away the passivation dielectric layer 4 at area of grid place; Nickel oxide layer at area of grid place deposition composite construction forms grid.Wherein, above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.
Above-mentioned grid consists of the nickel oxide layer with composite construction, from substrate direction, comprises that successively insulator oxide nickel 51, p-type semiconductor oxide nickel 52 and burning nickel 53,53 can be also other metal levels; The nickel oxide of above-mentioned composite construction can be by regulating the ratio of oxygen and nickel to realize.
In present embodiment, by forming the nickel oxide of composite construction, realize enhancement mode MIS device.Wherein, p-type semiconductor oxide nickel 52 can lift the Fermi level in the Two-dimensional electron gas channel of grid below, exhausts the two-dimensional electron gas of grid below or greatly reduces the concentration of two-dimensional electron gas, realizes the normal pass device under zero grid voltage.Insulator oxide nickel 51 can reduce electric leakage of the grid, improves the disruptive field intensity of grid, improves the puncture voltage of device.
Embodiment 2
In present embodiment, described device is to have from substrate direction to form successively the composite construction grid of insulator oxide nickel, p-type semiconductor oxide nickel and metal and have the enhancement mode MIS device of grid groove structure.By reference to the accompanying drawings 2, to compare with embodiment 1, in present embodiment, difference is, grid has groove structure.In present embodiment, the manufacture method of described groove structure is: during by etching passivation dielectric layer 4, etch away part nitride barrier layer layer 24, thereby the nitride barrier layer layer 24 of attenuate grid below forms grid groove structure; Then in grid groove structure, deposit nickel oxide, form successively insulator oxide nickel 51, p-type semiconductor oxide nickel 52 and burning nickel 53.By forming grid groove structure, can attenuate nitride barrier layer layer 24, reduce the concentration of the two-dimensional electron gas of nitride barrier layer layer 24 and the 23 interfaces formation of nitride channel layer, the threshold voltage that improves device makes it to forward transfer, thereby realize, has the enhancement device that higher threshold voltage is convenient to practical application.Other structures and manufacture method, with embodiment 1, do not repeat them here.
Embodiment 3
In present embodiment, described device is to have the enhancement mode MIS device that forms successively the composite construction grid of insulator oxide nickel, p-type semiconductor oxide nickel and metal from substrate direction.By reference to the accompanying drawings 3, this semiconductor device comprises: substrate 1; Nitride nucleating layer 21 on substrate 1; Nitride resilient coating 22 on nitride nucleating layer 21; Nitride channel layer 23 on nitride resilient coating 22; Nitride insert layer 25 on nitride channel layer 23; Nitride barrier layer layer 24 in nitride insert layer 25; The grid that on nitride barrier layer layer 24, area of grid forms; The source electrode 31 contacting with above-mentioned nitride barrier layer layer 24 and drain electrode 32.Wherein, above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.Compare with embodiment 1, the difference of present embodiment is, between nitride channel layer 23 and nitride barrier layer layer 24, has increased nitride insert layer 25, can improve the concentration of two-dimensional electron gas in raceway groove, improve the carrier mobility of device, and then improve the frequency characteristic of device.Other structures and manufacture method, with embodiment 1, do not repeat them here.
Embodiment 4
In present embodiment, described device is to have the enhancement mode MIS device that forms successively the composite construction grid of insulator oxide nickel, p-type semiconductor oxide nickel and metal from substrate direction.By reference to the accompanying drawings 4, this semiconductor device comprises: substrate 1; Nitride nucleating layer 21 on substrate 1; Nitride resilient coating 22 on nitride nucleating layer 21; Nitride channel layer 23 on nitride resilient coating 22; Nitride barrier layer layer 24 on nitride channel layer 23; Nitride on nitride barrier layer layer 24 emits layer 26; Nitride emits the grid that on layer 26, area of grid forms; Emit layer 26 source electrode contacting 31 and drain electrode 32 with above-mentioned nitride.Wherein, above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.Compare with embodiment 1, the difference of present embodiment is, has increased nitride and emit layer 26 on nitride barrier layer layer 24, can reduce nitride-based semiconductor surface state, and effects on surface plays the effect of passivation and protection, reduces the current collapse effect of device.Other structures and manufacture method, with embodiment 1, do not repeat them here.
Embodiment 5
In present embodiment, described device is to have the enhancement mode MIS device that forms successively the composite construction grid of insulator oxide nickel, p-type semiconductor oxide nickel and metal from substrate direction.By reference to the accompanying drawings 5, this semiconductor device comprises: substrate 1; Nitride nucleating layer 21 on substrate 1; Nitride resilient coating 22 on nitride nucleating layer 21; Nitride channel layer 23 on nitride resilient coating 22; Nitride barrier layer layer 24 on nitride channel layer 23; Nitride on nitride barrier layer layer 24 emits layer 26; Nitride emits the grid that on layer 26, area of grid forms; Emit layer 26 source electrode contacting 31 and drain electrode 32 with above-mentioned nitride.Wherein, above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.Compare with embodiment 1, the difference of present embodiment is, has increased nitride and emit layer 26 on nitride barrier layer layer 24, and the composite construction grid that insulator oxide nickel, p-type semiconductor oxide nickel and burning nickel form simultaneously has groove structure.Nitride emits layer 26 can reduce nitride-based semiconductor surface state, and effects on surface plays the effect of passivation and protection, reduces the current collapse effect of device.Meanwhile, p-type semiconductor oxide nickel emits layer 26 to contact with nitride gesture, can further reduce the concentration of the two-dimensional electron gas of grid below, improves the threshold voltage of device, contributes to realize enhancement device.Other structures and manufacture, with embodiment 1, do not repeat them here.
Embodiment 6
In present embodiment, described device is to have the enhancement mode MIS device that forms successively the composite construction grid of insulator oxide nickel, p-type semiconductor oxide nickel and metal from substrate direction, and insulator oxide nickel is optional.By reference to the accompanying drawings 6, this semiconductor device comprises: substrate 1; Nitride nucleating layer 21 on substrate 1; Nitride resilient coating 22 on nitride nucleating layer 21; Nitride channel layer 23 on nitride resilient coating 22; Nitride barrier layer layer 24 on nitride channel layer 23; The insulating medium layer 6 that on nitride barrier layer layer 24, area of grid forms; The grid forming on insulating medium layer 6; The source electrode 31 contacting with above-mentioned nitride barrier layer layer 24 and drain electrode 32.Wherein, above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.
Compare with embodiment 1, the difference of present embodiment is, above nitride barrier layer layer 24, can first deposit insulating medium layer below composite construction grid, described insulating medium layer can comprise SiN, SiO2, SiON, SiAlN, Al
2o
3, HfO
2deng.This insulating medium layer also can be considered a part in composite construction grid, and even this insulating medium layer can replace the insulator oxide nickel of top.The composite construction grid that insulator oxide nickel, p-type semiconductor oxide nickel and burning nickel form simultaneously has groove structure.Other structures and manufacture, with embodiment 1, do not repeat them here.
By above-mentioned execution mode, the nitride insulation grid field effect transistor that nitride insulation grid field effect transistor manufacture method of the present invention makes has following beneficial effect:
First, p-type semiconductor oxide nickel can lift the Fermi level in the Two-dimensional electron gas channel of grid below, exhausts the two-dimensional electron gas of grid below or greatly reduces the concentration of two-dimensional electron gas, realizes the normal pass device under zero grid voltage;
Secondly, insulator oxide nickel can reduce electric leakage of the grid, improves the disruptive field intensity of grid, improves the puncture voltage of device;
Again, prepared by the ratio that insulator oxide nickel and p-type nickel oxide can deposit by adjusting, the process conditions in oxidizing process change O and Ni, can realize the contamination of avoiding surperficial by single-step process, reduces current collapse and the leakage current density of device.
Finally, by forming grid groove structure, can attenuate nitride barrier layer layer, reduce the concentration of the two-dimensional electron gas of nitride barrier layer layer and the formation of nitride channel layer interface, the threshold voltage that improves device makes it to forward transfer, thereby realize, has the enhancement device that higher threshold voltage is convenient to practical application.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and in the situation that not deviating from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims rather than above-mentioned explanation, is therefore intended to include in the present invention dropping on the implication that is equal to important document of claim and all changes in scope.Any Reference numeral in claim should be considered as limiting related claim.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should make specification as a whole, and the technical scheme in each embodiment also can, through appropriately combined, form other execution modes that it will be appreciated by those skilled in the art that.
Claims (14)
1. a manufacture method for enhancement mode nitride compound semiconductor device, is characterized in that, comprises the steps:
(1) provide a substrate;
(2) on described substrate, form successively nitride nucleating layer, nitride resilient coating, nitride channel layer and nitride barrier layer layer;
(3) form drain electrode and the source electrode contacting with described nitride barrier layer layer;
(4) the area deposition passivation dielectric layer except source electrode and drain electrode on described nitride barrier layer layer, etches away the passivation dielectric layer at area of grid place, at the grid of area of grid place formation composite construction;
Wherein, described grid is between described source electrode and drain electrode, and the grid of this composite construction at least comprises three layers that arrange successively, and being respectively ground floor is that insulator oxide nickel, the second layer are p-type semiconductor oxide nickel, and the 3rd layer is metal level.
2. manufacture method according to claim 1, it is characterized in that: after etching away the passivation dielectric layer at area of grid place, described in continuation etching, nitride barrier layer layer forms groove, in groove, form grid, the bottom of described groove is not less than the conducting channel of described nitride channel layer and the two-dimensional electron gas formation of place, nitride barrier layer bed boundary again.
3. manufacture method according to claim 1 and 2, is characterized in that: after forming nitride channel layer, first form nitride insert layer, then form nitride barrier layer layer.
4. manufacture method according to claim 1 and 2, is characterized in that: on described nitride barrier layer layer, first form nitride and emit layer, then form drain electrode and the source electrode that emits layer to contact with described nitride.
5. manufacture method according to claim 4, it is characterized in that: at described nitride, emit the area deposition passivation dielectric layer except source electrode and drain electrode on layer, etch away the passivation dielectric layer at area of grid place, described in continuation etching, nitride emits layer to form a groove, in groove, form grid, the bottom of described groove is not run through described nitride and is emitted layer again.
6. manufacture method according to claim 1, is characterized in that: described passivation dielectric layer is one or more in silicon dioxide, silicon nitride, sial nitrogen.
7. manufacture method as claimed in claim 1, is characterized in that: above described nitride barrier layer layer, can also first deposit insulating medium layer below composite construction grid.
8. an enhancement mode nitride compound semiconductor device of being manufactured by manufacture method claimed in claim 1, is characterized in that, comprising:
Substrate;
Be located at successively nitride nucleating layer, nitride resilient coating, nitride channel layer and nitride barrier layer layer on described substrate;
The drain electrode and the source electrode that contact with described nitride barrier layer layer;
Be located on described nitride barrier layer layer and remove source electrode and the passivation dielectric layer of drain electrode with exterior domain, etch away the grid of the three-layer composite structure forming after the passivation dielectric layer at area of grid place;
Wherein, described grid is between described source electrode and drain electrode, and the grid of this composite construction at least comprises three layers that arrange successively, and being respectively ground floor is insulator oxide nickel, and the second layer is p-type semiconductor oxide nickel, and the 3rd layer is metal level.
9. semiconductor device according to claim 8, it is characterized in that: on the nitride barrier layer layer below area of grid, be provided with groove, in described groove, form the grid of composite construction, the bottom of described groove is not less than the conducting channel of described nitride channel layer and the two-dimensional electron gas formation of place, nitride barrier layer bed boundary.
10. semiconductor device according to claim 8 or claim 9, is characterized in that: between described nitride channel layer and nitride barrier layer layer, be provided with nitride insert layer.
11. semiconductor device according to claim 8 or claim 9, is characterized in that: on described nitride barrier layer layer, be provided with nitride and emit layer, described drain electrode and source electrode emit layer to contact with nitride.
12. semiconductor device according to claim 11, is characterized in that: the nitride below area of grid emits on layer and is provided with groove, forms the grid of three-layer composite structure in described groove, and the bottom of described groove is not run through described nitride and emitted layer.
13. semiconductor device according to claim 8, is characterized in that: described passivation dielectric layer is one or more in silicon dioxide, silicon nitride, sial nitrogen.
14. semiconductor device according to claim 8, is characterized in that: above described nitride barrier layer layer, be provided with insulating medium layer below composite construction grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410312838.4A CN104051522B (en) | 2014-07-02 | 2014-07-02 | A kind of enhanced nitride compound semiconductor device and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410312838.4A CN104051522B (en) | 2014-07-02 | 2014-07-02 | A kind of enhanced nitride compound semiconductor device and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104051522A true CN104051522A (en) | 2014-09-17 |
| CN104051522B CN104051522B (en) | 2018-05-11 |
Family
ID=51504143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410312838.4A Active CN104051522B (en) | 2014-07-02 | 2014-07-02 | A kind of enhanced nitride compound semiconductor device and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104051522B (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104966731A (en) * | 2015-07-06 | 2015-10-07 | 大连理工大学 | HEMT device with sandwich grid medium structure and preparation method thereof |
| CN105702821A (en) * | 2016-03-29 | 2016-06-22 | 苏州晶湛半导体有限公司 | Semiconductor light-emitting device and manufacturing method thereof |
| CN106549051A (en) * | 2017-01-18 | 2017-03-29 | 中国科学院微电子研究所 | GaN base HEMT device grid structure |
| CN108155099A (en) * | 2017-12-22 | 2018-06-12 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of p-type grid HEMT device comprising dielectric layer and preparation method thereof |
| CN108538908A (en) * | 2018-04-04 | 2018-09-14 | 华南理工大学 | A kind of enhanced GaN HEMT devices and preparation method thereof |
| CN108649065A (en) * | 2018-05-31 | 2018-10-12 | 江苏能华微电子科技发展有限公司 | A kind of normally-off gallium nitride HEMT device and preparation method thereof |
| CN108807524A (en) * | 2017-09-06 | 2018-11-13 | 苏州捷芯威半导体有限公司 | Semiconductor devices and its manufacturing method |
| WO2018223387A1 (en) * | 2017-06-09 | 2018-12-13 | 苏州晶湛半导体有限公司 | Reinforced switch device and method for manufacturing same |
| CN109817710A (en) * | 2018-12-29 | 2019-05-28 | 英诺赛科（珠海）科技有限公司 | High electron mobility transistor and its manufacturing method |
| CN110010562A (en) * | 2015-02-12 | 2019-07-12 | 英飞凌科技奥地利有限公司 | Semiconductor devices |
| CN111326568A (en) * | 2020-03-10 | 2020-06-23 | 苏州晶界半导体有限公司 | Nitride device with guard ring structure |
| WO2020191629A1 (en) * | 2019-03-26 | 2020-10-01 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method therefor |
| CN112185959A (en) * | 2020-08-28 | 2021-01-05 | 西安电子科技大学 | CMOS inverter monolithically integrated with GaN HEMT power electronic device and preparation method thereof |
| CN112335056A (en) * | 2020-09-09 | 2021-02-05 | 英诺赛科(苏州)科技有限公司 | Semiconductor device structure and method of manufacturing the same |
| WO2021102681A1 (en) * | 2019-11-26 | 2021-06-03 | 苏州晶湛半导体有限公司 | Semiconductor structure and method for manufacture thereof |
| WO2021102683A1 (en) * | 2019-11-26 | 2021-06-03 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method therefor |
| CN113257907A (en) * | 2020-02-12 | 2021-08-13 | 苏州晶界半导体有限公司 | Double-sided structure field effect transistor based on nitride |
| CN113628963A (en) * | 2021-08-05 | 2021-11-09 | 苏州英嘉通半导体有限公司 | III-nitride enhanced HEMT device and manufacturing method thereof |
| CN114520262A (en) * | 2022-02-17 | 2022-05-20 | 电子科技大学 | Enhanced MIS-GaN device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1937249A (en) * | 2006-10-16 | 2007-03-28 | 中国电子科技集团公司第五十五研究所 | Aluminium gallium nitride/gallium nitride high electronic migration rate transistor and its manufacturing method |
| US8125004B2 (en) * | 2008-12-24 | 2012-02-28 | Sanken Electric Co., Ltd. | Field-effect semiconductor device |
| CN102664188A (en) * | 2012-05-10 | 2012-09-12 | 电子科技大学 | Gallium nitride-based high-electron-mobility transistor with composite buffering layer |
| CN102723358A (en) * | 2012-05-30 | 2012-10-10 | 程凯 | Isolated gate field effect transistor and manufacture method thereof |
| CN102945860A (en) * | 2012-11-21 | 2013-02-27 | 西安电子科技大学 | AlGaN/GaN heterojunction enhancement-mode device with in-situ SiN cap layer and production method thereof |
| US20130168687A1 (en) * | 2011-06-29 | 2013-07-04 | Industrial Technology Research Institute | Enhancement mode gallium nitride based transistor device |
| CN103681830A (en) * | 2012-09-11 | 2014-03-26 | 中国科学院微电子研究所 | Double-channel transistor and preparation method for double-channel transistor |
-
2014
- 2014-07-02 CN CN201410312838.4A patent/CN104051522B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1937249A (en) * | 2006-10-16 | 2007-03-28 | 中国电子科技集团公司第五十五研究所 | Aluminium gallium nitride/gallium nitride high electronic migration rate transistor and its manufacturing method |
| US8125004B2 (en) * | 2008-12-24 | 2012-02-28 | Sanken Electric Co., Ltd. | Field-effect semiconductor device |
| US20130168687A1 (en) * | 2011-06-29 | 2013-07-04 | Industrial Technology Research Institute | Enhancement mode gallium nitride based transistor device |
| CN102664188A (en) * | 2012-05-10 | 2012-09-12 | 电子科技大学 | Gallium nitride-based high-electron-mobility transistor with composite buffering layer |
| CN102723358A (en) * | 2012-05-30 | 2012-10-10 | 程凯 | Isolated gate field effect transistor and manufacture method thereof |
| CN103681830A (en) * | 2012-09-11 | 2014-03-26 | 中国科学院微电子研究所 | Double-channel transistor and preparation method for double-channel transistor |
| CN102945860A (en) * | 2012-11-21 | 2013-02-27 | 西安电子科技大学 | AlGaN/GaN heterojunction enhancement-mode device with in-situ SiN cap layer and production method thereof |
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010562B (en) * | 2015-02-12 | 2023-09-15 | 英飞凌科技奥地利有限公司 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
| CN110010562A (en) * | 2015-02-12 | 2019-07-12 | 英飞凌科技奥地利有限公司 | Semiconductor devices |
| CN104966731A (en) * | 2015-07-06 | 2015-10-07 | 大连理工大学 | HEMT device with sandwich grid medium structure and preparation method thereof |
| CN104966731B (en) * | 2015-07-06 | 2018-04-10 | 大连理工大学 | HEMT device with sandwich gate dielectric structure and preparation method thereof |
| CN105702821A (en) * | 2016-03-29 | 2016-06-22 | 苏州晶湛半导体有限公司 | Semiconductor light-emitting device and manufacturing method thereof |
| CN106549051A (en) * | 2017-01-18 | 2017-03-29 | 中国科学院微电子研究所 | GaN base HEMT device grid structure |
| WO2018223387A1 (en) * | 2017-06-09 | 2018-12-13 | 苏州晶湛半导体有限公司 | Reinforced switch device and method for manufacturing same |
| US10998435B2 (en) | 2017-06-09 | 2021-05-04 | Enkris Semiconductor, Inc. | Enhancement-mode device and method for manufacturing the same |
| CN110100313A (en) * | 2017-06-09 | 2019-08-06 | 苏州晶湛半导体有限公司 | A kind of enhanced switching device and its manufacturing method |
| CN108807524B (en) * | 2017-09-06 | 2021-11-02 | 苏州捷芯威半导体有限公司 | Semiconductor device and method for manufacturing the same |
| CN108807524A (en) * | 2017-09-06 | 2018-11-13 | 苏州捷芯威半导体有限公司 | Semiconductor devices and its manufacturing method |
| CN108155099A (en) * | 2017-12-22 | 2018-06-12 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of p-type grid HEMT device comprising dielectric layer and preparation method thereof |
| CN108538908A (en) * | 2018-04-04 | 2018-09-14 | 华南理工大学 | A kind of enhanced GaN HEMT devices and preparation method thereof |
| CN108649065A (en) * | 2018-05-31 | 2018-10-12 | 江苏能华微电子科技发展有限公司 | A kind of normally-off gallium nitride HEMT device and preparation method thereof |
| CN109817710A (en) * | 2018-12-29 | 2019-05-28 | 英诺赛科（珠海）科技有限公司 | High electron mobility transistor and its manufacturing method |
| WO2020191629A1 (en) * | 2019-03-26 | 2020-10-01 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method therefor |
| US11876129B2 (en) | 2019-03-26 | 2024-01-16 | Enkris Semiconductor, Inc. | Semiconductor structure and manufacturing method for the semiconductor structure |
| WO2021102681A1 (en) * | 2019-11-26 | 2021-06-03 | 苏州晶湛半导体有限公司 | Semiconductor structure and method for manufacture thereof |
| WO2021102683A1 (en) * | 2019-11-26 | 2021-06-03 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method therefor |
| CN113257907A (en) * | 2020-02-12 | 2021-08-13 | 苏州晶界半导体有限公司 | Double-sided structure field effect transistor based on nitride |
| CN111326568A (en) * | 2020-03-10 | 2020-06-23 | 苏州晶界半导体有限公司 | Nitride device with guard ring structure |
| CN112185959A (en) * | 2020-08-28 | 2021-01-05 | 西安电子科技大学 | CMOS inverter monolithically integrated with GaN HEMT power electronic device and preparation method thereof |
| CN112185959B (en) * | 2020-08-28 | 2024-03-29 | 西安电子科技大学 | CMOS inverter monolithically integrated with GaN HEMT power electronic device and preparation method |
| WO2022051932A1 (en) * | 2020-09-09 | 2022-03-17 | Innoscience (Suzhou) Technology Co., Ltd. | Semiconductor device structures and methods of manufacturing the same |
| US11862722B2 (en) | 2020-09-09 | 2024-01-02 | Innoscience (Suzhou) Technology Co., Ltd. | Semiconductor device structures and methods of manufacturing the same |
| CN112335056A (en) * | 2020-09-09 | 2021-02-05 | 英诺赛科(苏州)科技有限公司 | Semiconductor device structure and method of manufacturing the same |
| CN113628963A (en) * | 2021-08-05 | 2021-11-09 | 苏州英嘉通半导体有限公司 | III-nitride enhanced HEMT device and manufacturing method thereof |
| CN113628963B (en) * | 2021-08-05 | 2024-03-08 | 苏州英嘉通半导体有限公司 | III-nitride enhanced HEMT device and manufacturing method thereof |
| CN114520262A (en) * | 2022-02-17 | 2022-05-20 | 电子科技大学 | Enhanced MIS-GaN device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104051522B (en) | 2018-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104051522A (en) | Enhanced nitride semiconductor device and manufacturing method thereof | |
| EP3059757B1 (en) | Group-iii nitride semiconductor device and manufacturing method therefor | |
| JP6373509B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| US10672896B2 (en) | GaN-based bidirectional switch device | |
| JP6486828B2 (en) | Etching technology for semiconductor structure and recess formation | |
| CN102386223B (en) | High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method | |
| CN103715086A (en) | Method for manufacturing enhancement device | |
| CN103337516B (en) | Enhancement mode switching device and manufacture method thereof | |
| CN102239550A (en) | Field effect transistor | |
| CN102709321A (en) | Enhanced switch element and production method thereof | |
| CN105336789A (en) | GaN-based field effect transistor with high quality MIS structure and preparation method of GaN-based field effect transistor | |
| CN102629624A (en) | Metal-insulator-semiconductor (MIS) grid enhanced high electron mobility transistor (HEMT) device based on gallium nitride (GaN) and manufacture method of MIS grid enhanced HEMT device | |
| CN104167445B (en) | GaN-based enhancement/depletion mode heterojunction field effect transistor with buried gate structure | |
| CN108417493A (en) | P-type grid enhancement transistor and preparation method thereof based on oxidation self-stopping technology technology | |
| CN112635545B (en) | Enhanced GaN-based MIS-HEMT with asymmetric gate dielectric layer and preparation method thereof | |
| CN104332504A (en) | GaN-based heterojunction schottky diode device and preparing method thereof | |
| CN102856366A (en) | Enhancement type device | |
| CN102856370B (en) | A kind of enhancement mode switching device | |
| Lu et al. | GaN power electronics | |
| CN103745990B (en) | Depletion-mode AlGaN/GaN MISHEMT high tension apparatus and preparation method thereof | |
| US20150364562A1 (en) | Semiconductor device | |
| US20130146888A1 (en) | Monolithic semiconductor device and method for manufacturing the same | |
| WO2014129245A1 (en) | Nitride semiconductor device | |
| CN104157679A (en) | GaN-based enhancement type heterogeneous junction field effect transistor | |
| TWI803770B (en) | Diode, method of manufacturing diode, and electric machine |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |