CN104051522B - A kind of enhanced nitride compound semiconductor device and its manufacture method - Google Patents
A kind of enhanced nitride compound semiconductor device and its manufacture method Download PDFInfo
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- CN104051522B CN104051522B CN201410312838.4A CN201410312838A CN104051522B CN 104051522 B CN104051522 B CN 104051522B CN 201410312838 A CN201410312838 A CN 201410312838A CN 104051522 B CN104051522 B CN 104051522B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- -1 nitride compound Chemical class 0.000 title claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 156
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 65
- 230000004888 barrier function Effects 0.000 claims abstract description 64
- 229910000480 nickel oxide Inorganic materials 0.000 claims abstract description 39
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000002131 composite material Substances 0.000 claims abstract description 33
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 33
- 239000012212 insulator Substances 0.000 claims abstract description 27
- 238000002161 passivation Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000010276 construction Methods 0.000 claims description 28
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- 150000001875 compounds Chemical class 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 239000004020 conductor Substances 0.000 abstract description 4
- 229910002601 GaN Inorganic materials 0.000 description 14
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 8
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910002704 AlGaN Inorganic materials 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical group [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- YLZGECKKLOSBPL-UHFFFAOYSA-N indium nickel Chemical compound [Ni].[In] YLZGECKKLOSBPL-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
Abstract
The present invention discloses a kind of enhanced nitride compound semiconductor device and its manufacture method, which includes substrate；Nitride nucleating layer, nitride buffer layer, nitride channel and the nitride barrier layer being sequentially arranged on substrate；The drain electrode being in contact with nitride barrier layer and source electrode；Source electrode is removed on nitride barrier layer and is drained with the passivation dielectric layer of exterior domain, etches away the grid of the three-layer composite structure formed after the passivation dielectric layer at area of grid；Grid can have groove structure.The first layer of grid is insulator oxide nickel, the second layer is p-type semiconductor nickel oxide, third layer is metal layer, so that the two-dimensional electron gas below grid is exhausted during zero grid voltage, realize enhanced conductor insulator semiconductor fet structure, while there is relatively low electric leakage and higher breakdown voltage.
Description
Technical field
The invention belongs to microelectronics technology, is related to a kind of manufacture method of semiconductor devices and by party's legal system
The semiconductor devices obtained, and in particular to a kind of manufacture method of III nitride semiconductor devices and obtained reinforced metal
Insulator semiconductor field effect transistor (MISFET).
Background technology
Gallium nitride semiconductor material has big energy gap, electronics saturation drift velocity height, disruptive field intensity height, high temperature resistant etc.
Remarkable advantage, compared with first generation semiconductor silicon and second generation Semiconductor GaAs, more suitable for making high temperature, high pressure, high frequency
With powerful electronic device, have broad application prospects, therefore as the hot spot of current semicon industry research.
GaN high electron mobility transistor (HEMT) is formed using the two-dimensional electron gas at AlGaN/GaN hetero-junctions
A kind of gallium nitride device, can be applied to high frequency, high pressure and powerful field.As one kind of field-effect transistor, nitrogen
Changing gallium HEMT mainly has depletion device and enhancement device two types.Due to two-dimensional electron gas have higher mobility and
Saturation drift velocity, usually makes the gallium nitride HEMT device of depletion type using the normally opened characteristic of Two-dimensional electron gas channel, fits
For the high frequency application field such as wireless communication.In fields such as other specific application field such as power switch and digital circuit, lead to
Often need to use enhanced gallium nitride HEMT device.
However, relative to depletion type gallium nitride HEMT device, enhancement type gallium nitride HEMT device is but not easily accomplished.Realize
Enhanced gallium nitride HEMT device is, it is necessary to find when method causes zero grid voltage below gate electrode two at AlGaN/GaN hetero-junctions
The concentration of dimensional electron gas is reduced to sufficiently low.A kind of method is that gate regions are performed etching, and aluminum gallium nitride potential barrier below grid is thinned
The thickness of layer, to reduce the concentration of two-dimensional electron gas below grid.Second method is square selective retention p-type nitrogen under the gate
Compound, lifts the fermi level at AlGaN/GaN hetero-junctions by p-type nitride, forms depletion region, realize enhancement device.
Both approaches have shortcoming.In first method, threshold voltage is usually no more than 1V, does not reach reality
Using 3 required~5V.Therefore, in order to improve threshold voltage, it is also necessary in addition increase dielectric layer such as alundum (Al2O3).But
Interfacial state of the alundum (Al2O3) dielectric layer with aluminum gallium nitride barrier layer interface there are higher density, the electric current that can increase device collapse
Collapse, the efficiency of device is affected greatly.In the second approach, it is necessary to etch away grid while p-type nitride is retained
Other all areas beyond below pole.Accurate control to etch thicknesses, is a more insoluble problem.Moreover,
The defects of etching causes, and the magnesium atom produced in p-type gallium nitride, it can all cause current collapse effect.In addition, p-type nitrogenizes
The hole concentration that gallium ionization produces is usually no more than 1E18cm-3.So low hole concentration will be insufficient to allow below grid two
Dimensional electron gas all exhaust, and can not complete switch off two-dimensional electron gas conducting channel.Thus it is difficult to realize really enhanced
Device.
Therefore, for above-mentioned technical problem, it is necessary to provide it is a kind of have structure improved enhanced nitride partly lead
Body device, to overcome drawbacks described above.
The content of the invention
In view of this, it is an object of the invention to provide a kind of the enhanced of compound gate structure being made of nickel oxide
Nitride compound semiconductor device and its manufacture method.
Nickel oxide is a kind of special oxide, can change its electrology characteristic by adjusting the ratio of nickel and oxygen.
Under the conditions of the different proportion of nickel and oxygen, nickel oxide can be insulator, can be metal or P-type semiconductor.Pass through P
Type nickel oxide, insulator oxide nickel, metal layer and other dielectric layers formed it is rational it is composite structured be used as grid, can be with shape
Into conductor insulator semiconductor fet (MISFET), and realize enhanced MISFET structures.
To achieve the above object, the present invention provides a kind of manufacture method of enhanced nitride compound semiconductor device, including
Following step：
The 1st, one substrate is provided；
2nd, nitride nucleating layer, nitride buffer layer, nitride channel and nitride are sequentially formed on above-mentioned substrate
Barrier layer；
3rd, the drain electrode being in contact with above-mentioned nitride barrier layer and source electrode are formed；
4th, the area deposition passivation dielectric layer on above-mentioned nitride barrier layer in addition to source electrode and drain electrode, etches away grid
Passivation dielectric layer at region, forms the grid of composite construction at area of grid；
Wherein, the grid is located between the source electrode and drain electrode, and the grid of the composite construction includes at least to be arranged successively
Three layers of cloth, are respectively that first layer is insulator oxide nickel, the second layer is p-type semiconductor nickel oxide, and third layer is metal layer.
Each nickel oxide layer in the composite construction grid can pass through the side such as thermal oxide, ALD, CVD, MOCVD, PVD
Method makes, and different types of nickel oxide layer can be made by different methods.
Preferably, after the passivation dielectric layer at area of grid is etched away, continue to etch the nitride barrier layer being formed
Groove, forms grid in groove, and the bottom of the groove is not less than the nitride channel and nitride barrier layer stratum boundary
The conducting channel that two-dimensional electron gas is formed at face.
Preferably, insulating medium layer can also be first deposited above the nitride barrier layer, below composite construction grid,
Such as SiN, SiO2、SiON、SiAlN、Al2O3、HfO2Deng.
Preferably, after nitride channel is formed, nitride insert layer is initially formed, re-forms nitride barrier layer.
Preferably, nitride cap is initially formed on the nitride barrier layer, re-formed and above-mentioned nitride cap phase
The drain electrode of contact and source electrode；
Further, the area deposition passivation dielectric layer in above-mentioned nitride cap in addition to source electrode and drain electrode, etching
Fall the passivation dielectric layer at area of grid, continue to etch the nitride cap formation groove, grid is formed in groove, institute
The bottom of groove is stated not through the nitride cap.
Preferably, the passivation dielectric layer is one or more of in silica, silicon nitride, sial nitrogen.
The present invention also provides a kind of enhanced nitride compound semiconductor device being prepared by the above method, including：
Substrate；
Nitride nucleating layer, nitride buffer layer, nitride channel and the nitride gesture being sequentially arranged on the substrate
Barrier layer；
The drain electrode being in contact with the nitride barrier layer and source electrode；
Except source electrode and drain electrode are with the passivation dielectric layer of exterior domain on the nitride barrier layer, area of grid is etched away
The grid of the composite construction formed after the passivation dielectric layer at place；
Wherein, the grid is located between the source electrode and drain electrode, and the grid of the composite construction includes at least to be arranged successively
Three layers of cloth, are respectively that first layer is insulator oxide nickel, the second layer is p-type semiconductor nickel oxide, and third layer is metal layer.
Preferably, groove is equipped with the nitride barrier layer below area of grid, composite construction is formed in the groove
Grid, the bottom of the groove is formed not less than the nitride channel and nitride barrier layer interface two-dimensional electron gas
Conducting channel.
Preferably, under nickel oxide can first metallization medium layer, such as SiN, SiO2、SiON、SiAlN、Al2O3、 HfO2Deng.
Preferably, nitride insert layer is equipped between the nitride channel and nitride barrier layer.
Preferably, nitride cap, the drain electrode and source electrode and nitride cap are equipped with the nitride barrier layer
It is in contact；
Further, groove is equipped with the nitride cap below area of grid, three layers of formation is compound in the groove
The grid of structure, the bottom of the groove is not through the nitride cap.
Preferably, the passivation dielectric layer is one or more of in silica, silicon nitride, sial nitrogen.
It can be seen from the above technical proposal that the p-type semiconductor nickel oxide of the present invention can lift two dimension electricity below grid
Fermi level in sub- gas channel, exhausts the two-dimensional electron gas below grid or substantially reduces the concentration of two-dimensional electron gas, realizes
Normal pass device under zero grid voltage；Insulator oxide nickel can reduce electric leakage of the grid, improve the disruptive field intensity of grid, improve device
Breakdown voltage；By forming gate recess structure, nitride barrier layer can be thinned, reduce nitride barrier layer and nitride ditch
The concentration for the two-dimensional electron gas that channel layer interface is formed, improving the threshold voltage of device makes it to forward transfer, so as to fulfill tool
There is the enhancement device that higher threshold voltage is easy to practical application.
Brief description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the attached drawing for the present invention in describing below is only the one of the present invention
A little embodiments, for those of ordinary skill in the art, without creative efforts, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the cross-sectional view of the enhanced nitride compound semiconductor device of the embodiment of the present invention 1；
Fig. 2 is the cross-sectional view of the enhanced nitride compound semiconductor device of the embodiment of the present invention 2；
Fig. 3 is the cross-sectional view of the enhanced nitride compound semiconductor device of the embodiment of the present invention 3；
Fig. 4 is the cross-sectional view of the enhanced nitride compound semiconductor device of the embodiment of the present invention 4；
Fig. 5 is the cross-sectional view of the enhanced nitride compound semiconductor device of the embodiment of the present invention 5；
Fig. 6 is the cross-sectional view of the enhanced nitride compound semiconductor device of the embodiment of the present invention 6.
Embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, detailed retouch is carried out to the technical solution in the embodiment of the present invention
State, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.Based on the present invention
In embodiment, the every other implementation that those of ordinary skill in the art are obtained on the premise of creative work is not made
Example, belongs to the scope of protection of the invention.
Embodiment 1
In present embodiment, the device is with sequentially forming insulator oxide nickel, p-type semiconductor from substrate direction
The enhanced MIS devices of the composite construction grid of nickel oxide and metal nickel oxide.With reference to attached drawing 1, which includes：Lining
Bottom 1；Nitride nucleating layer 21 on substrate 1；Nitride buffer layer 22 on nitride nucleating layer 21；On nitride buffer layer 22
Nitride channel 23；Nitride barrier layer 24 on nitride channel 23；Area of grid shape on nitride barrier layer 24
Into grid；The source electrode 31 being in contact with above-mentioned nitride barrier layer 24 and drain electrode 32.Wherein, above-mentioned grid is located at above-mentioned source electrode
Between 31 and above-mentioned drain electrode 32.
Above-mentioned grid is made of the nickel oxide layer with composite construction, includes insulator oxide nickel successively from substrate direction
51st, p-type semiconductor nickel oxide 52 and metal nickel oxide 53,53 can also be other metal layers；The nickel oxide of above-mentioned composite construction
It can be realized by adjusting the ratio of oxygen and nickel.It can include passivation dielectric layer 4 on nitride barrier layer 24, including nitrogen
One or more of combination in SiClx, silica, sial nitrogen.
The manufacture method of above-mentioned semiconductor device, comprises the following steps：
Substrate 1 is provided；Nitride nucleating layer 21 is formed on substrate 1；Nitride is formed on nitride nucleating layer 21 to delay
Rush layer 22；Nitride channel 23 is formed on nitride buffer layer 22；Nitride barrier layer is formed on nitride channel 23
Layer 24；The source electrode 31 being in contact and drain electrode 32 are formed on nitride barrier layer 24；Source is removed on above-mentioned nitride barrier layer 24
Area deposition passivation dielectric layer 4 beyond pole 31 and drain electrode 32；Etch away the passivation dielectric layer 4 at area of grid；In gate regions
The nickel oxide layer of deposited complex structures forms grid at domain.Wherein, above-mentioned grid be located at above-mentioned source electrode 31 and above-mentioned drain electrode 32 it
Between.
Above-mentioned grid is made of the nickel oxide layer with composite construction, includes insulator oxide nickel successively from substrate direction
51st, p-type semiconductor nickel oxide 52 and metal nickel oxide 53,53 can also be other metal layers；The nickel oxide of above-mentioned composite construction
It can be realized by adjusting the ratio of oxygen and nickel.
In present embodiment, enhanced MIS devices are realized by forming the nickel oxide of composite construction.Wherein, p-type half
Conductor indium nickel 52 can lift the fermi level in Two-dimensional electron gas channel below grid, exhaust the Two-dimensional electron below grid
Gas or the concentration for substantially reducing two-dimensional electron gas, realize the normal pass device under zero grid voltage.Insulator oxide nickel 51 can reduce grid
Pole is leaked electricity, and improves the disruptive field intensity of grid, improves the breakdown voltage of device.
Embodiment 2
In present embodiment, the device is with sequentially forming insulator oxide nickel, p-type semiconductor from substrate direction
The composite construction grid of nickel oxide and metal and the enhanced MIS devices with grid slot structure.With reference to attached drawing 2, with 1 phase of embodiment
Than difference is in present embodiment, and grid has groove structure.In present embodiment, the manufacture of the groove structure
Method is：Partial nitridation thing barrier layer 24 is etched away during by etching passivation dielectric layer 4, so that the nitride below grid be thinned
Barrier layer 24, forms gate recess structure；Then the deposited oxide nickel in gate recess structure, sequentially forms insulator oxide nickel
51st, p-type semiconductor nickel oxide 52 and metal nickel oxide 53.By forming gate recess structure, nitride barrier layer can be thinned
24, the concentration of nitride barrier layer 24 and the two-dimensional electron gas of 23 interface of nitride channel formation is reduced, improves device
Threshold voltage makes it to forward transfer, so as to fulfill the enhancement device of practical application is easy to higher threshold voltage.Other
Structure and manufacture method are with embodiment 1, and details are not described herein.
Embodiment 3
In present embodiment, the device is with sequentially forming insulator oxide nickel, p-type semiconductor from substrate direction
The enhanced MIS devices of the composite construction grid of nickel oxide and metal.With reference to attached drawing 3, which includes：Substrate 1；Lining
Nitride nucleating layer 21 on bottom 1；Nitride buffer layer 22 on nitride nucleating layer 21；Nitridation on nitride buffer layer 22
Thing channel layer 23；Nitride insert layer 25 on nitride channel 23；Nitride barrier layer 24 in nitride insert layer 25；
The grid that area of grid is formed on nitride barrier layer 24；The source electrode 31 being in contact with above-mentioned nitride barrier layer 24 and drain electrode
32.Wherein, above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.Compared with Example 1, the difference of present embodiment
Part is, nitride insert layer 25 is added between nitride channel 23 and nitride barrier layer 24, can improve raceway groove
The concentration of middle two-dimensional electron gas, improves the carrier mobility of device, and then improves the frequency characteristic of device.Other structures and system
Method is made with embodiment 1, details are not described herein.
Embodiment 4
In present embodiment, the device is with sequentially forming insulator oxide nickel, p-type semiconductor from substrate direction
The enhanced MIS devices of the composite construction grid of nickel oxide and metal.With reference to attached drawing 4, which includes：Substrate 1；Lining
Nitride nucleating layer 21 on bottom 1；Nitride buffer layer 22 on nitride nucleating layer 21；Nitridation on nitride buffer layer 22
Thing channel layer 23；Nitride barrier layer 24 on nitride channel 23；Nitride cap 26 on nitride barrier layer 24；Nitrogen
The grid that area of grid is formed in compound cap layers 26；The source electrode 31 being in contact with above-mentioned nitride cap 26 and drain electrode 32.Wherein,
Above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.Compared with Example 1, the difference of present embodiment exists
In adding nitride cap 26 on nitride barrier layer 24, nitride-based semiconductor surface state can be reduced, surface is played
Passivation and the effect of protection, reduce the current collapse effect of device.Other structures and manufacture method are with embodiment 1, herein no longer
Repeat.
Embodiment 5
In present embodiment, the device is with sequentially forming insulator oxide nickel, p-type semiconductor from substrate direction
The enhanced MIS devices of the composite construction grid of nickel oxide and metal.With reference to attached drawing 5, which includes：Substrate 1；Lining
Nitride nucleating layer 21 on bottom 1；Nitride buffer layer 22 on nitride nucleating layer 21；Nitridation on nitride buffer layer 22
Thing channel layer 23；Nitride barrier layer 24 on nitride channel 23；Nitride cap 26 on nitride barrier layer 24；Nitrogen
The grid that area of grid is formed in compound cap layers 26；The source electrode 31 being in contact with above-mentioned nitride cap 26 and drain electrode 32.Wherein,
Above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.Compared with Example 1, the difference of present embodiment exists
In adding nitride cap 26, while insulator oxide nickel, p-type semiconductor nickel oxide and gold on nitride barrier layer 24
Belonging to the composite construction grid that nickel oxide is formed has groove structure.Nitride cap 26 can reduce nitride-based semiconductor surface
State, plays the role of passivation and protection to surface, reduces the current collapse effect of device.Meanwhile p-type semiconductor nickel oxide and nitrogen
Compound gesture cap layers 26 contact, and can further reduce the concentration of the two-dimensional electron gas below grid, improve the threshold voltage of device,
Help to realize enhancement device.Other structures and manufacture are with embodiment 1, and details are not described herein.
Embodiment 6
In present embodiment, the device is with sequentially forming insulator oxide nickel, p-type semiconductor from substrate direction
The enhanced MIS devices of the composite construction grid of nickel oxide and metal, insulator oxide nickel is optional., should be partly with reference to attached drawing 6
Conductor device includes：Substrate 1；Nitride nucleating layer 21 on substrate 1；Nitride buffer layer 22 on nitride nucleating layer 21；
Nitride channel 23 on nitride buffer layer 22；Nitride barrier layer 24 on nitride channel 23；Nitride barrier layer
The insulating medium layer 6 that area of grid is formed on layer 24；The grid formed on insulating medium layer 6；With above-mentioned nitride barrier layer 24
The source electrode 31 being in contact and drain electrode 32.Wherein, above-mentioned grid is between above-mentioned source electrode 31 and above-mentioned drain electrode 32.
Compared with Example 1, the difference of present embodiment is, above nitride barrier layer 24, composite construction
Insulating medium layer can be first deposited below grid, the insulating medium layer can include SiN, SiO2, SiON, SiAlN, Al2O3、
HfO2Deng.The insulating medium layer also can be considered a part in composite construction grid, or even the insulating medium layer can be with
Substitute the insulator oxide nickel of top.What insulator oxide nickel, p-type semiconductor nickel oxide and metal nickel oxide were formed at the same time is compound
Structure grid has groove structure.Other structures and manufacture are with embodiment 1, and details are not described herein.
By above-mentioned embodiment, nitride made from nitride insulation grid field effect transistor manufacture method of the present invention
Isolated-gate field effect transistor (IGFET) has the advantages that：
First, p-type semiconductor nickel oxide can lift the fermi level in Two-dimensional electron gas channel below grid, exhaust grid
Two-dimensional electron gas below pole or the concentration for substantially reducing two-dimensional electron gas, that realizes under zero grid voltage normal closes device；
Secondly, insulator oxide nickel can reduce electric leakage of the grid, improve the disruptive field intensity of grid, improve the breakdown potential of device
Pressure；
Again, insulator oxide nickel and p-type nickel oxide can be changed by the process conditions adjusted in deposition, oxidizing process
Prepared by the ratio of O and Ni, the contamination to avoid surface can be realized by single-step process, reduces current collapse and the electric leakage of device
Current density.
Finally, by forming gate recess structure, nitride barrier layer can be thinned, reduce nitride barrier layer and nitridation
The concentration of the two-dimensional electron gas formed at thing channel layer interface, improving the threshold voltage of device makes it to forward transfer, so that real
Now there is the enhancement device that higher threshold voltage is easy to practical application.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Profit requires rather than described above limits, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.Any reference numeral in claim should not be considered as to the involved claim of limitation.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each embodiment is only wrapped
Containing an independent technical solution, this narrating mode of specification is only that those skilled in the art should for clarity
Using specification as an entirety, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
It is appreciated that other embodiment.
Claims (14)
1. a kind of manufacture method of enhanced nitride compound semiconductor device, it is characterised in that comprise the following steps：
(1) substrate is provided；
(2) nitride nucleating layer, nitride buffer layer, nitride channel and nitride barrier layer are sequentially formed over the substrate
Layer；
(3) drain electrode being in contact with the nitride barrier layer and source electrode are formed；
(4) the area deposition passivation dielectric layer on the nitride barrier layer in addition to source electrode and drain electrode, etches away gate regions
Passivation dielectric layer at domain, forms the grid of composite construction at area of grid；
Wherein, the grid is located between the source electrode and drain electrode, and the grid of the composite construction includes at least what is arranged successively
Three layers, be respectively first layer be insulator oxide nickel, the second layer be p-type semiconductor nickel oxide, third layer is oxidation nickel metal layer,
The grid of composite construction is realized with single-step process by adjusting the ratio of oxygen and nickel.
2. manufacture method according to claim 1, it is characterised in that：Etching away the passivation dielectric layer at area of grid
Afterwards, continue to etch the nitride barrier layer formation groove, grid is formed in groove, the bottom of the groove is not less than institute
State the conducting channel that nitride channel and nitride barrier layer interface two-dimensional electron gas are formed.
3. manufacture method according to claim 1 or 2, it is characterised in that：After nitride channel is formed, nitrogen is initially formed
Compound insert layer, re-forms nitride barrier layer.
4. manufacture method according to claim 1 or 2, it is characterised in that：Nitrogen is initially formed on the nitride barrier layer
Compound cap layers, re-form the drain electrode being in contact with the nitride cap and source electrode.
5. manufacture method according to claim 4, it is characterised in that：In the nitride cap except source electrode and drain electrode with
Outer area deposition passivation dielectric layer, etches away the passivation dielectric layer at area of grid, continues to etch the nitride cap shape
Into groove, grid is formed in groove, the bottom of the groove is not through the nitride cap.
6. manufacture method according to claim 1, it is characterised in that：The passivation dielectric layer for silica, silicon nitride,
It is one or more of in sial nitrogen.
7. manufacture method as claimed in claim 1, it is characterised in that：Above the nitride barrier layer, composite construction grid
Insulating medium layer can also be first deposited below pole.
A kind of 8. enhanced nitride compound semiconductor device that manufacture method as described in claim 1 manufactures, it is characterised in that bag
Include：
Substrate；
Nitride nucleating layer, nitride buffer layer, nitride channel and the nitride barrier layer being sequentially arranged on the substrate；
The drain electrode being in contact with the nitride barrier layer and source electrode；
Except source electrode and drain electrode are with the passivation dielectric layer of exterior domain on the nitride barrier layer, etch away at area of grid
The grid of the three-layer composite structure formed after passivation dielectric layer；
Wherein, the grid is located between the source electrode and drain electrode, and the grid of the composite construction includes at least what is arranged successively
Three layers, be respectively that first layer is insulator oxide nickel, and the second layer is p-type semiconductor nickel oxide, and third layer is oxidation nickel metal layer,
The grid of composite construction is realized with single-step process by adjusting the ratio of oxygen and nickel.
9. semiconductor devices according to claim 8, it is characterised in that：On the nitride barrier layer below area of grid
Equipped with groove, form the grid of composite construction in the groove, the bottom of the groove not less than the nitride channel and
The conducting channel that nitride barrier layer interface two-dimensional electron gas is formed.
10. semiconductor devices according to claim 8 or claim 9, it is characterised in that：In the nitride channel and nitride
Nitride insert layer is equipped between barrier layer.
11. semiconductor devices according to claim 8 or claim 9, it is characterised in that：Nitrogen is equipped with the nitride barrier layer
Compound cap layers, the drain electrode and source electrode are in contact with nitride cap.
12. semiconductor devices according to claim 11, it is characterised in that：In the nitride cap below area of grid
Equipped with groove, the grid of three-layer composite structure is formed in the groove, the bottom of the groove is not through the nitride cap.
13. semiconductor devices according to claim 8, it is characterised in that：The passivation dielectric layer is silica, nitridation
It is one or more of in silicon, sial nitrogen.
14. semiconductor devices according to claim 8, it is characterised in that：Above the nitride barrier layer, composite junction
Insulating medium layer is equipped with below structure grid.
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| CN113906573A (en) | 2019-03-26 | 2022-01-07 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method thereof |
| WO2021102683A1 (en) * | 2019-11-26 | 2021-06-03 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method therefor |
| US20220115525A1 (en) * | 2019-11-26 | 2022-04-14 | Enkris Semiconductor, Inc. | Semiconductor structures and manufacturing methods thereof |
| CN113257907A (en) * | 2020-02-12 | 2021-08-13 | 苏州晶界半导体有限公司 | Double-sided structure field effect transistor based on nitride |
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