CN103441144B - HEMT device and manufacture method thereof - Google Patents
HEMT device and manufacture method thereof Download PDFInfo
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- CN103441144B CN103441144B CN201310400284.9A CN201310400284A CN103441144B CN 103441144 B CN103441144 B CN 103441144B CN 201310400284 A CN201310400284 A CN 201310400284A CN 103441144 B CN103441144 B CN 103441144B
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Abstract
The invention provides HEMT device and for the method manufacturing HEMT device.According to an aspect of the invention, it is provided a kind of HEMT device, including: the semiconductor layer on substrate；Sealing coat on above-mentioned semiconductor layer；The source electrode contacted with above-mentioned semiconductor layer and drain electrode；The first medium layer on the whole region between above-mentioned source electrode and drain electrode on above-mentioned sealing coat；And the grid on above-mentioned first medium layer；Wherein, above-mentioned grid is double-decker, and it is conductive layer at the middle and upper levels, and lower floor is second dielectric layer, and above-mentioned second dielectric layer exists only under above-mentioned conductive layer, and above-mentioned first medium layer includes the dielectric material that can reduce device current pull-in effect.
Description
The application is the Application No. 200810098656.6, entitled submitted on June 5th, 2008
The divisional application of the patent application of " HEMT device and manufacture method thereof ".
Technical field
The present invention relates to wide bandgap semiconductor gallium nitride HEMT (HEMT) device,
It particularly relates to utilize composite dielectric materials structure to reduce the same of gallium nitride HEMT grid leakage current
Time alleviate current collapse effect device structure design.
Background technology
The dielectric breakdown voltage of third generation semiconductor gallium nitride (GaN) is significantly larger than first generation quasiconductor
Silicon (Si) or second filial generation Semiconductor GaAs (GaAs), up to 3MV/cm so that it is electronic device
The highest voltage can be born.The raceway groove of gallium nitride heterojunction structure has the highest electron concentration and electronics
Mobility, it means that leading in altofrequency of GaN high electron mobility transistor (HEMT)
Logical high electric current, and there is the lowest conducting resistance.It addition, gallium nitride is wide bandgap semiconductor, can work
Make in higher temperature.These characteristics make gallium nitride HEMT be particularly well-suited to manufacture the high power of high frequency
Radio-frequency devices and the pressure switching device of height.
In AlGaN/GaN hetero-junctions HEMT, there is the highest polarity effect, cause device surface
Highdensity electron trap occurs.The response speed of electron trap is slow, thus causes current collapse effect.
For reply current collapse effect, nowadays gallium nitride HEMT typically uses SiN medium 102 material such as grade
The passivation technology (Fig. 1) on covering device surface.The mechanism that surface passivation reduces current collapse effect is existing
The most not exclusively determining.The problem that SiN surface passivation technique brings is owing to having in SiN medium
Higher leakage current, thereby increases the leakage current of grid, thus reduce device breakdown voltage and
Input impedance, and the linearity of device can be deteriorated.
Test finds, SiO2Leakage current in medium is the least.Place one layer of SiO under the gate2Medium,
Compare metal Schottky-based contact and can be greatly reduced the Leakage Current of grid.This device is referred to as metal
Insulant field-effect transistor (MISFET).SiO2Can be formed between layer and AlGaN layer
The most highdensity electron trap, high current pull-in effect.Even if using on this MISFET
SiN surface passivating treatment, current collapse effect still exists.It is believed that the electric current on MISFET
Pull-in effect mostlys come from SiO under grid2Interface electron trap with AlGaN.
Summary of the invention
In order to solve above-mentioned problems of the prior art, the invention provides HEMT device, with
And for the method manufacturing HEMT device.
According to an aspect of the invention, it is provided a kind of HEMT device, including: on substrate
Semiconductor layer；Sealing coat on above-mentioned semiconductor layer；The source electrode contacted with above-mentioned semiconductor layer and leakage
Pole；The first medium layer on the whole region between above-mentioned source electrode and drain electrode on above-mentioned sealing coat；
And the grid on above-mentioned first medium layer；Wherein, above-mentioned grid is double-decker, and it is at the middle and upper levels
For conductive layer, lower floor is second dielectric layer, and above-mentioned second dielectric layer exists only under above-mentioned conductive layer,
Above-mentioned first medium layer includes the dielectric material that can reduce device current pull-in effect.
According to another aspect of the present invention, it is provided that a kind of method for manufacturing HEMT device,
Comprise the following steps: deposited semiconductor layer on substrate；Layer deposited isolating on above-mentioned semiconductor layer；
Form the source electrode and drain electrode contacted with above-mentioned semiconductor layer；Above-mentioned source electrode on above-mentioned sealing coat and leakage
First medium layer is deposited on region between pole；Above-mentioned first medium layer deposits second dielectric layer；
Above-mentioned second dielectric layer is formed grid conductor；And using above-mentioned grid conductor as mask, etching
Above-mentioned second dielectric layer, the stack gate being made up of above-mentioned grid conductor and above-mentioned second dielectric layer with formation
Pole.
Accompanying drawing explanation
Believe by below in conjunction with the accompanying drawing explanation to the specific embodiment of the invention, it is possible to make people more
Understand well the above-mentioned feature of the present invention, advantage and purpose, wherein:
Fig. 1 shows former design: the surface passivating treatment of gallium nitride HEMT.
Fig. 2 shows former design: gallium-nitride metal insulant field-effect transistor (MISFET).
Fig. 3 shows the low grid leakage current of the present invention, low current pull-in effect gallium nitride HEMT
Structure.
Fig. 4 A-4D shows the technological process of the gallium nitride HEMT device manufacturing the present invention.
Fig. 5 A-5E shows that a kind of of the present invention deforms: the grid structure of band field plate, and it manufactures
Technological process.
Fig. 6 shows a kind of deformation of the present invention: cutting, band field plate on AlGaN sealing coat
Grid structure.
Detailed description of the invention
The most just combine accompanying drawing each preferred embodiment of the present invention is described in detail.
Fig. 3 is gallium nitride enhancement mode field-effect tube structure of the present invention.The substrate 12 of growing gallium nitride material
It is usually Sapphire, SiC or silicon.Nucleating layer 13 grows on the substrate 12；On substrate 12 it is
GaN cushion 14；It is AlGaN sealing coat 15 on the buffer layer.Two Ohmic contact are formed respectively
The source electrode 22 of field effect transistor and drain electrode 23.Region between source electrode 22 and drain electrode 23, device surface
It is completely covered by SiN medium 32.Near the position on AlGaN surface in SiN medium, it is wrapped in
Double-deck grid structure.Upper strata is the metal gates 24 of conduction；Lower floor is SiO2Medium 33, and SiO2
Medium exists only under gate metal.Our this grid structure is called buried grid structure.
Reality is seen on the whole, is for 24 times two-layer complex media at metal gates.SiO2Layer upper,
It is close to gate metal, plays the effect reducing grid leakage current.This layer of SiO2Medium can be dropped by any
The medium of low electric leakage of the grid electric current substitutes.SiN layer under, directly contact with AlGaN layer, play table
The effect of face passivation, reduces and even eliminates current collapse effect.This layer of SiN medium can be dropped by any
The medium of low device current pull-in effect substitutes.This low grid leakage current and the nitridation of low current avalanche
Gallium HEMT has the characteristic that running voltage is high and switching speed is high, is particularly suitable for manufacturing microwave power and puts
Big amplifier and electric energy permutator device.
In order to increase the mutual conductance of device, grid 24 (is exactly two dimension from raceway groove in gallium nitride HEMT
Electron gas 2DEG position) distance should be the smaller the better.This just requires the metal gates of device of the present invention
Under the gross thickness of two-layered medium the smaller the better.In general, the SiN layer under metal gates should be 10
About nm, and SiO2Layer is 5～about 10nm.
Fig. 4 gives a kind of manufacturing process of device of the present invention.After forming Ohmic contact, first
Being the SiN about deposition a layer thickness 10nm, deposition a layer thickness 5～10nm is left immediately after
Right SiO2(Fig. 4 A).Next step is deposition gate metal (Fig. 4 B).Then with gate metal
For the mask of self-registered technology, etch away SiO by the method for dry etching2Layer, only retains grid gold
The SiO of subordinate2(Fig. 4 C).Due to SiO2Etching speed higher than the etching speed of SiN, this
Selective etching ratio is easier to control.Fraction of SiN over etching also can be made up at next step.
The final step of manufacturing process is the SiN surface passivation of whole device.The SiN of last deposition and
The SiN of deposition merges for the first time, by SiO2Layer and gate metal wrap up (Fig. 4 D).
A kind of deformation of the present invention is the grid of band field plate structure, as shown in fig. 5e.At plane form
In field-effect transistor, electric field can be gathered in the grid (Fig. 3) limit by drain directions of ordinary construction
Edge.And field plate structure can reduce the electric field in this position and concentrate, improve the use voltage of device,
And alleviate current collapse effect.The manufacturing process of this deformation is: after forming Ohmic contact, first
The first SiN about deposition a layer thickness 150nm, the then dry etching grooving of the position at grid,
Form the benchmark (Fig. 5 A) of field plate structure.Next step is the SiN about deposition a layer thickness 10nm,
Deposit the SiO of a layer thickness 5～about 10nm immediately after2(Fig. 5 B).Then deposition grid gold
Belong to, form field plate structure gate metal 24 (Fig. 5 C).Next step is with gate metal for autoregistration work
The mask of skill, etches away SiO by the method for dry etching2Layer, only retains the SiO under gate metal2
(Fig. 5 D).The final step of manufacturing process is the SiN surface passivation of whole device.Three depositions
SiN merges, by SiO2Layer and gate metal wrap up (Fig. 5 E).
The another kind of deformation of the present invention is the grid of also band field plate structure, but the cutting of field plate structure is deep
Enter in AlGaN sealing coat 15, as shown in Figure 6.Owing to gate metal 24 is from raceway groove (2DEG)
Distance than upper a kind of deformation device architecture closer to, be favorably improved the mutual conductance of device.This change
The manufacturing process of shape is basically identical, simply when field plate structure dry method cutting, at SiN with upper a kind of deformation
After layer has etched, continue etching AlGaN sealing coat 15 to certain degree of depth with chloro plasma.
Follow-up flow process is identical with upper a kind of deformation.
Although and being used for the HEMT device of the present invention by some exemplary embodiments above
The method manufacturing HEMT device is described in detail, but the above embodiment is not poor
Lifting, those skilled in the art can realize variations and modifications within the spirit and scope of the present invention.
Therefore, the present invention is not limited to these embodiments, and the scope of the present invention with appended claims is only
Accurate.
Claims (9)
1. a HEMT device, including:
Semiconductor layer on substrate；
Sealing coat on above-mentioned semiconductor layer；
The source electrode contacted with above-mentioned semiconductor layer and drain electrode；
The first medium layer on the whole region between above-mentioned source electrode and drain electrode on above-mentioned sealing coat；
And
Grid on above-mentioned first medium layer；
Wherein, above-mentioned grid is double-decker, and it is conductive layer at the middle and upper levels, and lower floor is second dielectric layer,
Above-mentioned second dielectric layer exists only under above-mentioned conductive layer, and above-mentioned first medium layer includes reducing device
The dielectric material of part current collapse effect, the fully wrapped around above-mentioned grid of above-mentioned first medium layer.
HEMT device the most according to claim 1, the most above-mentioned grid is intermediate portion
Divide the field plate structure gone out to above-mentioned convex semiconductor layer.
HEMT device the most according to claim 2, wherein has in above-mentioned sealing coat
The groove corresponding with the field plate structure of above-mentioned protrusion.
4. according to the HEMT device in any of the one of claim 1-3, the most above-mentioned half
Conductor layer includes GaN.
5. according to the HEMT device in any of the one of claim 1-3, the most above-mentioned
The thickness of one dielectric layer is 10nm.
HEMT device the most according to claim 5, the most above-mentioned first medium layer includes
SiN。
7. according to the HEMT device in any of the one of claim 1-3, the most above-mentioned
Second medium layer includes SiO2。
8. according to the HEMT device in any of the one of claim 1-3, the most above-mentioned every
Absciss layer includes AlGaN.
9., for the method manufacturing HEMT device, comprise the following steps:
Deposited semiconductor layer on substrate；
Layer deposited isolating on above-mentioned semiconductor layer；
Form the source electrode and drain electrode contacted with above-mentioned semiconductor layer；
On the whole region between above-mentioned source electrode and drain electrode on above-mentioned sealing coat, deposition can reduce device
The first medium layer of part current collapse effect；
Above-mentioned first medium layer deposits second dielectric layer；
Above-mentioned second dielectric layer is formed grid conductor；
Using above-mentioned grid conductor as mask, etch above-mentioned second dielectric layer, only retain above-mentioned grid and lead
Above-mentioned second dielectric layer under body, is made up of above-mentioned grid conductor and above-mentioned second dielectric layer with formation
Stacked gate；And
Deposit the material identical with first medium layer with above-mentioned grid fully wrapped around with above-mentioned first medium layer
Pole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310400284.9A CN103441144B (en) | 2007-06-06 | 2008-06-05 | HEMT device and manufacture method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200710018009.5 | 2007-06-06 | ||
| CN200710018009 | 2007-06-06 | ||
| CN2007100180095 | 2007-06-06 | ||
| CNA2008100986566A CN101320750A (en) | 2007-06-06 | 2008-06-05 | HEMT device and manufacturing method thereof |
| CN201310400284.9A CN103441144B (en) | 2007-06-06 | 2008-06-05 | HEMT device and manufacture method thereof |
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| CNA2008100986566A Division CN101320750A (en) | 2007-06-06 | 2008-06-05 | HEMT device and manufacturing method thereof |
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| CN103441144A CN103441144A (en) | 2013-12-11 |
| CN103441144B true CN103441144B (en) | 2016-09-14 |
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| CNA2008100986566A Pending CN101320750A (en) | 2007-06-06 | 2008-06-05 | HEMT device and manufacturing method thereof |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011024367A1 (en) | 2009-08-27 | 2011-03-03 | パナソニック株式会社 | Nitride semiconductor device |
| CN103026491B (en) * | 2010-07-06 | 2016-03-02 | 香港科技大学 | Normal turn-off type III-nitride metal-two-dimensional electron gas tunnel junctions field-effect transistor |
| CN107275287B (en) | 2011-12-19 | 2021-08-13 | 英特尔公司 | Group III-N transistors for system-on-a-chip (SOC) architecture with integrated power management and radio frequency circuitry |
| CN103311284B (en) * | 2013-06-06 | 2015-11-25 | 苏州晶湛半导体有限公司 | Semiconductor device and preparation method thereof |
| CN104113289B (en) * | 2014-06-05 | 2017-03-15 | 苏州能讯高能半导体有限公司 | A kind of microwave integrated amplifier circuit and preparation method thereof |
| CN104134689B (en) * | 2014-06-11 | 2018-02-09 | 华为技术有限公司 | A kind of HEMT device and preparation method |
| CN104167445B (en) * | 2014-08-29 | 2017-05-10 | 电子科技大学 | GaN-based enhancement/depletion mode heterojunction field effect transistor with buried gate structure |
| US11508821B2 (en) | 2017-05-12 | 2022-11-22 | Analog Devices, Inc. | Gallium nitride device for high frequency and high power applications |
| CN112368843A (en) * | 2018-07-06 | 2021-02-12 | 美国亚德诺半导体公司 | Composite device with rear field plate |
| CN115602723A (en) * | 2021-07-09 | 2023-01-13 | 长鑫存储技术有限公司（Cn） | Semiconductor structure and manufacturing method thereof |
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| JP2006173294A (en) * | 2004-12-15 | 2006-06-29 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
| CN1954440A (en) * | 2004-05-11 | 2007-04-25 | 美商克立股份有限公司 | Wide bandgap HEMTS with source connected field plates |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1954440A (en) * | 2004-05-11 | 2007-04-25 | 美商克立股份有限公司 | Wide bandgap HEMTS with source connected field plates |
| JP2006173294A (en) * | 2004-12-15 | 2006-06-29 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
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| CN101320750A (en) | 2008-12-10 |
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