CN1937249A - Aluminium gallium nitride/gallium nitride high electronic migration rate transistor and its manufacturing method - Google Patents
Aluminium gallium nitride/gallium nitride high electronic migration rate transistor and its manufacturing method Download PDFInfo
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- CN1937249A CN1937249A CN 200610096645 CN200610096645A CN1937249A CN 1937249 A CN1937249 A CN 1937249A CN 200610096645 CN200610096645 CN 200610096645 CN 200610096645 A CN200610096645 A CN 200610096645A CN 1937249 A CN1937249 A CN 1937249A
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Abstract
Duplex conflicts exist in current semiconductor device: high breakdown voltage but small transconductance; or large transconductance but low breakdown voltage. The disclosed high electron mobility transistor of nitride of aluminum gallium/ gallium nitride possesses advantages of both. The invention also discloses preparation method. The method includes steps and structures: the disclosed transistor includes channel layer, barrier layer as well as source pole and drain pole setup on the barrier layer; providing groove on the barrier layer between source pole and drain pole; quadrate or T type gate electrode is installed on groove covered by dielectric layer; function of dielectric layer is to reduce leakage current on gate electrode, and increase maximum current of device; function of groove is to raise transconductance of device. Advantages are: retaining large transconductance, small leakage current of gate electrode, and large drive current.
Description
Technical field
The present invention relates to a kind of semiconductor structure and manufacture method thereof, specifically a kind of aluminum gallium nitride/GaN high electron mobility transistor and manufacture method.
Background technology
At present, microwave system adopts the semiconductor solid-state device can effectively reduce system bulk, and improves reliability.Along with development of science and technology, various microwave applications system presses for and is applicable to high temperature, high frequency, high-power, radiation-resistant electronic device, all be very limited at aspects such as output power density, high temperature resistant and radioresistances based on the electronic device of conventional semiconductors such as Si and GaAs, thereby need to seek novel semiconductor material and substitute Si and GaAs etc.GaN belongs to the Wideband gap semiconductor material, on output power density, high temperature resistant and radioresistance, have sizable advantage with comparing based on its insulated gate aluminum gallium nitride compound (AlGaN)/gallium nitride (GaN) HEMT based on the device of Si and GaAs, people estimate that AlGaN/GaN HEMT will surpass the GaAs device by its power output capacity comprehensively in 2.5～30GHz frequency range, thereby AlGaN/GaN HEMT becomes the focus of research in the world in recent years.
People such as Khan (Khan et al.Applied Physics Letters, vol.63, no.9, pp.1214-1215,1993.) first AlGaN/GaNHEMT with DC characteristic disclosed in 1993, and in disclosing first AlGaN/GaN HEMT (Khan et al.Applied Physics Letters with microwave property, Vol.65, no.9, pp.1121-1123, Aug.1994.), after this research of AlGaN/GaN HEMT device is extensively carried out, and obtained progress at full speed.
People such as Wu (Wu et al.IEEE Electron Device Letters, vol.17, no.9, pp.455-457,1996.) first AlGaN/GaNHEMT device with microwave power output disclosed in 1996, device is 1.1W/mm in the 2GHz output power density.And then people (Green et al.IEEE Electron Device Lett. such as Green in 2000, Vol.21 no.6, pp.268-270,2000.) disclose and adopted the SiN passivating technique can suppress the current collapse of AlGaN/GaN HEMT effectively, for improving, device performance lays the foundation, device architecture such as MIS, field plate, grid grooving and technology obtain openly in succession after that, and in conjunction with passivating technique, the power output capacity of AlGaN/GaN HEMT has obtained further raising.At present, the output power density of disclosed small size AlGaN/GaN HEMT can reach above (the Wu et al.IEEE Electron Device Lett. of 30W/mm, Vol.25, No.3, pp.117-119,2004.), large-size device single-chip continuous wave output power has also reached above (the Nagy et al.IEEE MTT-S International Microwave Symposium Digest of 1OOW, pp.483-486,2005.), pulse power output even reached 368W (Therrien et al.IEEEIEDM Tech.Digest, pp.568-571,2005.)
The current collapse phenomenon of AlGaN/GaN HEMT is seriously restricting the device performance performance, generally adopt the SiN passivation to suppress current collapse at present on the technology, but the problem of bringing is that the leakage current on the device grid increases after the passivation.Consider on the material structure that people such as Kikkawa (Kikkawa et al.IEEE IEDM Tech.Digest, pp.585-588,2001.) disclose the effect that GaN cap layer also can well play the inhibition current collapse of introducing.Because the energy gap of GaN cap layer is than next little of AlGaN, the introducing of GaN cap layer will cause device to descend in the puncture voltage after the passivation manyly causing that in other words the leakage current on the device grid further increases, particularly work as GaN cap layer and be under the state of doping.Device electric breakdown strength descends then, and device corresponding work voltage makes the dynamic range of device under the microwave operating state reduce, thereby has reduced the microwave power fan-out capability of device also with regard to reducing; The also reliability of unfavorable device of the increase of leakage current on the grid simultaneously.
In order to reduce leakage current, the raising puncture voltage on the device grid, just be necessary under the device grid, to introduce dielectric layer and make insulated gate AlGaN/GaN HEMT with high breakdown field strength.With reference to Figure 1 shows that a kind of insulated gate AlGaN/GaN HEMT structure commonly used, this HEMT comprises semi-insulation SiC substrate 1, on substrate, pass through metallo-organic compound chemical vapor deposition (MOCVD) or the epitaxially grown AlN resilient coating 2 of other suitable epitaxy methods, GaN resistive formation 3 and AlGaN barrier layer 4 successively, be produced on the source ohmic contact 5 on the barrier layer 4 and leak ohmic contact 6, in the source ohmic contact and leak the dielectric layer 51 between the ohmic contact and be produced on metal gate 8 on the dielectric layer.
It is SiO that people such as Khan (Khan et al.Appl.Phys.Letters, Vol.77, p.1339,2000) disclose figure medium layer
2Insulated gate AlGaN/GaN HEMT.With reference to Fig. 1, in the process of this HEMT of preparation, dielectric layer 51 is SiO
2, and using plasma chemical gas-phase deposition enhanced (PECVD) method obtains.
People such as Hu (Hu et al.Appl.Phys.Letters, Vol.79, p.2832,2000) disclose Fig. 1 medium layer 51 and have been the insulated gate AlGaN/GaN HEMT of silicon nitride (SiN).With reference to Fig. 1, the SiN dielectric layer 51 same PECVD deposition process that adopt of this HEMT obtain.
People such as Ye (Ye et al.Appl.Phys.Letters, Vol.86, p.2832,2005) disclose Fig. 1 medium layer 51 and have been the alundum (Al (Al of atomic layer deposition fabrication techniques
2O
3) insulated gate AlGaN/GaN HEMT.With reference to Fig. 1, in the process of this HEMT of preparation, dielectric layer 51 obtains by the following method: utilize atomic layer deposition technology deposit one deck Al on the AlGaN/GaN heterojunction material that is obtained by the MOCVD growth
2O
3 Dielectric layer 51, and then the 60s that under 600 ℃, oxygen atmosphere, anneals.Al is finished in deposit
2O
3The making of just carrying out source ohmic contact 5 behind the dielectric layer 51, leaking ohmic contact 6 and metal gate 8, wherein source ohmic contact 5, leak in ohmic contact 6 manufacturing process need to increase extra photoetching, etch step is exposed barrier layer 4 with the dielectric layer of removing under it 51.
Introduce dielectric layer 51 in the device 1 between metal gate 8 and the barrier layer 4 and reduced leakage current on the metal gate 8 with high breakdown field strength, improved puncture voltage accordingly, but disadvantageous one side is the threshold voltage that has improved device, just reduced the mutual conductance of device, this will influence the frequency characteristic of device.
Summary of the invention
The objective of the invention is the breakdown voltage resistant height that exists at the conventional semiconductor device but mutual conductance is little or the big and breakdown voltage resistant low dual contradiction of mutual conductance, invent a kind of aluminum gallium nitride/GaN high electron mobility transistor that has the two advantage concurrently, provide its manufacture method simultaneously.
Technical scheme of the present invention is:
A kind of aluminum gallium nitride/GaN high electron mobility transistor comprises:
One from sapphire, Si and SiC, select a kind of as substrate 1,
One is positioned at the resilient coating 2 on the described substrate 1,
One is positioned at the gallium nitride channel layer 3 on the described resilient coating 2,
The one aluminum gallium nitride barrier layer 4 that on described channel layer 3, forms,
The source electrode 5 and the drain electrode 6 that on barrier layer 4, form, the spacing between source electrode 5 and the drain electrode 6 is the 2-5 micron,
It is characterized in that: on the barrier layer 4 between described source electrode 5 and the drain electrode 6, be provided with a groove 7, in described groove 7, gate electrode be installed, described gate electrode or be square gate electrode 8, or be T type gate electrode 12; When the gate electrode of installing in the groove 7 is square gate electrode 8, its lower end is stretched in the described groove 7, its upper end projection is on the highest face temperature of dielectric layer 9, and the coverage of described dielectric layer 9 comprises the bottom surface of the upper surface of the barrier layer 4 between source electrode 5 and the drain electrode 6 with groove 7; When the gate electrode of installing in the groove 7 is T shape gate electrode 8, its perpendicular shape lower end is stretched in the described groove 7, its horizontal shape upper end projection is on dielectric layer 18, described dielectric layer 18 is arranged in groove 7, its top is positioned on the dielectric layer 13, and dielectric layer 13 is on the barrier layer 4 except groove 7 parts between source electrode 5 and the drain electrode 6.
On described dielectric layer 9, be provided with the dielectric layer 11 that barrier layer 4 expose portions can be covered.
When described dielectric layer 18 does not cover or partly cover on the dielectric layer 13, on described dielectric layer 13, be provided with the dielectric layer 19 that barrier layer 4 expose portions can be covered, when on the described dielectric layer 18 complete blanket dielectric layer 13, on described dielectric layer 13, be provided with the dielectric layer 20 that barrier layer 4 expose portions can be covered.
Described dielectric layer 9,11,13,18,19,20 is any in silicon nitride, aluminium nitride, silicon dioxide or the alundum (Al, and its thickness is 5-15nm.
The thickness of described barrier layer 4 is between 15-50nm.
The lower end of described T shape gate electrode 12 is biased in the described groove 7, and its side 14 and side 15 spacings are less than 0.5 micron, and side 16 is 0.5～1.5 micron with side 17 spacings, and promptly the lateral separation of the horizontal shape protruding two side faces in upper end of gate electrode and its lower end is respectively recently less than 0.5 micron and 0.5～1.5 micron.
According to the difference of gate electrode, method of the present invention has two kinds, and is as follows respectively:
One, a kind of manufacturing has the method for the aluminum gallium nitride/GaN high electron mobility transistor of square gate electrode, it is characterized in that it may further comprise the steps:
---on substrate 1, adopt MOCVD or RF-MBE method to form resilient coating 2, GaN channel layer 3 and AlGaN barrier layer 4 successively;
---on barrier layer 4, form first ohmic contact regions 5 as the source electrode;
---on barrier layer 4, form second ohmic contact regions 6 as drain electrode at a distance of the place of 2-5 micron with first ohmic contact regions;
---on the barrier layer between source electrode and the drain electrode 4, utilize the method for dry method or wet etching to form a groove 7;
---deposit one dielectric layer 9 on the barrier layer 4 between source electrode 5 and the drain electrode 6, the deposition process of dielectric layer 9 includes but not limited to any among sputter, electron beam evaporation, the plasma reinforced chemical vapor deposition PECVD;
---form gate electrode 8 on dielectric layer 9, gate electrode 8 is positioned at the folded space of parallel plane at 7 two sidewall places of groove.
Said method also comprise in case of necessity utilize identical method on dielectric layer 9 again deposit one deck cover the dielectric layer 11 of barrier layer 4 expose portions.
Two, a kind of method of making the aluminum gallium nitride/GaN high electron mobility transistor of T shape gate electrode is characterized in that it may further comprise the steps:
---on substrate 1, adopt MOCVD or RF-MBE method to form resilient coating 2, GaN channel layer 3, AlGaN barrier layer 4 successively;
---on barrier layer 4, form first ohmic contact regions 5 as the source electrode;
---on barrier layer 4, form second ohmic contact regions 6 as drain electrode at a distance of the place of 2-5 micron with first ohmic contact regions;
---on the barrier layer between source electrode and the drain electrode 4, utilize the method for dry method or wet etching to form a groove 7;
---deposit one dielectric layer 13 on the surface of barrier layer 4 except that groove 7 between source electrode 5 and drain electrode 6, the deposition process of dielectric layer 13 includes but not limited to sputter, electron beam evaporation, plasma reinforced chemical vapor deposition PECVD;
---deposit one dielectric layer 18 on dielectric layer 13 and groove 7, the deposition process of dielectric layer 18 includes but not limited to sputter, electron beam evaporation or plasma reinforced chemical vapor deposition PECVD;
---form T-shape gate electrode 12 on dielectric layer 18, two sides 15,16 of gate electrode 12 are positioned at the folded space of parallel plane at 7 two sidewall places of groove.
Said method also comprises in case of necessity and utilizes dielectric layer 19 that identical method can cover the expose portion on the barrier layer 4 in deposit one on the dielectric layer 13 or the dielectric layer 20 that the expose portion on the barrier layer 4 can be covered in deposit one on the dielectric layer 18.
In brief, one aspect of the present invention provides a kind of groove insulated gate aluminum gallium nitride compound/gallium nitride HEMT.This HEMT comprises: from sapphire, that selects among Si and the SiC is a kind of as substrate, be formed on the resilient coating that constitutes by the III group-III nitride on the substrate, the III group iii nitride layer (being referred to as " barrier layer ") that the one deck of growing has wideer energy gap is gone up and gone up to the III group iii nitride layer (being referred to as " channel layer ") that has the high resistant characteristic on the resilient coating, be produced on first ohmic contact regions on the barrier layer as the source electrode, second ohmic contact regions that is produced on the barrier layer and separates with first ohmic contact regions is as drain electrode, the groove that on the barrier layer between source electrode and the drain electrode, forms, cover the medium on the barrier layer between source electrode and the drain electrode, on medium and be right against the gate electrode of groove, gate electrode and dielectric layer, barrier layer forms sandwich structure.
The present invention provides a kind of manufacture method of groove insulated gate aluminum gallium nitride compound/gallium nitride HEMT on the other hand.This method may further comprise the steps: adopt as any suitable growing method such as MOCVD, RF-MBE on substrate successively epitaxial growth obtain resilient coating, GaN channel layer and the barrier layer of device, and the band gap of barrier layer is greater than the GaN channel layer, add stronger spontaneous polarization of III group-III nitride self and piezoelectric polarization effect, will have highdensity two-dimensional electron gas in the near interface formation of heterojunction material like this.Substrate is any one among sapphire, Si and the SiC, preferably, adopts semi-insulated 4H-SiC and semi-insulated 6H-SiC as substrate, and the selection of resilient coating is relevant with backing material, and barrier layer is generally the Al of band gap greater than the GaN channel layer
XGa
1-xN (0＜x＜1), about 15 nanometers of its thickness are to 50 nanometers.
On barrier layer, provide two to have at a distance of 2 microns to 5 microns ohmic contact regions respectively as the source Ohm contact electrode and leak Ohm contact electrode, on the barrier layer between source Ohm contact electrode and the leakage Ohm contact electrode, adopt the method for dry method or wet etching to form a rectangular recess, the distance of the two sides of recess width, groove and source Ohm contact electrode and leakage Ohm contact electrode depends on the purposes of made device, and the degree of depth of groove depends on the thickness of barrier layer.
Groove completes, and deposit one deck 5 nanometers are to the dielectric material of 15 nano thickness on the barrier layer between source Ohm contact electrode and the leakage Ohm contact electrode in the back, and selectable dielectric material includes but not limited to aluminium nitride (AlN), silicon nitride (SiN), silica (SiO
2) and alundum (Al (Al
2O
3) in a kind of, the method for dielectric deposition includes but not limited to sputter, electron beam evaporation, plasma reinforced chemical vapor deposition (PECVD).On dielectric layer, make metal gate electrode afterwards, make barrier layer, dielectric layer and metal gate electrode form sandwich structure, finish the making of groove insulated gate aluminum gallium nitride compound/gallium nitride HEMT.
The present invention has the following advantages:
One aspect of the present invention has been inherited the advantage that traditional insulated gate structure device has little gate leakage current, high puncture voltage and bigger current driving ability, increase the dynamic range of device under microwave signal drives, thereby improved device microwave power fan-out capability.Again by setting up the notched gates structure,, gain on the other hand, improve the device frequency characteristic thereby improve the device microwave power to remedy the reduction that introducing oxide skin(coating) or insulating barrier cause the device mutual conductance.Method proposed by the invention has simple, practical advantage.
Description of drawings
Fig. 1 is the profile of conventional insulated gate AlGaN/GaN HEMT;
Fig. 2 is one of structural representation of the present invention;
Fig. 3 is the AlGaN/GaN HEMT surface profile of deposit one dielectric layer again among Fig. 2;
Fig. 4 A-4C is the manufacture process schematic diagram of the HEMT of Fig. 2 structure;
The situation of Fig. 5 A-5B gate electrode misalignment that may exist of the present invention;
Fig. 6 is two of a structural representation of the present invention;
Fig. 7 is the AlGaN/GaN HEMT surface profile of deposit one dielectric layer again among Fig. 6;
Fig. 8 is three of a structural representation of the present invention;
Fig. 9 is the AlGaN/GaN HEMT surface profile of deposit one dielectric layer again among Fig. 8;
Figure 10 A-10D is the manufacture process schematic diagram of the HEMT of Fig. 2 of the present invention and/or Fig. 3 structure.
Embodiment
The present invention is further illustrated for following structure drawings and Examples.
Embodiment one.
Fig. 2 is a device 32 of embodiments of the invention.1 is substrate in the device 32, and 2 is resilient coating, and 3 is the GaN channel layer, and 4 is Al
XGa
1-xN (0＜x＜1) barrier layer.Substrate 1 is any one among sapphire, Si and the SiC, preferably, adopt semi-insulated 4H-SiC (0001) and semi-insulated 6H-SiC (0001) as substrate, they have the thermal conductivity height, with characteristics such as the GaN lattice mismatch is little, not only be easy to the GaN epitaxial material of growing high-quality, also help simultaneously the heat radiation of device, the Cree company of the present U.S. and the SiC substrate that all there are 4H and two kinds of forms of 6H in II-VI company are sold.Resilient coating 2 is mainly used to as transitional function between substrate and channel layer, because the stress that channel layer and substrate lattice mismatch are introduced, choosing of resilient coating is relevant with backing material to reduce, and this is well known in the art, and is not described further.Channel layer 3 is the GaN layer, and its thickness is about 1 micron.The component x of aluminium is preferably between 0.15 to 0.3 in the barrier layer 4, thickness is preferably 15 nanometers to 30 nanometers, because the band gap of barrier layer 1 is greater than channel layer 3, so at the two-layer sheet charged region that will occur at the interface, all electronics have been formed a two-dimensional electron gas in this sheet charge district, sometimes for increasing two-dimensional electron gas at the interface, can barrier layer 4 be mixed, the doping content maximum is about 4 * 10
18Cm
-3Resilient coating 2, channel layer 3, barrier layer 4 for adopt MOCVD, RF-MBE or other any suitable growing methods successively on substrate 1 epitaxial growth obtain, its concrete growth course can be with reference to pertinent literature.
On barrier layer, provide Ohm contact electrode 5 as the source electrode, Ohm contact electrode 6 is as drain electrode, source electrode 5 and drain electrode 6 can be that Ti/Al/Ni/Au, Ti/Al/Mo/Au, Ti/Al/Ti/Au or any other can form the suitable material of ohmic contact with barrier layer, metal on source electrode 5 and the drain electrode 6 preferably adopts electron beam evaporation to form, and, in the short annealing process, need nitrogen (N under 780 ℃ to the 900 ℃ high temperature about short annealing 30s
2) or the metal of any other suitable inert gas shielding source electrode 5 and drain electrode 6 not oxidized.As previously mentioned, the spacing of source electrode 5 and drain electrode 6 is generally 2 microns to 5 microns.
On the barrier layer between source Ohm contact electrode and the leakage Ohm contact electrode, provide a groove 7, the formation of groove 7 can be adopted the method for dry method or wet etching, preferred lithographic method is a dry etching, comprise reactive ion etching (RIE) and inductively coupled plasma etching (ICP), method and principle for dry etching III group-III nitride are well-known, here repeat no more, specifically can be referring to people's such as Egawa document (Egawa et al.Appl.Phys.Lett., vol.76, pp.121-123,2000) or people's such as Coffie document (Coffie et al.Applied Physics Letters Vol.83, p.4779,2003).The distance and the recess width of the distance of groove source sidewall and source electrode, leakage side sidewall and drain electrode are decided according to the actual requirements, and depend on the precision that photoetching can reach in the manufacturing, as previously mentioned, depth of groove depends on barrier layer thickness, preferably makes groove lower barrierlayer thickness remain 8 nanometers to 20 nanometers.
At surface deposition one deck dielectric layer 9 that barrier layer 4 exposes, the spendable material of dielectric layer includes but not limited to aluminium nitride (AlN), silicon nitride (SiN), silica (SiO
2) and alundum (Al (Al
2O
3) in a kind of, the method for dielectric layer 9 deposits includes but not limited to sputter, electron beam evaporation, plasma reinforced chemical vapor deposition (PECVD), preferably adopts the electron beam evaporation deposition technology.Thickness of dielectric layers is preferably 5 nanometers as previously mentioned to 15 nanometers.
Fig. 4 A-4C is some embodiments of present embodiment, is included in to form groove 7 on the barrier layer and utilize self-aligned technology to form dielectric layer 9 and grid metal 8 on groove.As previously mentioned, on substrate 1, adopt MOCVD, RF-MBE or other any suitable growing methods epitaxial growth formation resilient coating 2, channel layer 3 and barrier layer 4 successively, on barrier layer 4, form source Ohm contact electrode 5 and leak Ohm contact electrode 6.
Groove on the barrier layer is carried out composition, so that etching forms groove 7.Shown in Fig. 4 A, form mask 41 on the surface of device, so that the place that device is not needed to form groove is protected, mask 41 preferable material are photoresist, its thickness is about 2 microns, so that play the effect that stops etching; Shown in Fig. 4 B, utilize foregoing lithographic method that barrier layer 4 is carried out etching, and make that groove 7 lower barrierlayer residual thickness are that 8 nanometers are to 20 nanometers.
After groove 7 etchings form,, remove mask 41 as Fig. 4 C, and surface deposition one dielectric layer 9 that exposes at barrier layer 4, optionally the dielectric layer material includes but not limited to aluminium nitride (AlN), silicon nitride (SiN), silica (SiO
2) and alundum (Al (Al
2O
3) in a kind of, the method for dielectric layer deposited 9 preferably adopts the method for electron beam evaporation, with the thickness of accurate control medium layer 9, the thickness of dielectric layer 9 is that 5 nanometers are to 15 nanometers as previously mentioned.Use conventional technology on dielectric layer 9, to form grid metal 8, because at groove, grid metal is not to adopt self-registered technology to form, thereby deviation might take place, shown in Fig. 5 A-5B, make having covered beyond the groove of grid metal part, trickle deviation will can not produce big influence to the function of device, but big deviation is disadvantageous to device.
For protection device, sometimes as shown in Figure 3 on device 32 surfaces again 11 pairs of devices of deposit one deck dielectric layer carry out passivation and form device 33, dielectric layer 11 comprises aluminium nitride (AlN), silicon nitride (SiN), silica (SiO
2) and alundum (Al (Al
2O
3) in a kind of, the method for its deposit comprises sputter, electron beam evaporation, plasma reinforced chemical vapor deposition (PECVD).
In brief, the manufacture method of present embodiment may further comprise the steps:
---on substrate 1, adopt MOCVD or RF-MBE method to form resilient coating 2, GaN channel layer 3 and AlGaN barrier layer 4 successively;
---on barrier layer 4, form first ohmic contact regions 5 as the source electrode;
---on barrier layer 4, form second ohmic contact regions 6 as drain electrode at a distance of the place of 2-5 micron with first ohmic contact regions;
---on the barrier layer between source electrode and the drain electrode 4, utilize the method for dry method or wet etching to form a groove 7;
---deposit one dielectric layer 9 on the barrier layer 4 between source electrode 5 and the drain electrode 6, the deposition process of dielectric layer 9 includes but not limited to any among sputter, electron beam evaporation, the plasma reinforced chemical vapor deposition PECVD;
---form gate electrode 8 on dielectric layer 9, gate electrode 8 is positioned at the folded space of parallel plane at 7 two sidewall places of groove.
Said method also comprise in case of necessity utilize identical method on dielectric layer 9 again deposit one deck cover the dielectric layer 11 of barrier layer 4 expose portions.
Embodiment two.
Fig. 6 is the device 34 of the band T-shape grid of one embodiment of the present of invention.Be similar to the device 32 among Fig. 2, device 34 has substrate 1, resilient coating 2, GaN channel layer 3 and AlGaN barrier layer 4.Device 34 also has with device 32 and is positioned at source electrode 5 and drain electrode 6 on the barrier layer, the surface of device 34 is all covered by dielectric layer 13 except that groove 7, bottom portion of groove and sidewall are covered by dielectric layer 18, dielectric layer 18 extends and covers on the dielectric layer 13 to source electrode 5 and drain electrode 6 at device surface, 18 of dielectric layers are present under the gate electrode 12, and the gate electrode 12 of device is T-shape grid structures.Sidewall 14 and 15 distance be less than 0.5 micron in the T-shape grid 12, sidewall 16 and 17 distance are about 1 micron, and promptly T-shape grid 12 are not symmetry fully, and this asymmetric T-shape grid structure is that to improve the AlGaN/GaNHEMT performance needed.
Deposit one deck dielectric layer 13 is with the required T-shape grid of convenient formation on the expose portion of barrier layer 4, dielectric layer 13 preferred dielectric materials are SiN, it has been proved to be able to the current collapse phenomenon that suppression device surface state effectively causes, and the thickness of dielectric layer 10 is preferably more than the 100nm.
The forming process of groove 7 is shown in Figure 10 A-10B.Shown in Figure 10 A, form mask 42 on the surface of device, so that the place that device is not needed to form groove is protected, mask 42 preferable material are photoresist, its thickness is about 2 microns, so that play the effect that stops etching; Shown in Figure 10 B, at first be the etching dielectric layer, be known for the lithographic method of SiN dielectric material, no longer describe in detail herein, utilize foregoing lithographic method that barrier layer 4 is carried out etching to form groove 7 then.
The formation of dielectric layer 18 and T-shape grid 12 is shown in Figure 10 C-10D.Shown in Figure 10 C, remove mask 42 and form mask 43 at device surface, the place that does not need dielectric layer deposited 13 is protected.Shown in Figure 10 D, whole surface deposition one dielectric layer 13 at device, optionally the dielectric layer material as previously mentioned, the method of dielectric layer deposited 13 preferably adopts the method for electron beam evaporation, so that the enforcement of the stripping technology that carries out thereafter, the thickness of dielectric layer 13 be as previously mentioned 5 nanometers to 15 nanometers, optionally the dielectric layer material includes but not limited to aluminium nitride (AlN), silicon nitride (SiN), silica (SiO
2) and alundum (Al (Al
2O
3) in a kind of.In the dielectric layer deposition process, dielectric layer 13 has also covered on the mask 43 simultaneously.After dielectric layer 13 deposits are finished, utilize the electron beam evaporation deposition technology, whole surface deposition one deck grid metal 12 at device, in grid metal 12 deposition processs, grid metal 12 has also covered on the dielectric layer 13 that is positioned on the mask 43 simultaneously, and the thickness summation of the thickness of grid metal 12 and dielectric layer 13 should guarantee to be lower than half of mask 43 thickness.Utilize at last stripping technology with mask 43 and on dielectric layer 13 grid metals 12 remove, obtain device 36.
As shown in Figure 6, sometimes for protection device on device 34 surfaces again 19 pairs of deposit one deck dielectric layers carry out passivation and form device 35, optionally the dielectric layer material comprises aluminium nitride (AlN), silicon nitride (SiN), silica (SiO
2) and alundum (Al (Al
2O
3) in a kind of, the method for deposit comprises sputter, electron beam evaporation, plasma reinforced chemical vapor deposition (PECVD).
In brief, the transistorized manufacture method of T type structure mainly may further comprise the steps:
---on substrate 1, adopt MOCVD or RF-MBE method to form resilient coating 2, GaN channel layer 3, AlGaN barrier layer 4 successively;
---on barrier layer 4, form first ohmic contact regions 5 as the source electrode;
---on barrier layer 4, form second ohmic contact regions 6 as drain electrode at a distance of the place of 2-5 micron with first ohmic contact regions;
---on the barrier layer between source electrode and the drain electrode 4, utilize the method for dry method or wet etching to form a groove 7;
---deposit one dielectric layer 13 on the surface of barrier layer 4 except that groove 7 between source electrode 5 and drain electrode 6, the deposition process of dielectric layer 13 includes but not limited to sputter, electron beam evaporation, plasma reinforced chemical vapor deposition PECVD;
---deposit one dielectric layer 18 on dielectric layer 13 and groove 7, the deposition process of dielectric layer 18 includes but not limited to sputter, electron beam evaporation or plasma reinforced chemical vapor deposition PECVD;
---form T-shape gate electrode 12 on dielectric layer 18, two sides 15,16 of gate electrode 12 are positioned at the folded space of parallel plane at 7 two sidewall places of groove.
Said method also comprises in case of necessity and utilizes dielectric layer 19 that identical method can cover the expose portion on the barrier layer 4 in deposit one on the dielectric layer 13 or the dielectric layer 20 that the expose portion on the barrier layer 4 can be covered in deposit one on the dielectric layer 18
Embodiment three.
Fig. 8 is the device 36 of band T-shape grid of an alternative embodiment of the invention.With the device among the embodiment of front, device 36 has substrate 1, resilient coating 2, GaN channel layer 3 and AlGaN barrier layer 4, is positioned at source electrode 5 and drain electrode 6 on the barrier layer, the surface of device 36 is covered by dielectric layer 13 except that groove 7,18 of dielectric layers not only are present in the expose portion that has also covered dielectric layer 13 under the grid metal simultaneously, and the gate electrode 12 of device 36 equally is a T-shape grid structure with device 34. Same sidewall 14 and 15 distance be less than 0.5 micron, and sidewall 16 and 17 distance are about 1 micron, with the performance of raising AlGaN/GaNHEMT.
The formation of resilient coating 2, GaN channel layer 3 and AlGaN barrier layer 4, source electrode 5 and drain electrode 6 is with front embodiment, the forming process of groove 7 shown in Figure 10 A-10B, identical in method and the device 34.
After 7 formation of the groove among Figure 10 B, the mask 42 of device surface is removed, dielectric layer 18 is deposited to the surface that barrier layer 4 exposes, optionally dielectric material is with device 34, the method of dielectric layer deposited 18 preferably adopts the method for sputter, so that the side to groove forms good covering, the thickness of dielectric layer 18 is that 5 nanometers are to 15 nanometers.Use conventional technology on dielectric layer 18, to form grid metal 12, because at groove, grid metal is not to adopt self-registered technology to form, thereby equally deviation might take place with device 32, same trickle deviation will can not produce big influence to the function of device, but big deviation is disadvantageous to device.
Deposit one deck dielectric layer 20 carries out passivation on the surface to device and forms device 37 more as shown in Figure 9, and optionally the dielectric layer material comprises aluminium nitride (AlN), silicon nitride (SiN), silica (SiO
2) and alundum (Al (Al
2O
3) in a kind of, the method for deposit comprises sputter, electron beam evaporation, plasma reinforced chemical vapor deposition (PECVD).
Manufacture method can be carried out with reference to embodiment two.
The part that the present invention does not describe in detail is all same as the prior art.
Claims (11)
1, a kind of aluminum gallium nitride/GaN high electron mobility transistor comprises:
One substrate (1),
One is positioned at the resilient coating (2) on the described substrate (1),
One is positioned at the gallium nitride channel layer (3) on the described resilient coating (2),
One at the last aluminum gallium nitride barrier layer (4) that forms of described channel layer (3),
Go up source electrode (5) and the drain electrode (6) that forms at barrier layer (4), the spacing between source electrode (5) and the drain electrode (6) is the 2-5 micron,
It is characterized in that: on the barrier layer (4) between described source electrode (5) and the drain electrode (6), be provided with a groove (7), in described groove (7), gate electrode be installed, described gate electrode or be square gate electrode (8), or be T type gate electrode (12); When the gate electrode of installing in the groove (7) is square gate electrode (8), its lower end is stretched in the described groove (7), and the coverage of described dielectric layer (9) comprises the bottom surface of the upper surface and the groove (7) of the barrier layer (4) between source electrode (5) and the drain electrode (6); When the gate electrode of installing in the groove (7) is T shape gate electrode (8), its perpendicular shape lower end is stretched in the described groove (7), its horizontal shape upper end projection is on dielectric layer (18), described dielectric layer (18) is arranged in groove (7), its top is positioned on the dielectric layer (13), and dielectric layer (13) is positioned on the barrier layer (4) except groove (7) part between source electrode (5) and the drain electrode (6).
2, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1 is characterized in that being provided with the dielectric layer (11) that barrier layer (4) expose portion can be covered on described dielectric layer (9).
3, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1, it is characterized in that when described dielectric layer (18) does not cover or partly cover on the dielectric layer (13), on described dielectric layer (13), be provided with the dielectric layer (19) that barrier layer (4) expose portion can be covered, when the complete blanket dielectric layer (13) of described dielectric layer (18) goes up, on described dielectric layer (13), be provided with the dielectric layer (20) that barrier layer (4) expose portion can be covered.
4, according to claim 1,2 or 3 described aluminum gallium nitride/GaN high electron mobility transistors, it is characterized in that described dielectric layer (9,11,13,18,19,20) be in silicon nitride, aluminium nitride, silicon dioxide or the alundum (Al any, its thickness is 5-15nm.
5, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1, the thickness that it is characterized in that described barrier layer (4) is between 15-50nm.
6, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1, the lower end that it is characterized in that described T shape gate electrode (12) is biased in the described groove (7), and its side (14) and side (15) spacing are less than 0.5 micron, and side (16) are 0.5～1.5 micron with side (17) spacing.
7, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1, wherein substrate (1) is any among SiC, sapphire or the Si.
8, a kind of described method that has the aluminum gallium nitride/GaN high electron mobility transistor of square gate electrode of claim 1 of making is characterized in that it may further comprise the steps:
---upward adopt MOCVD or RF-MBE method to form resilient coating (2), GaN channel layer (3) and AlGaN barrier layer (4) successively at substrate (1);
---go up formation first ohmic contact regions (5) as the source electrode at barrier layer (4);
---upward form second ohmic contact regions (6) as drain electrode at a distance of the place of 2-5 micron at barrier layer (4) with first ohmic contact regions;
---on the barrier layer between source electrode and the drain electrode (4), utilize the method for dry method or wet etching to form a groove (7);
---the barrier layer (4) between source electrode (5) and drain electrode (6) is gone up deposit one dielectric layer (9), and the deposition process of dielectric layer (9) includes but not limited to any in sputter, electron beam evaporation, the plasma reinforced chemical vapor deposition (PECVD);
---go up formation gate electrode (8) at dielectric layer (9), gate electrode (8) is positioned at the folded space of parallel plane at (7) two sidewall places of groove.
9, manufacturing according to claim 8 has the method for the aluminum gallium nitride/GaN high electron mobility transistor of square gate electrode, it is characterized in that it also comprise utilize identical method on dielectric layer (9) again deposit one deck cover the dielectric layer (11) of barrier layer (4) expose portion.
10, a kind of method of making the aluminum gallium nitride/GaN high electron mobility transistor of the described T of the having shape of claim 1 gate electrode is characterized in that it may further comprise the steps:
---upward adopt MOCVD or RF-MBE method to form resilient coating (2), GaN channel layer (3), AlGaN barrier layer (4) successively at substrate (1);
---go up formation first ohmic contact regions (5) as the source electrode at barrier layer (4);
---upward form second ohmic contact regions (6) as drain electrode at a distance of the place of 2-5 micron at barrier layer (4) with first ohmic contact regions;
---on the barrier layer between source electrode and the drain electrode (4), utilize the method for dry method or wet etching to form a groove (7);
---deposit one dielectric layer (13) on the surface of barrier layer (4) except that groove (7) between source electrode (5) and drain electrode (6), the deposition process of dielectric layer (13) includes but not limited to sputter, electron beam evaporation, plasma reinforced chemical vapor deposition (PECVD);
---go up deposit one dielectric layer (18) at dielectric layer (13) and groove (7), the deposition process of dielectric layer (18) includes but not limited to sputter, electron beam evaporation or plasma reinforced chemical vapor deposition (PECVD);
---go up formation T-shape gate electrode (12) at dielectric layer (18), two sides (15,16) of gate electrode (12) are positioned at the folded space of parallel plane at (7) two sidewall places of groove.
11, manufacturing according to claim 10 has the method for the aluminum gallium nitride/GaN high electron mobility transistor of T shape gate electrode, it is characterized in that it comprises that also utilizing identical method to go up deposit one at dielectric layer (13) can go up the dielectric layer (20) that deposit one can cover the expose portion on the barrier layer (4) with the dielectric layer (19) of the covering of the expose portion on the barrier layer (4) or at dielectric layer (18).
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