JP3350426B2 - Method for manufacturing heterojunction bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a heterojunction bipolar transistor (hereinafter referred to as "HBT"), and more particularly, to a method suitable for application to a low power consumption circuit, having a fine transistor dimension, and having a high reliability. H with excellent high frequency characteristics
The present invention relates to a BT manufacturing method.

[0002]

2. Description of the Related Art An HBT uses a semiconductor material having a band gap larger than that of a base for an emitter, so that a large current amplification factor can be obtained without lowering the emitter injection efficiency even when the impurity concentration of the base is increased. Therefore, there are many advantages, such as a low base resistance, which are advantageous for improving the performance of the transistor.

[0003] In particular, when a III-V compound semiconductor material is used, its excellent electron transporting properties, the selection of materials, the combination of heterojunctions can be expanded, and not only electronic devices but also optical devices can be integrated. The advantages, such as being, increase.

An HBT using a compound semiconductor is generally
A target semiconductor layer is epitaxially grown on a semi-insulating semiconductor substrate having a (100) plane as a main surface, a mesa structure is formed by etching, and an emitter layer, a base layer,
It is manufactured by forming an ohmic contact electrode on each of the collector layers.

In order to reduce the parasitic resistance and the parasitic capacitance of the HBT to increase the speed, and to achieve high integration and low power consumption, it is necessary to miniaturize the transistor dimensions. Self-aligned HBTs are advantageous.
In the manufacturing process of the self-aligned HBT, an undercut region is formed by side-etching the semiconductor layer forming the emitter with respect to the emitter electrode, and a base electrode forming metal is formed from above on the region including the emitter electrode. There is a process of forming an emitter and a base electrode simultaneously and separately by electron beam evaporation. This is widely used because the distance between the emitter mesa region having a fine dimension and the base electrode can be reduced as much as possible and the parasitic base resistance can be greatly reduced.

The simplest method of introducing side etching into the semiconductor layer forming the emitter with respect to the emitter electrode is to perform side etching by selective wet etching on the emitter contact layer and the emitter layer using the emitter electrode as an etching mask. . Generally, Ga
When a compound semiconductor centering on As or InP is etched by a wet etching method, the etching rate and the etching cross-sectional shape greatly differ depending on the crystal plane orientation, and the etching cross-sectional shape is a trapezoidal forward mesa shape and an inverted trapezoidal shape (upper bottom). Is longer than the lower bottom).

In the self-alignment step of performing side etching of the emitter contact layer and the emitter layer by using the emitter electrode as a mask to form an undercut region, and depositing a base electrode forming metal on the undercut region by electron beam vapor deposition, an inverted mesa sectional shape is formed. Since the emitter / base electrode is separated by the minimum necessary amount of side etching,
The etching time is short, and the reproducibility and the uniformity within the wafer surface are excellent. Also, since the amount of side etching is small,
The adhesion area between the emitter electrode material serving as an etching mask and the emitter contact semiconductor layer is also improved, and a high yield can be realized.

On the other hand, if the side etching amount is not sufficient in the forward mesa cross-sectional shape, the base electrode metal deposited by electron beam partially contacts the emitter layer, and there is a danger of causing a short circuit between the emitter and the base. In order to perform a sufficiently deep side etching, the etching time must be lengthened, and the reproducibility of the etching depth in the lateral direction and the uniformity within the wafer surface deteriorate. Further, when the deep side etching is performed, the contact area between the emitter electrode material and the emitter contact layer is reduced, and there is a concern that the yield may be reduced.

[0009] Among compound semiconductor-based HBTs, a wavelength band that is particularly excellent in high-speed operation and corresponds to the band gap energy of the material system is well suited to optical devices.
In P / InGaAs HBTs, it has been reported that the InP emitter mesa having a forward mesa cross-sectional shape is more reliable than an inverted mesa shape ("Extended Abstracts of K. Krisima et al.").
The 1997 International Conference on Solid State Devices and Materials 199
7 years 420-421 (K. Kurishima et al., Extended Abstr
acts of the 1997 International Conference on Solid
State Devices and Materials, 1997, pp. 420-421).

Therefore, a highly reliable self-aligned I
In order to manufacture nP / InGaAsHBT, an undercut region must be formed by an emitter mesa structure including a normal mesa surface, and therefore, a sufficiently deep side etching is necessary for an emitter electrode serving as an etching mask. . In particular, the forward mesa surface in InP is
Since it is the (111) B plane and the mesa cross-sectional shape is at an angle close to 45 degrees, a deep side etching amount (0.2 μm or more) that at least greatly exceeds the thickness of the emitter layer is required.

FIGS. 9A and 9B show a conventional InP / I.
It is a schematic sectional drawing which shows the manufacturing process of nGaAsHBT.

In FIG. 9, reference numeral 24 denotes p ⁺ type InGaAs.
A base layer, 25 is an n-type InP emitter layer, 26 is an n ⁺ -type InGaAs emitter contact layer, and 27 is a WSi emitter electrode.

In other words, these figures show a manufacturing process of a self-aligned emitter / base mesa structure including a forward mesa InP emitter layer 25 of InP / InGaAsHBT by a conventional manufacturing method, and a forward mesa cross-sectional structure appears.
11) Shows a cross-sectional shape viewed from the plane orientation.

(A) shows an n ⁺ -type InGaAs emitter contact layer 26 doped with a high concentration n-type impurity,
Using WSi (tungsten silicide) emitter electrode 27 as an etching mask, anisotropic etching by ECR-RIE using Cl ₂ / Ar mixed gas (that is, reactive ion etching using a plasma source excited by electron cyclotron resonance). 4 shows a step of performing etching only in the vertical direction.

(B) shows the state of (A), further using an aqueous solution of citric acid / hydrogen peroxide to form an n ⁺ -type InGaAs emitter contact layer 26 and an n-type InP emitter layer 25 doped with an n-type impurity. After selective side etching, n-type InP using hydrochloric acid / phosphoric acid solution
The step of selectively etching only the emitter layer 25 is shown.

In FIG. 3B, a metal for forming a base electrode for forming a self-aligned base is then subjected to electron beam evaporation from the entire surface including the emitter electrode 27 (not shown). At this time, the n-type InP emitter layer 25 / p ⁺
If the pn junction dimension width of the InGaAs base layer 24 (the width of the lower end of the mesa in contact with the p ⁺ -type InGaAs base layer 24) is longer than at least the width of the WSi emitter electrode 27, a short circuit between the emitter and the base is caused. In addition, the transistor characteristics are significantly reduced. The leakage current between the emitter and the base not only lowers the current gain but also causes a significant deterioration in reliability. Therefore, using citric acid / hydrogen peroxide aqueous solution, n ⁺
Significant side etching must be performed on the type InGaAs emitter contact layer 26.

In order to increase the reliability of the InP / InGaAs HBT, it is important to select a p-type impurity (dopant) in the base layer. However, the diffusion coefficient is the smallest, and the GaAs HBT also exhibits high reliability. C (carbon) is promising. As an epitaxial growth method for doping a C acceptor, metalorganic vapor phase epitaxial growth methods (MOCVD, MOVPE) are widely used in terms of miniaturization of an apparatus and easy replenishment of raw materials. However, during these epitaxial growths, hydrogen of a hydride such as hydrogen (H ₂ ), arsine (AsH ₃ ), or phosphine (PH ₃ ) as a carrier gas is bonded to the C acceptor, inactivating the C acceptor, and The problem was to lower the hole carrier concentration. Hydrogen bonded to C can be easily removed by high-temperature annealing (450 ° C. or higher) at a temperature higher than the base layer growth temperature. However, even if annealing is performed with the wafer having the HBT structure, the space charge at the base / emitter pn junction becomes a barrier, and the same positively charged hydrogen in the base layer cannot escape to the outside. Therefore, it is necessary to remove the emitter layer and perform high-temperature annealing with the base layer exposed (Japanese Journal of Applied Physics Vol. 35, 1996 by H. Ito et al.)
Pp. 6139-6144 (H. Ito et al., Jpn.J. Appl. Phys.
Vol. 35 (1996), pp. 6139-6144). In an actual HBT having an emitter mesa structure, hydrogen in the internal base region immediately below the emitter diffuses in the lateral direction by annealing, and escapes when reaching the external base region.
On the other hand, in order to avoid a decrease in crystallinity, it is desirable to perform annealing at 650 ° C. or lower.

Therefore, in order to achieve dehydrogenation and to recover the hole carrier concentration of the C-doped base layer, the base layer is exposed, and the base layer including the emitter electrode is exposed.
High temperature annealing must be performed in a temperature range of 0 ° C to 650 ° C.

[0019]

SUMMARY OF THE INVENTION In an emitter mesa cross-sectional structure including a forward mesa surface of a self-aligned InP / InGaAs HBT having a C-doped InGaAs base layer, which is expected to have high reliability and excellent high-frequency characteristics, the base is formed by electron beam evaporation. In order to prevent an emitter / base short circuit when depositing an electrode metal, a sufficiently deep side etching must be performed on the emitter electrode serving as a mask as described above. Therefore, with the increase of the wet etching time, the reproducibility of the side etching depth and the decrease in the uniformity within the wafer surface become problems.

In addition, particularly, a fine dimension HB having a narrow emitter width is used.
In T, when deep side etching is introduced, as described above, the contact area between the emitter electrode material and the emitter contact layer is reduced, and the yield is reduced.

In order to increase the hole carrier concentration by performing dehydrogenation of the C-doped InGaAs base layer inactivated by hydrogenation during epitaxial growth,
High temperature annealing above the base layer growth temperature (at least 45
(0 ° C. or more), and since this annealing is performed in a state including the emitter electrode, the emitter electrode is required to have heat resistance. Therefore, gold (Au) usually used for the emitter electrode cannot be used.

In order to avoid the danger of performing a sufficiently deep side etching on the single-layer emitter electrode, a method of processing the laminated emitter electrode into a T-shaped structure and providing an undercut region in the emitter electrode itself has been attempted. (Microwave and Optical Technology Letters, Vol. 11, No. 3 by H. Masuda et al.
1996 pp. 159-163 (H. Masuda et al., Microwave an
d Optical Technology Letters, Vol.11, No.3, 1996, p
p.159-163)). By using the T-shaped emitter electrode structure including the undercut region, the danger of side-etching the emitter contact layer deeply with respect to the emitter electrode can be avoided. However, when forming a T-shaped emitter electrode structure, it is important for the realization of a fine self-aligned HBT with excellent reproducibility that the material of the uppermost layer serving as a mask is not etched by RIE using a reactive gas. For example, tungsten silicide (lower layer) / tungsten (upper layer) (WSi / W) having excellent heat resistance
Is used as an emitter electrode material, and the lower WSi layer is side-etched by RIE using a reactive gas containing fluorine (F) to realize a T-shaped electrode structure. As a result, the film is receded by side etching to some extent, and the controllability and reproducibility of the dimensions of the emitter electrode and the reduction in the uniformity within the wafer surface become problems.

An object of the present invention is to solve the problems of the prior art as described above and to control the size of the emitter electrode.
An object of the present invention is to provide a self-aligned HBT having high reproducibility, uniformity in a wafer surface, high reliability, a high current amplification factor, and excellent in high-frequency characteristics.

[0024]

In order to solve the above-mentioned problems, a method of manufacturing a heterojunction bipolar transistor according to the present invention comprises a method of forming a collector contact layer, a collector layer, a base layer, an emitter layer, and an emitter contact layer on a substrate. a first step of sequentially forming, a second step of depositing a first metal film made of WSi the emitter contact layer, Ti film have a predetermined pattern on said first metal film
Third forming a second metal film ing by depositing Pt film on
Step, and using the second metal film as a mask,
Reactive metal etch using sulfur hexafluoride gas until the emitter contact layer is exposed.
Dry etching in ring, and the side etching in the lateral direction said first metal film from the second end of the metal film on the inner side, T-shaped comprising a first and second metal films A fourth step of forming an electrode, and acid-treating the substrate;
A fifth step of removing a reaction product on the substrate; and selectively using the second metal film as a mask to selectively separate the emitter contact layer in a direction perpendicular to the substrate surface until the emitter layer is exposed. While performing the isotropic dry etching or not performing the anisotropic etching, the emitter contact layer is selectively wet-etched using the T-shaped electrode as a mask, and the wet etching is performed near the end of the first metal film. A sixth step of forming an emitter contact layer having a mesa structure so that an upper end is in contact with the emitter contact layer, and selectively wet-etching the emitter layer using the emitter contact layer as a mask until the base layer is exposed; as its upper end comes into contact with the end portion of the layer, and the seventh step of forming an emitter layer of the mesa structure, with respect to the substrate, the temperature range 45 ° C. performed dehydrogenation by annealing to 650 ° C., and an eighth step of recovering the carrier concentration of the base layer, on the base layer exposed, depositing a third metal film, the base electrode and the T A ninth step of forming in a self-alignment manner with respect to the V-shaped electrode.

The emitter contact layer is made of InG.
consists GaAs, said emitter layer is made of InP, the Ri InGaAs Tona the base layer doped with C, an acid treatment is hydrochloric acid treatment before <br/> SL fifth step, the sixth step ECR-R using a mixed gas of chlorine and argon diluted with an inert gas
IE, wherein the wet etching solution in the sixth step is a mixture of citric acid, hydrogen peroxide solution and water,
Wet etching solution of the seventh step is characterized in that it is a mixture of hydrochloric acid and phosphoric acid.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing an HBT according to the present invention will be described below with reference to the drawings.

The present embodiment is based on a process in which an emitter electrode is formed first, and then a base electrode is formed in a self-aligned manner. Each electrode is formed by vapor deposition and a lift-off method. Please note that this basic process
For example, it is disclosed in Japanese Patent Application Laid-Open No. 5-136159 by the same applicant.

FIG. 7 is a schematic sectional view of an HBT manufactured by the manufacturing method according to the embodiment of the present invention.

1 is a semi-insulating InP substrate, 2 is a collector contact layer, 3 is a collector layer, 4 is a base layer, 5 is an emitter layer, 6 is an emitter contact layer, 10 is a T-shaped laminated emitter electrode, 11, 12, Reference numeral 13 denotes an emitter electrode layer constituting a T-shaped laminated emitter electrode, 14 denotes a base electrode, 1
5 is a collector electrode, 16 is a passivation film, 17 is a silicon oxide film, 18 and 19 are contact through holes, 20 is an emitter pad wiring connected to the emitter electrode 10, and 21 is a collector pad wiring connected to the collector electrode 15. is there.

C-doped In excellent in high frequency characteristics and reliability
Fine self-aligned InP with GaAs base layer /
In order to realize InGaAsHBT, a T-shaped laminated emitter electrode structure is required to prevent an emitter / base short circuit when a base electrode metal is deposited by an electron beam evaporation method in an emitter mesa cross-sectional structure including a normal mesa surface. In this case, a heat-resistant emitter electrode material that can withstand high-temperature dehydrogenation annealing performed at a stage where the C-doped base layer is exposed is required, and at the same time, when forming a T-shaped structure by RIE using a reactive gas, at least the uppermost layer It is desirable that the metal etching rate is extremely slow and the emitter electrode width does not recede.

As a conductive material capable of realizing the T-shaped laminated emitter electrode structure, WSi / Ti / P
The electrode configuration consisting of t is optimal, and a T-shaped laminated emitter electrode and a self-aligned emitter / base mesa structure can be manufactured from the following steps. WSi / Ti /
In the configuration of the Pt laminated electrode, Ti functions to improve the adhesion between WSi and Pt, so that a thin film having a thickness of about 20 nm is formed. WSi and Pt show sufficient heat resistance in the annealing temperature range of 450 ° C. to 650 ° C.
Since this is also a thin film, high temperature annealing does not significantly affect the formation of the self-aligned emitter / base mesa.

The steps of the realizing means are as follows.

FIG. 1 is a layer configuration diagram of an HBT manufactured by the manufacturing method according to the embodiment of the present invention.

1 is a semi-insulating InP substrate, and 2 is an n ⁺ -type InP substrate.
GaAs collector contact layer, 3 is a collector layer, 7,
8 and 9 are constituent layers of a collector layer, 7 is an n-type InP layer, 8
Is an n-type InGaAs layer, 9 is undoped InGaAs
Layers, 4 are p ⁺ -type InGaAs base layers, 5 is n-type InP
Layer 6 is an n ⁺ -type InGaAs emitter contact layer.

FIGS. 2 to 6 show the HB shown in FIGS. 1 and 7.
T emitter / base mesa structure (until base electrode is formed)
It is a schematic sectional drawing which shows the manufacturing process of. 2 to 6
In the figure, the layers below the base layer 4 are not shown.

(1) First, a collector contact layer 2 and a collector layer 3 (7, 8, 9) are formed on a semi-insulating InP substrate.
After sequentially laminating the base layer 4, the emitter layer 5, and the emitter contact layer 6 (see FIG. 7), as shown in FIG. 2, a WSi layer, which is a refractory metal, is formed on the heavily doped n ⁺ -type InGaAs emitter contact layer 6. A Ti / Pt electrode layer 12 patterned in a predetermined shape is formed on the WSi layer 11 'by vapor deposition and lift-off in this order.

(2) Next, as shown in FIG. 3, the WSi layer 1 is formed by RIE using sulfur hexafluoride (SF ₆ ) gas.
At the same time as selectively removing only 1 ', side etching of the WSi layer 11' is performed on at least the uppermost Pt electrode layer 13.

(3) Next, after removing the reaction products adhered on the emitter contact layer 6 with the above-mentioned plasma-formed SF ₆ gas by a concentrated hydrochloric acid treatment, as shown in FIG.
ECR-RI using a chlorine / argon (Cl ₂ / Ar) mixed gas diluted with an inert gas, using the T-shaped WSi / Ti / Pt laminated emitter electrode 10 as an etching mask.
By E, the emitter contact layer 6 is anisotropically etched (in the direction perpendicular to the substrate surface) in the depth direction.

(4) Next, the T-shaped laminated emitter electrode 10
As an etching mask, citric acid, hydrogen peroxide solution,
Using a selective wet etchant composed of water,
As shown in FIG. 5, the emitter contact layer 6 is side-etched at least to the width of the recessed WSi layer 11 by the SF ₆ -RIE.

(5) Next, the T-shaped laminated emitter electrode 10
As an etching mask, using a wet etching solution composed of hydrochloric acid and phosphoric acid, as shown in FIG.
Only the InP emitter layer 5 is selectively etched to expose the C-doped InGaAs base layer 4.

(6) Next, the T-shaped laminated emitter electrode 10
Is performed at a high temperature of at least 450 ° C. without forming an annealing protective film to drive out hydrogen in the base layer 4 and recover the hole carrier concentration.

(7) Next, the T-shaped laminated emitter electrode 10
Over the entire surface of the emitter mesa including Pt / Ti / Pt
A metal layer 14 'for forming a base electrode made of an Au layer is subjected to electron beam evaporation to manufacture a self-aligned emitter / base mesa structure.

By the steps shown in FIGS. 2 to 6, an emitter / base mesa structure including an InP emitter layer having a normal mesa sectional shape as shown in FIG. 7 can be manufactured with good reproducibility and uniformity. Therefore, it is possible to provide a fine dimension self-aligned InP / InGaAsHBT excellent in reliability and high frequency characteristics.

[0044]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an embodiment of a method for manufacturing an HBT according to the present invention.

FIGS. 1 to 7 show schematic cross-sectional structures as viewed from the (011) plane orientation where a normal mesa structure appears.

As shown in FIG. 1, MOVPE (MOCV) is formed on a semi-insulating InP substrate having a (100) plane as a main surface.
D) or the like, an n ⁺ -type InGaAs collector contact layer containing a high-concentration n-type impurity for forming an ohmic resistance in the collector, a collector layer 3 composed of InP and InGaAs, and a high-concentration C impurity A p ⁺ -type InGaAs base layer 4, an n-type InP emitter layer 5 doped with an n-type impurity, and an n ⁺ -type InGaAs emitter contact layer 6 doped with a high-concentration n-type impurity for forming an ohmic resistance in the emitter. Epitaxial growth is performed.

The collector layer 3 made of InP and InGaAs has a band structure designed for ultra-high speed and high withstand voltage. In this embodiment, n-type impurity doped with n-type impurities is used.
An epitaxial layer structure is used in which a P layer 7, an n-type InGaAs layer 8 doped with an n-type impurity, and an undoped InGaAs layer 9 are sequentially epitaxially grown.

Next, as shown in FIG. 2, n ⁺ -type InGa
After a WSi layer 11 'is entirely deposited on the As emitter contact layer 6 to a thickness of 200 nm by sputtering, a Ti / Pt laminated metal structure 12 is formed by electron beam evaporation and lift-off. In this embodiment, the thickness of the Ti / Pt laminated structure 12 is set to 20 nm / 150 nm. Next, after patterning the Ti / Pt laminated structure 12 using a resist, immediately before electron beam evaporation, RIE using a C ₂ F ₆ gas is performed on the WSi layer 11 ′ for 1 minute and 30 seconds to form a WSi layer. 11 'surface is cleaned and WSi layer 1
The contact resistance between 1 'and the Ti layer was reduced as much as possible. At this time, the planar shape of the Ti / Pt layer 12 serving as the emitter electrode has a hexagonal shape in which two corners form an angle of 90 degrees, the (011) plane orientation forms the emitter length, and the emitter width direction. It is important not to include the (01） 1) plane orientation (where “” in “1￣” indicates a negative direction). In this embodiment, the emitter electrode width is 1.2 μm and the emitter length is 5 μm.

Next, as shown in FIG. 3, a Ti / Pt emitter layer 12 as an etching mask to selectively etch only the WSi layer 11 'by RIE using SF ₆ gas, by further performing overetching Then, the WSi layer 11 'is side-etched to an arbitrary depth with respect to the uppermost Pt layer. RIE using this SF ₆ gas
(Use Teflon substrate as base, RF bias is 400
In W), the reaction gas pressure was set as high as 10 Pa so as to increase the isotropic component and promote side etching. The etching rate under this etching condition is W
200 nm / min for the Si layer 11 ′ and 20 nm for the Ti layer
/ Min, the Pt layer and the InGaAs layer 6 are hardly etched.

FIG. 8 is a diagram showing the relationship between the side etching depth and the etching time of the WSi layer 11 'by SF ₆ -RIE in this embodiment (pressure 10P).
a).

As shown in this figure, the dependence of the side etching depth of the WSI on the etching time satisfies the linearity, and the side etching depth can be controlled only by the etching time, which is advantageous in the process. In this embodiment, S
By performing F ₆ -RIE under the above etching conditions for 3 minutes and 15 seconds, WSi is side-etched by about 0.25 μm on one side with respect to Pt, and a desired T-shaped laminated emitter electrode 10 is formed.
The structure can be realized.

Next, after this SF ₆ -RIE treatment, in order to remove a reaction product (for example, fluoride of S-As, Ga or In) with the InGaAs layer 6 by SF ₆ plasma,
The substrate is subjected to a concentrated hydrochloric acid treatment.

Next, as shown in FIG.
Using the Ti / Pt laminated emitter electrode 10 as an etching mask, reactive ion etching (ECR-RIE) using a plasma source excited by electron cyclotron resonance, and anisotropic etching with a Cl ₂ / Ar mixed gas (chlorine gas) By adding an argon gas to the etching mask, verticality of the etching side surface with respect to the etching mask can be realized) at least until the n ⁺ -type InGaAs emitter contact layer 6 is exposed until the n-type InP emitter layer 5 is exposed. The etching of the emitter electrode 10 by the ECR-RIE does not proceed.

Next, the n ⁺ -type InGaAs emitter contact layer 6 etched only in the vertical direction by ECR-RIE is selectively wetted with respect to the n-type InP emitter layer 5 using an aqueous citric acid / hydrogen peroxide solution. Etching is performed to form a mesa structure of the emitter contact layer 6 such that the upper end of the emitter contact layer 6 is in contact with the lower end of the WSi emitter electrode layer 11 as shown in FIG. Next, using the emitter contact layer 6 as a mask, an n-type InP emitter layer 5 is selectively formed on the C-doped p ⁺ -type InGaAs base layer 4 using a hydrochloric acid / phosphoric acid solution until the base layer 4 is exposed. By wet etching, a mesa structure of the emitter layer 5 is formed near the lower end of the emitter contact layer 6 such that the upper end of the emitter layer 5 is in contact with the lower end of the emitter contact layer 6, as shown in FIG. Since the etching of the n ⁺ -type InGaAs layer 6 proceeds from the (100) plane, the etching in the horizontal direction is stopped at the mask end of the WSi layer 11 as shown in FIG. In this embodiment, etching with an aqueous citric acid / hydrogen peroxide solution was performed for 30 seconds. Also, n
-Type InP emitter layer 5, with hydrochloric acid / phosphoric acid solution n ⁺ -type InGaAs layer 6 as a mask is selectively etched, etching of the emitter layer 5 is n ⁺ -type InGaA
Etching stops at the end of the s layer 6. That is, the lateral dimension of the emitter layer 5 is determined by the width of the n ⁺ -type InGaAs layer 6. In this embodiment, etching with a hydrochloric acid / phosphoric acid solution was performed for 15 seconds.

Next, the hydrochloric acid / phosphoric acid solution was used to form n-type I
The nP emitter layer 5 is etched to form p ⁺ -type InGaAs
After the base layer 4 is exposed, hydrogen in the C-doped InGaAs base layer 4 is expelled to increase the hole concentration.
High-temperature dehydrogenation annealing is performed. This dehydrogenation annealing temperature is in the range of 450 to 500 ° C. for 5 to 20 minutes, and a hole concentration recovery of 90% or more can be expected. Then
Forming a photoresist film (not shown) on the substrate;
The photoresist film is patterned and left only in a region outside the external base region where it is not desired to form a base electrode, and then, as shown in FIG. A base electrode forming metal film of / Pt / Au is subjected to electron beam evaporation and lifted off.

Next, the p ⁺ -type InGaAs base layer 4 and the undoped InG
The collector layer (see FIG. 1) composed of the aAs layer 9, the n-type InGaAs layer 8, and the n-type InP layer is selectively wet-etched using a citric acid / hydrogen peroxide aqueous solution or a hydrochloric acid / phosphoric acid solution to obtain an n ⁺ type. InGaAs collector contact layer 2
Is exposed (see FIG. 7), and a collector electrode 15 having a Ti / Pt / Au / Pt / Ti laminated structure is formed by vapor deposition and a lift-off method. Thereafter, using a photoresist film mask, the n ⁺ -type InGaAs collector contact layer 2 is formed.
Is separated from each other by performing mesa etching except for the active element portion using wet etching of a citric acid / hydrogen peroxide aqueous solution. Then, a cycloten resin (BCB) is spin-coated on the entire surface of the wafer, and heated at 250 ° C. Hardening (curing) by heat treatment is performed to form a passivation film 16 on the semiconductor surface. Since the BCB precursor has low viscosity, the BCB precursor is excellent in flatness, and is effective in avoiding problems such as disconnection in a wiring process.

Next, a silicon oxide film (SiO ₂ ) 17 is deposited on the entire surface of the wafer on which the passivation film 16 is applied by plasma CVD, and a photoresist film (not shown) is formed thereon. Emitter electrode 1
0, an opening of the photoresist film is formed on the base electrode 14 and the collector electrode 15 by patterning. Thereafter, using the photoresist film as a mask, the silicon oxide film 17 is etched by RIE using C ₂ F ₆ gas, and the passivation film 16 is etched by RIE using SF ₆ gas, and the contact through holes 18 and 19 (base) are formed. The through-hole of the electrode 14 forms an illustration (not shown in FIG. 7). By using C ₂ F ₆ gas, selectivity with the photoresist can be secured to some extent, and anisotropic etching only in the vertical direction is possible. In this embodiment, the thickness of the silicon oxide film 17 is 300 nm, and the thickness of the photoresist film is about 1.2 μm. Further, since the selectivity to the silicon oxide film 17 can be obtained by performing SF ₆ -RIE, the silicon oxide film 1
The mask No. 7 does not retreat significantly. Therefore, 1
The emitter, base,
A contact through hole for pad wiring on the collector electrode can be formed, and the throughput can be improved. Finally, pad wirings 20 and 21 are formed on the emitter, base and collector electrodes through the contact through holes (pad wirings of the base electrode are not shown). FIG. 7 shows the completed H
The cross-sectional structure outline of the BT is shown. Note that pad wiring 2
0 and 21 are thick Ti / Pt / Au (20/20/120)
0 nm). In the HBT manufactured in such a process, high in-plane uniformity of the well was obtained with good controllability and reproducibility.

In this embodiment, InP / In
Although the most basic structure in the GaAs system has been described, the present invention is not limited to this, and the layer structure can be appropriately designed. Further, although the etching system used is slightly different, InAlAs / InGaAs and AlGaAs / GaAs having a hydrogenated C-doped base layer are used.
s, H using another material system such as InGaP / GaAs system
Needless to say, it can be applied to BT.

Further, ECR-RIE using a mixed gas of Cl ₂ / Ar is used for etching the emitter contact layer 6. However, when the emitter contact layer 6 is thin, the ECR-RIE is not used and the quenching is performed. Even if the emitter contact layer is etched only with an acid / hydrogen peroxide aqueous solution, the purpose of the present invention is satisfied. The type of the wet etching solution is not limited to the citric acid / hydrogen peroxide aqueous solution and the hydrochloric acid / phosphoric acid solution described in this embodiment, but may be InG.
Any wet etching solution for selecting the aAs layer and the InP layer can be used.

[0060]

As described above, according to the method of manufacturing the HBT of the present invention, the controllability of the dimensions of the emitter electrode, the reproducibility, the uniformity within the wafer surface are high, and the reliability and the current amplification factor are high. In addition, it is possible to provide a self-aligned HBT having an excellent high frequency characteristic and a fine dimension suitable for application to a low power consumption circuit.

[Brief description of the drawings]

FIG. 1 is a layer configuration diagram of one embodiment of an HBT according to the present invention.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the emitter / base mesa structure of the HBT shown in FIG.

FIG. 3 is a schematic cross-sectional view showing a step of manufacturing the emitter / base mesa structure of the HBT shown in FIG.

FIG. 4 is a schematic cross-sectional view showing a step of manufacturing the emitter / base mesa structure of the HBT shown in FIG.

FIG. 5 is a schematic cross-sectional view showing a step of manufacturing the emitter / base mesa structure of the HBT shown in FIG.

FIG. 6 is a schematic cross-sectional view showing a step of manufacturing the emitter / base mesa structure of the HBT shown in FIG.

FIG. 7 is a schematic sectional view of one embodiment of an HBT according to the present invention.

FIG. 8 is a diagram showing a relationship between a side etching depth of a WSi layer by SF ₆ -RIE and an etching time in one embodiment of the present invention.

FIGS. 9A and 9B are conventional InP / InGaAs.
It is a schematic sectional drawing which shows the manufacturing process of sHBT.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating InP board, 2 ... n ⁺ type InGaAs collector contact layer, 3 ... collector layer, 7 ... n-type InP
Layer, 8 ... n-type InGaAs layer, 9 ... undoped InGa
As layer, 4 ... p ⁺ -type InGaAs base layer, 5 ... n-type I
nP layer, 6 ... n ⁺ type InGaAs emitter contact layer, 10 ... T-shaped laminated emitter electrode, 11 ... WSi emitter electrode layer, 12 ... Ti / Pt emitter electrode layer, 13 ...
Pt / Ti / Pt / Au emitter electrode layer, 14 ... Pt /
Ti / Pt / Au base electrode, 15 ... Ti / Pt / Au
/ Pt / Ti collector electrode, 16: BCB passivation film, 17: silicon oxide film, 18, 19: contact through hole, 20: Ti / Pt / Au emitter pad wiring, 21: Ti / Pt / Au collector pad wiring.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Noriyuki Watanabe 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (56) References JP-A-8-288302 (JP, A) JP-A-5-326463 (JP, A) JP-A-9-64054 (JP, A) JP-A-9-115919 (JP, A) JP-A 8-288297 (JP, A) JP-A 9-181085 (JP, A) JP-A-2-194652 (JP, A) JP-A-5-136159 (JP, A) JP-A-64-76761 (JP, A) JP-A-5-129324 (JP, A) Nubuo NAGANO, et. a l. , "AlGaAs / GaAs Heterojunction Bipolar Transistor ICs for Optical Transmission Systems", IE ICE TRANS. ELECTRO N. , June 1993, VOL. E76-C, NO. 6, pp. 883-890 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/33-21/331 H01L 29/68-29/737 H01L 21/28-21/288 H01L 29/40-29 / 51 H01L 29/872

Claims (2)

(57) [Claims] A first step of sequentially forming a collector contact layer, a collector layer, a base layer, an emitter layer, and an emitter contact layer on a substrate; and forming a first metal film made of WSi on the emitter contact layer. a second step of depositing a predetermined pattern on said first metal film perforated with on the Ti film
A third step of forming a second metal film Pt film ing by depositing, the second metal film as a mask, selectively said first metal layer, the emitter contact layer is exposed Up to six
Dry etching by reactive ion etching using sulfur fluoride gas , and laterally etching the first metal film laterally inward from an end of the second metal film; A fourth step of forming a T-shaped electrode comprising a first metal film and a second metal film; a fifth step of subjecting the substrate to an acid treatment to remove a reaction product on the substrate; Using the metal film of No. 2 as a mask, the emitter contact layer is selectively anisotropically dry-etched in a direction perpendicular to the substrate surface until the emitter layer is exposed, or without performing the anisotropic etching. , The T
A sixth step of selectively wet-etching the emitter contact layer using the V-shaped electrode as a mask, and forming a mesa-structured emitter contact layer such that the upper end is in contact with an end of the first metal film, Using the emitter contact layer as a mask, the emitter layer is selectively wet-etched until the base layer is exposed, and an emitter layer having a mesa structure is formed so that an upper end thereof is in contact with an end of the emitter contact layer. Step 7, dehydrogenation of the substrate by heat treatment in a temperature range of 450 ° C. to 650 ° C. to recover the carrier concentration of the base layer, A ninth step of depositing a metal film of No. 3 and forming a base electrode in self-alignment with the T-shaped electrode. Method of manufacturing a case bipolar transistor. 2. The method according to claim 1, wherein said emitter contact layer is made of InGaAs.
The emitter layer is made of InP, and the base layer is made of C-doped InGaAs.And Previous The acid treatment in the fifth step is a concentrated hydrochloric acid treatment, and the anisotropic dry etching in the sixth step is an inert gas treatment.
Using a gas mixture of chlorine and argon diluted with water
ECR-RIE, wherein the wet etching solution in the sixth step is citric acid,
A liquid mixture of hydrogen peroxide water and water, wherein the wet etching solution in the seventh step is hydrochloric acid and
With a mixture of phosphoric acidis there2. The method according to claim 1, wherein
A method for manufacturing a heterojunction bipolar transistor.