JPH05136159A - Heterojunction type bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a device which is excellent in high speed operation, reliability and uniformity and suitable to microminiaturization, by providing an emitter- base mesa which is self-aligned with an emitter electrode and smaller than it, and a base electrode aligned with the emitter electrode. CONSTITUTION:Emitter regions 5-7 of a first conductivity type, a base region of a second conductivity type, and collector regions 2, 3 of a first conductivity type are formed on a semiconductor substrate 1. In a mesa type heterojunction bipolar transistor in the above constitution, an emitter.base mesa is self-aligned with an emitter electrode 11, and the size of the emitter.base mesa is made smaller than the emitter electrode 11. When viewed from above, the end of the emitter electrode 11 coincides with the end of a base electrode 12, and the base electrode 12 is self-aligned with the base.collector mesa. For example, the emitter electrode 11 is used as a mask and the emitter.base mesa is etched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a heterojunction bipolar transistor (hereinafter abbreviated as HBT), a semiconductor material having a bandgap larger than that of a base is used for an emitter so that the emitter injection efficiency is increased even if the base is heavily doped with impurities. It has the advantage of being able to maintain the temperature and can operate at higher speed than the homojunction bipolar transistor.

As an HBT, an AlGaAs / GaAs system HBT is taken as an example, and a well-known structure is shown in FIG. On the semi-insulating GaAs substrate 1, a subcollector layer 2, n made of GaAs containing a high concentration of n-type impurities
-Type collector layer 3 made of GaAs, base layer 4 made of GaAs containing a high concentration of p-type impurities, emitter layer 5 made of AlGaAs containing an n-type impurity, and emitter made of GaAs containing a high concentration of n-type impurities Cap layer 6
On the emitter cap layer 6, the base layer 4, and the sub-collector layer 2, respectively, for example, AuGe / N
Emitter electrode 1 made of i, AuZn, AuGe / Ni
1 ', a base electrode 12', and a collector electrode 13 '.

[0004]

However, in order to increase the operating speed of the heterojunction bipolar transistor or to improve the performance of the integrated circuit by using it as a constituent element of the integrated circuit, it is necessary to miniaturize the device. Although indispensable, the transistor having the above-mentioned structure has the following problems, which makes it difficult to miniaturize it or lacks reliability.

.. Since the emitter electrode exists on the emitter mesa with a smaller area than the emitter mesa, there is no pattern alignment margin. Furthermore, the situation that a through hole for contacting the wiring and the emitter electrode has to be formed on the emitter electrode makes the situation where there is no room for alignment more severe. Therefore, it is difficult to miniaturize the emitter electrode.

[0006] Even if the emitter is miniaturized, it is difficult to miniaturize the base. This is because a margin is still required for the distance between the emitter mesa and the end of the base electrode. The fact that the distance between the emitter mesa and the base electrode end cannot be shortened leads to the fact that the base resistance cannot be reduced, and the fact that the base electrode cannot be miniaturized leads to the fact that the capacitance between the base and the collector cannot be reduced and the transistor performance is improved. Hinder.

[0007]. Since there is a part where the emitter-base junction is exposed on the side wall of the mesa, it is particularly preferable to use AlGaA.
In the case of s / GaAs HBT, the base current due to the recombination at the exposed junction cannot be reduced. This effect becomes relatively larger as the size of the emitter becomes smaller, and the current amplification factor decreases even if the emitter and the base are physically miniaturized.

[0008] It is difficult to miniaturize the electrodes because alloy type ohmic electrodes are used for all three terminals. Further, since the constituent atoms are mutually diffused between the semiconductor and the metal, the ohmic resistance may increase, and the characteristics of the pn junction of the semiconductor may be affected, resulting in poor reliability.

[0009]. In many cases, the emitter mesa is formed before forming the emitter electrode, which makes it difficult to form a pattern of the emitter electrode with high resolution. In addition, the surface of the emitter cap layer to which the emitter electrode is attached is often subjected to some treatment such as plasma irradiation before the electrode is formed, which makes it difficult to obtain a good ohmic contact.

[0010]. Before applying the base electrode, the thin base layer must be exposed, but there is no margin for this process. That is, if the base layer is exposed and further overetched, the base resistance increases and the base-collector junction characteristic deteriorates.

[0011]. Before forming the base electrode,
In many cases, collector mesas are formed, and it becomes difficult to form a pattern of the base electrode with good resolution. Also,
Although it is necessary to narrow the width of the base electrode, it is difficult to form a narrow base electrode pattern in the vicinity of the presence of the emitter mesa.

[0012]. Since the base-collector mesa is outside the base electrode, the junction capacitance of the base-collector becomes large. At the same time, since the distance from the collector electrode end to the emitter mesa end becomes long, the collector resistance becomes large.

The present invention has been made to solve the above problems, and provides a heterojunction bipolar transistor which is excellent in high speed, reliability, and uniformity and suitable for miniaturization, and a manufacturing method thereof. With the goal.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0015]

The heterojunction bipolar transistor according to the present invention has basically the same structure as the conventional heterojunction bipolar transistor shown in FIG.

In order to achieve the above object, the present invention has an emitter / base mesa smaller than an emitter electrode formed in self-alignment with an emitter ohmic electrode, and self-aligns with the emitter electrode. It is characterized in that it has a base electrode formed in alignment, and has a base-collector mesa formed in self-alignment with the base electrode.

In order to realize this structure, the manufacturing method according to the present invention is such that MBE (Molecular Be) is added at the beginning of the manufacturing process.
am Epitaxy) or MOCVD (Metalorganic Chemi)
HB with crystal growth such as cal Vapor Deposition method
An emitter electrode is formed on the uppermost emitter cap layer of the T-wafer.

Furthermore, the present emitter electrode is a non-alloy type ohmic electrode and is characterized in that heat treatment is performed immediately after the formation of the emitter electrode in order to secure the adhesion with the emitter cap layer.

The manufacturing method of the present invention is characterized in that base / emitter mesa etching is performed using the emitter electrode as a mask.

Furthermore, by performing etching using a selective etching solution for etching only the emitter cap layer or the emitter layer as a part of this etching, it is possible to insert an undercut in the emitter cap layer or the emitter layer with respect to the emitter electrode. Characterize.

When the emitter cap layer is selectively etched, the emitter layer is etched to expose the base layer. Before the etching of the emitter layer, the undercut portion is filled with, for example, a resist, or sidewalls of an insulating film are formed to leave only the emitter layer under the umbrella of the emitter electrode. The remaining emitter layer becomes a guard ring that surrounds the emitter mesa and does not increase the recombination current in the mesas of the mesa. When the emitter layer is selectively etched, the etching exposes the base layer.

Next, the method of manufacturing an HBT according to the present invention is characterized in that the base electrode is vapor-deposited including the top of the emitter electrode. Due to the above-described undercut, the base electrode is formed in a self-aligned manner with respect to the emitter electrode by this process without short-circuiting the emitter electrode to the base electrode. The present base electrode is also a non-alloy type ohmic electrode, and is characterized in that heat treatment is performed immediately after the electrode is formed in order to secure adhesion with the base layer.

Next, although base / collector mesa etching is performed, the present invention is characterized in that etching is performed using the base electrode as a mask. That is, the resist is patterned so as to cover the emitter mesa, and the cover resist is etched so as to fit inside the base electrode.

Another feature of the present invention is the utilization of crystal anisotropy. That is, depending on the material system, the etching rate and etching shape may remarkably differ depending on the crystal orientation in the selective etching for forming the undercut. In the present invention, the pattern arrangement direction is determined so that the undercut is surely formed along the long side direction of the emitter.

[0025]

According to the above-described means, the heterojunction bipolar transistor having the conventional structure shown in FIG. 10 has the same structure as the heterojunction bipolar transistor having the conventional structure shown in FIG. It has the basic functions of.

Furthermore, the heterojunction bipolar transistor according to the present invention can simultaneously realize the following features.

Since the emitter / base mesa is formed self-aligningly with respect to the emitter electrode and smaller than the emitter electrode, the emitter can be easily miniaturized and the emitter resistance can be reduced. Since the patterning and formation of the emitter electrode are performed at the beginning of the manufacturing process, it is easy to miniaturize the emitter electrode with high resolution and reduce the emitter resistance uniformly with reproducibility.

Since the base electrode is formed in self-alignment with the emitter electrode by utilizing the undercut under the emitter electrode, the base resistance is reduced.
Further, since the patterning of the base electrode may be formed so as to include the region of the emitter electrode, it is extremely easy to reduce the width of the base electrode.

The base-collector mesa is formed in self-alignment with the base electrode. The self-alignment of the base electrode and the base-collector mesa, together with the self-alignment of the base electrode and the emitter electrode and the easy narrowing of the width of the base electrode, make it possible to significantly reduce the base-collector junction area. Capacity is reduced.

Since the emitter electrode and the base electrode are made of a non-alloy type metal, reliability is increased and miniaturization is easy. In particular, the base electrode exposes a thin base layer and forms an ohmic electrode there, so a non-alloy type electrode is indispensable. Further, since the heat treatment for increasing the adhesion is performed immediately after the formation of these non-alloy type ohmic electrodes, it is possible to avoid the fine electrode pattern from peeling even during the selective wet etching.

[0031]

Embodiments of the present invention will be described in detail below with reference to the drawings.

In all the drawings for explaining the embodiments,
Those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

Example 1 The structure of an HBT of Example 1 of the present invention is shown in FIG. 1 (schematic cross-sectional view). Semi-insulating GaA
On the main surface of the substrate 1, an n ⁺ GaAs subcollector layer 2 for forming an ohmic contact with the collector by a method such as MBE or MOCVD, an n-type or undoped GaAs collector layer 3, p ⁺ GaA
s or p ⁺ AlGaAs base layer 4, n-type AlGaA
s emitter layer 5, n ⁺ GaAs emitter cap layer 6, and n ⁺ InG for making ohmic contact with the emitter
The contact layer 7 of aAs is epitaxially grown.
Here, when the base layer 4 is AlGaAs, the Al composition ratio is continuously increased from the collector side end to the emitter side end, for example, from 0 to 0.1. The Al composition ratio of the emitter layer 5 is, for example, 0.3 at the center of the layer so that both the base side and the emitter cap side are continuously connected. The thickness of each layer is, for example, 800 nm for the sub-collector layer 2, 300 nm for the collector layer 3, 40 nm for the base layer 4, and 8 for the emitter layer 5.
0 nm, the emitter cap layer 6 is 160 nm, and the emitter contact layer 7 is 90 nm.

Here, the collector may have a multi-layer structure such as n ⁺ · n to · p ⁺ · n ⁺ in order to utilize the ballistic movement of electrons. Also, depending on the application field, it is easy to increase the collector breakdown voltage by setting the thickness as thick as 1 μm and setting the carrier concentration low.

A manufacturing process for realizing the structure of FIG. 1 will be described step by step. First, following the step of epitaxial growth, a photoresist is applied on the emitter contact layer 7, and the resist in the region where the emitter electrode is formed is removed by a known method to pattern the emitter electrode. Since the wafer is flat at this stage, fine patterning of the emitter electrode can be easily performed with high resolution.

Then, for example, as an emitter electrode material,
Ti / Pt / Au is vapor-deposited, an unnecessary portion of the electrode material is lifted on together with the resist, and an emitter electrode is formed as shown in FIG. 2 (schematic cross-sectional view). After lift-off, heat treatment is performed at 300 ° C., for example, in order to increase the adhesion between the emitter contact layer and the electrode material. Where Ti / Pt / Au
Is a non-alloy type ohmic electrode, which can provide a highly reliable ohmic contact and can maintain high resolution as an electrode pattern. Further, since the emitter electrode is formed in the first stage of the process, it is easy to uniformly form the ohmic contact having low resistance.

Then, ECR (El) using Ar and Cl ₂
The InGaAs contact layer 7 and the GaAs emitter cap layer 6 are etched by plasma etching (ectron Cyclotron Resonance). This dry etching is performed as shown in FIG.
The As layer 6 is performed halfway. At this time, the emitter electrode 11
Serves as a mask material for etching. Other methods can be used as long as they are directional dry etching.
Following the dry etching, the GaAs layer 6 is etched with, for example, an etching solution containing hydrogen peroxide and ammonia water. In order to selectively etch the GaAs layer, this etching solution forms an undercut under the emitter electrode 11 as shown in FIG. 4 (schematic cross-sectional view). Further, this selective etching solution is AlGaA.
Since the s emitter layer 5 is hardly etched, the margin is increased as compared with the previous dry etching, and
Even if there are variations, clear them.

Next, a photoresist is applied to the entire surface of the wafer, and the entire surface is exposed and developed without patterning. Through this step, the undercut portion is filled with the photoresist 21. In order to increase the adhesion between the resist 21 and the undercut portion, after heat treatment at 130 ° C., the emitter layer 5 is etched with a mixed solution of sulfuric acid, hydrogen peroxide solution and water to expose the base layer 4. Since the emitter layer 5 is thin, the base layer 4 can be uniformly exposed over the entire surface of the wafer without overetching the base layer 4. If the emitter electrode 11 having a size that can be applied with a prober is arranged, the completion of etching of the emitter layer 5 can be confirmed by examining the voltage-current characteristics between the emitter electrodes. That is, while the emitter layer 5 remains, it shows ohmic characteristics, but when the etching of the emitter layer 5 is completed, it becomes diode characteristics. The resist 21 is removed after exposing the base surface.

Here, since the undercut is filled with the resist 21, the emitter layer 5 at the undercut portion remains without being etched. The remaining emitter layer 5 serves as a guard ring. That is, it is prevented that the emitter-base junction is exposed to the outside due to depletion in the operating state of the transistor, the increase of the recombination current at the side of the mesa is suppressed, and the current amplification factor is not decreased.

In order to form the guard ring, SiN is formed in the undercut portion as shown in FIG. 5 (schematic cross-sectional view).
The sidewall 22 may be formed. In order to form the SiN sidewall 22, first, a photo CVD (Chemica
SiN is deposited by l Vapor Deposition).
The insulating film formed by photo-CVD has good step coverage, and the film is evenly deposited on the undercut portion. Then, the SiN film is etched by a known dry etching technique to form the SiN sidewall 22 as shown in FIG. In this state, if the emitter layer 5 is etched by the method described above, a guard ring is formed.

After exposing the base layer 4, a photoresist is applied to form a base electrode and patterning for the base electrode is performed. Since this patterning is performed so as to cover the emitter mesa, it is not necessary to narrow the patterning width itself to narrow the width of the base electrode. continue,
For example, a non-alloy type base metal material of Ti / Pt / Au is vapor-deposited, and an unnecessary portion of the electrode material is lifted off together with the resist to realize the structure shown in FIG. 6 (schematic cross-sectional view). The base electrode material is also vapor-deposited on the emitter electrode 11, but due to the undercut, the base and the emitter are not short-circuited. By this step, the base electrode 12 having a narrow width can be easily formed on the emitter electrode in a self-aligned manner. Next, as in the case of the emitter electrode, heat treatment is performed at, for example, 300 ° C. in order to increase the adhesion between the base layer 4 and the base electrode 12.

Subsequently, a photoresist is applied and patterning is performed to form an emitter mesa cover 23 as shown in FIG. 7 (schematic cross-sectional view). At this time, since the boundary of the pattern has only to be on the base electrode 12, the alignment margin is large.

Next, base / collector mesa etching is performed by using, for example, a mixed solution of sulfuric acid, hydrogen peroxide and water. Since the base electrode 12 serves as an etching mask, the base collector mesa is formed in self-alignment with the base electrode 12 (FIG. 7). The etching amount is at least required to remove the base layer, and a desired side etching can be performed in order to reduce the base-collector junction area and thus the base-collector capacitance.

The base / collector mesa etching is Ar
Alternatively, plasma etching of ECR using Cl ₂ and Cl ₂ may be performed. In this case, side etching does not occur, and it becomes extremely easy to eliminate the disconnection of the upper layer wiring at the step portion.

Subsequently, a photoresist is applied and patterning for a collector electrode is performed. Using this resist as a mask, etching with a mixed solution of sulfuric acid, hydrogen peroxide and water is performed to form a collector electrode in an area. The collector contact layer 2 is exposed. Then, for example, AuGe / N
A collector electrode material of i / Ti / Pt / Au is vapor-deposited, and an unnecessary portion of the electrode material is lifted off to form the collector electrode 13. Next, heat treatment is performed, for example, at 360 ° C. to alloy the alloy and obtain a low ohmic collector ohmic contact.

Since the subsequent steps such as element isolation and formation of upper layer wiring are carried out by known methods, description thereof will be omitted.

Example 2 Example 2 of the HBT structure according to the present invention is shown in FIG. 8 (schematic cross-sectional view). Semi-insulating I
On the main surface of the nP substrate 51, by a method such as MOCVD, a collector buffer layer 51 ', an n ⁺ InGaAs subcollector layer 52 for forming an ohmic contact with the collector, an n-type or undoped InGaAs
Collector layer 53, ap ⁺ InGaAs base layer 54,
An n-type InP emitter layer 55, an n ⁺ InP emitter cap layer 56, and an n ⁺ InGaAs contact layer 57 for making ohmic contact with the emitter are epitaxially grown. The thickness of each layer is, for example, the buffer layer 51 ′.
Is 100 nm, the subcollector layer 52 is 400 nm, the collector layer 53 is 300 nm, the base layer 54 is 50 nm, the emitter layer 55 is 150 nm, the emitter cap layer 56 is 50 nm, and the emitter contact layer 57 is 100 nm.

Here, the collector may have a multi-layered structure such as n ⁺ · n to · p ⁺ · n ⁺ in order to utilize the ballistic movement of electrons.

The manufacturing process for realizing the structure of FIG.
AlGaAs / GaAs shown in Example 1
Although it is the same as the manufacturing process of the system HBT, the difference will be mainly described below.

First, following the epitaxial growth step, a non-alloy type emitter electrode 61 is formed on the emitter contact layer 57, and a heat treatment is performed to increase the adhesion. Next, InGa plasma etching was performed using Ar and Cl ₂ with the emitter electrode 51 as a mask to remove InGa.
As contact layer 57 and InP emitter cap layer 5
Etch 6 and part of the InP emitter. The steps up to this point are the same as in the case of the first embodiment.

However, the long side direction of the emitter is such that it becomes an inverted mesa shape when the cross section in the long side direction is seen by subsequent wet etching, for example, in the [011] direction (direction perpendicular to the wafer orientation flat). Unified.

Next, the emitter layer 55 is etched with a mixed solution of hydrochloric acid and water. Since InGaAs is not etched by hydrochloric acid, the base layer 54 is uniformly exposed over the entire surface of the wafer. At this time, in wet etching of InP, crystal anisotropy appears strongly, and an inverted mesa undercut as shown in FIG. 9 (schematic cross-sectional view) is formed under the emitter electrode. In the present embodiment, since the long side direction of the emitter is set to [011], the etching shape is a forward mesa shape along the short side direction, that is, the [011] ((− is negative direction) direction, and the side etching proceeds. It is difficult to do this, but if the width of the emitter in the short side direction is 2 μm or less, which is practical for a high-speed transistor, it is oblique,
[10] [01-0] [001] [001-] Since side etching easily proceeds from each direction, an undercut can be formed so as to surround all of the emitter mesas.

The long side direction of the emitter may be unified in the [010] direction instead of the [011] direction. In this case, side etching progresses while maintaining a surface perpendicular to the main surface of the wafer to form an undercut.

In this embodiment, the guard ring is not formed around the emitter mesa as in the case of the first embodiment, but in the InP / InGaAs HBT, the recombination current is generated even if the emitter-base junction is exposed. Since it is extremely small, no guard ring is required.

Since the subsequent steps are almost the same as those in the first embodiment, the description thereof will be omitted. However, the sub-collector layer 52
Is n ⁺ InGaAs, the ohmic contact can be a good ohmic contact as a non-alloy type electrode of, for example, Ti / Pt / Au as well as the emitter and the base.

Although the present invention has been specifically described based on the above embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the scope of the invention. ..

[0057]

As described above, H according to the present invention
In BT, the emitter electrode is formed in the first stage of the process and is made of a non-alloy type electrode material, so that the contact resistance becomes uniformly small and stable. Further, the emitter mesa and the base electrode are formed in a self-aligned manner with respect to the emitter electrode, and the base-collector mesa is formed in a self-aligned manner with respect to the base electrode. Therefore, miniaturization is easy, and the base resistance and the base-collector capacitance are reduced. Further, by disposing a guard ring, it is possible to suppress the current amplification factor accompanying the miniaturization of the emitter. In addition, the production of the HBT according to the present invention does not require any special process,
It consists of extremely simple steps.

As described above, according to the present invention, an HBT excellent in high frequency characteristics, fine and highly reliable can be easily realized with good reproducibility and uniformity, and without complicated steps. It will be possible.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional structure diagram showing a schematic configuration of a heterojunction bipolar transistor of Example 1 of the present invention,

FIG. 2 is a schematic cross-sectional structure diagram for explaining each step in the method for manufacturing the heterojunction bipolar transistor of FIG.

FIG. 3 is a schematic cross-sectional structure diagram for explaining each step in the method of manufacturing the heterojunction bipolar transistor of FIG.

FIG. 4 is a schematic cross-sectional structure diagram for explaining each step in the method for manufacturing the heterojunction bipolar transistor of FIG.

5 is a schematic cross-sectional structure diagram for explaining each step in the method for manufacturing the heterojunction bipolar transistor of FIG.

6 is a schematic cross-sectional structure diagram for explaining each step in the method for manufacturing the heterojunction bipolar transistor of FIG.

7 is a schematic cross-sectional structure diagram for explaining each step in the method for manufacturing the heterojunction bipolar transistor of FIG.

FIG. 8 is a schematic cross-sectional structure diagram showing a schematic configuration of a terror junction type bipolar transistor of Example 2 of the present invention,

9 is a schematic cross-sectional structure diagram for explaining each step in the method for manufacturing the heterojunction bipolar transistor in FIG.

FIG. 10 is a schematic cross-sectional structure diagram showing the structure of a conventional heterojunction bipolar transistor.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... n ⁺ GaAs subcollector layer, 3 ... N-type GaAs collector layer, 4 ... p ⁺ GaA
s or p ⁺ AlGaAs base layer, 5 ... n-type AlGaA
s emitter layer, 6 ... n ⁺ GaAs emitter cap layer,
7 ... n ⁺ InGaAs emitter contact layer, 11 ... T
i / Pt / Au emitter electrode, 12 ... Ti / Pt / Au
Base electrode, 13 ... AuGa / Ni / Ti / Pt / Au
Collector electrode, 21 ... photoresist, 22 ... SiN sidewall, 23 ... emitter mesa cover, 51 ... semi-insulating InP substrate, 51 '... collector buffer layer, 52 ... n
⁺ InGaAs subcollector layer, 53 ... n-type InGaA
s collector layer, 54 ... p ⁺ InGaAs base layer, 5
5 ... n-type InP emitter layer, 56 ... n ⁺ InP emitter cap layer, 57 ... n ⁺ InGaAs emitter contact layer, 61 ... Ti / Pt / Au emitter electrode, 62 ... T
i / Pt / Au base electrode, 63 ... Ti / Pt / Au collector electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Kurishima 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Inventor Hiroki Nakajima 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (8)

[Claims] 1. A mesa heterojunction bipolar device having a first conductivity type emitter region, a second conductivity type base region, and a first conductivity type collector region formed on a semiconductor substrate. In the transistor, the emitter / base mesa and the emitter electrode are self-aligned, the size of the emitter / base mesa is smaller than the size of the emitter electrode, and the end of the emitter electrode and the end of the base electrode coincide with each other in plan view, A heterojunction bipolar transistor characterized in that the base electrode and the base-collector mesa are self-aligned. 2. A manufacturing method for forming a mesa heterojunction bipolar transistor by using a heterojunction bipolar transistor wafer having a collector layer, a base layer, an emitter layer, and an emitter cap layer on a semiconductor substrate. A method of manufacturing a heterojunction bipolar transistor, which comprises forming an emitter ohmic electrode on a cap layer as a first step. 3. The method of manufacturing a heterojunction bipolar transistor according to claim 2, wherein emitter-base mesa etching is performed using the emitter electrode as a mask to form an appropriate undercut under the emitter electrode and at the same time expose the base surface. And a base electrode is formed in a region including a part or all of the emitter electrode and the emitter mesa, and the emitter electrode and the base electrode are self-aligned without short-circuiting the emitter and the base. Manufacturing method of bipolar transistor. 4. The method for manufacturing a heterojunction bipolar transistor according to claim 3, wherein at the time of emitter / base mesa etching using the emitter electrode as a mask, first, one of the emitter cap layer is formed by anisotropic dry etching. Part is etched off, and then selective wet etching is performed to stop etching at the interface between the emitter layer and the emitter cap layer, and this etching simultaneously forms an undercut under the emitter electrode. Manufacturing method of bipolar transistor. 5. The method for manufacturing a heterojunction bipolar transistor according to claim 3, wherein when the base layer is exposed, the undercut portion is filled with a resistor, or a sidewall made of an insulating film is formed in the undercut portion. A method for manufacturing a heterojunction bipolar transistor, which is characterized by forming a part of an emitter layer at an undercut portion to form a guard ring. 6. The method for manufacturing a heterojunction bipolar transistor according to claim 3, wherein during the emitter / base mesa etching using the emitter electrode as a mask, the emitter cap layer is first etched or isotropic. The emitter cap layer and a part of the emitter layer are etched by dynamic dry etching, and then selective wet etching is performed to etch only the emitter layer to expose the base layer and simultaneously form an undercut under the emitter electrode. And method for manufacturing heterojunction bipolar transistor. 7. The method for manufacturing a heterojunction bipolar transistor according to claim 3, wherein the direction of the long side of the emitter is along the long side due to crystal anisotropy during etching when forming an undercut. A method of manufacturing a heterojunction bipolar transistor, characterized in that the undercut shape is unified so as to be an overhang shape or a vertical direction. 8. A mesa heterojunction bipolar device having a first conductivity type emitter region, a second conductivity type base region, and a first conductivity type collector region formed on a semiconductor substrate. In the transistor manufacturing method,
A non-alloy type base electrode is formed before the collector mesa etching, the emitter mesa is covered with a resist when the base collector mesa etching is performed, and the resist is not outside the already formed base electrode. And a method of manufacturing a heterojunction bipolar transistor, characterized by etching using a base electrode as a mask.