JP2714096B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to forming an ohmic contact with a p-type compound semiconductor layer.

[Conventional technology]

Heterojunction bipolar transistors formed by joining heterogeneous semiconductor materials to form a heterojunction have superior high-frequency characteristics and switching characteristics compared to homojunction bipolar transistors made using a single material. It is very promising as a transistor for high-speed logic circuits and a transistor for high-speed analog circuits.

However, it is difficult to form a heterojunction with good interface characteristics, and it is extremely difficult to form a multilayer thin film in which the amount of doping in each layer is carefully controlled. No progress has been seen.

In recent years, with the development of excellent epitaxy technologies such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD), heterojunction bipolar transistors as ultra-high-speed devices have been receiving attention again. .

Such heterojunction bipolar transistor, as shown a structural cross-sectional view in FIG. 3 as an example, the non-doped gallium arsenide (GaAs) surface of the substrate 1, a collector region consisting of n ⁺ GaAs layer 2, p ^- The base region composed of the GaAs layer 3 and the emitter region composed of the n ^- AlGaAs layer 4 are sequentially laminated by the MBE method.
A collector electrode 5, a base electrode 6, and an emitter electrode 7 are formed.

In such a heterojunction bump transistor, the formation of an electrode on the base region composed of the p ^- GaAs layer 3 is performed by np
The n-layer of the compound semiconductor substrate having the n-structure is etched to expose the p-layer (p ^- GaAs layer 3), and gold-zinc (Auz
n) It is performed by depositing a metal layer such as a layer.

By the way, the impurity concentration of the p-layer is set to a condition that enhances the performance of the intrinsically operating portion of this transistor, and its value is about 5 × 10 ¹⁹ / cm ³ . On the other hand, the ohmic contact resistance to the p-type compound semiconductor becomes lower as the p-type carrier concentration becomes higher, and in order to obtain an ohmic contact resistance of about 1 × 10 ⁻⁷ Ωcm ^2, an impurity of 1 × 10 ²⁰ / cm ³ or more is required. A concentration p-layer is required.

Similarly, for the purpose of enhancing the performance of the intrinsically operating portion of the transistor, the p-type compound semiconductor is often, for example, p-type GaAlAs instead of p-type GaAs.
In many cases, ohmic contact resistance to the Auzn layer is higher than that of p-type GaAs.

For these two reasons, in the conventional heterojunction bipolar transistor, the electrode for contacting the base region cannot reduce the contact resistance, which has been one of the major causes of hindering the high-speed operation.

This has been a factor that hinders improvement in performance such as high-speed performance not only in heterojunction bipolar transistors but also in compound semiconductor devices in general including formation of electrodes on p-type compound semiconductors.

That is, the high speed of such a compound semiconductor device is
It is determined by the performance of the intrinsic operation portion of the semiconductor device and the magnitude of the parasitic capacitance and parasitic resistance associated therewith. In particular, in the case of a bipolar transistor having an npn structure, the size of the external base of the p-type base significantly affects high-speed performance. Incidentally, the external base resistance is composed of two components, a sheet resistance of the base electrode and an ohmic contact resistance for taking out the base electrode. Therefore, it has been strongly desired to form an electrode capable of reducing the ohmic contact resistance while maintaining good performance of the intrinsic operation portion.

(Problems to be Solved by the Invention) As described above, in the conventional compound semiconductor device having the npn structure, it was not possible to form a contact with low ohmic contact resistance while maintaining good performance of the intrinsic operation portion.

The present invention has been made in view of the above circumstances, and in an npn structure compound semiconductor device, a method of forming an electrode on a p-layer capable of reducing ohmic contact resistance while maintaining good performance of an intrinsic operation portion. The purpose is to provide.

Another object of the present invention is to miniaturize a compound semiconductor device having an npn structure.

[Configuration of the invention]

(Means for Solving the Problems) Therefore, in the method of the present invention, a pattern composed of a high melting point metal layer is formed on a substrate surface including a compound semiconductor region having an npn structure, and the substrate surface is etched using this pattern as a mask. The p-layer is exposed, and using this pattern as a mask, a p-layer for ohmic contact having a desired concentration is selectively grown on the surface of the p-layer by an epitaxial growth method, and a metal electrode is formed on the surface of the p-layer. I have.

Further, according to the semiconductor device of the present invention, in the above method, p
The metal electrode formed on the layer surface is used as a first electrode, and the refractory metal pattern used as a mask for epitaxial growth is used as a second electrode.

(Operation) According to the above configuration, formation of an ohmic contact to the p-layer is convenient for obtaining a low-resistance ohmic contact having a desired (high) carrier concentration epitaxially grown on the p-layer. Since it is formed on a p-type compound semiconductor layer for contact of various kinds, it becomes possible to obtain an ohmic contact resistance of about 1 × 10 ⁻⁷ Ωcm ² , which was impossible with the prior art.

Further, since the epitaxial growth is performed using the high-melting-point metal thin film as a mask, the high-melting-point metal thin film can be stably maintained without causing a reaction of the compound semiconductor even under a high temperature condition during the epitaxial growth step. Therefore, this refractory metal thin film can be used as it is as an extraction electrode for the n-layer.

Furthermore, according to this apparatus, since the epitaxial growth layer is selectively formed using the high melting point thin film as a mask,
The electrode formed on the epitaxial growth layer and the electrode made of the high melting point metal thin film are formed close to each other in a self-aligned manner. For this reason, it is possible to reduce the parasitic resistance due to the sheet resistance of the p layer from the high melting point thin film electrode to the electrode on the epitaxial growth layer,
As a result, the high speed of the compound semiconductor device can be sufficiently brought out.

As described above, by reducing the contact resistance and shortening the length of the p-layer leading to the contact, it is possible to reduce the parasitic resistance due to the sheet resistance.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a heterojunction bipolar transistor (HBT) according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (h) show a method of a heterojunction bipolar transistor according to an embodiment of the present invention. It is a manufacturing process figure at the time of applying to manufacture.

As shown in FIG. 1, this HBT is configured similarly to the conventional HBT shown in FIG. 3, and has a p ^- G
The formation of an ohmic contact to the AlAs layer is performed by using a high-concentration Zn-doped p ^- GaAs layer epitaxially grown using the tungsten nitride (WNx) layer 7 as a mask.
10 (base electrode), and the tungsten nitride (WNx) layer 7 is directly used as an emitter electrode.

That is, first, as shown in FIG. 2A, a high concentration silicon-doped n ⁺ GaAs layer 2 and a silicon-doped n-type GaAs layer 2 constituting a collector layer are formed on the surface of a chromium-doped n-type GaAs substrate 1 by MBE. GaAs layer 3, beryllium-doped p ⁺ AlGaAs layer 4 constituting the base layer (beryllium concentration 1 × 10 ¹⁹
/ Cm ³ ), silicon-doped n AlG constituting the emitter layer
An aAs layer 5 and an n ⁺ InGaAs layer 6 doped with silicon at a high concentration are sequentially deposited.

Thereafter, as shown in FIG. 2 (b), a 1500 nm-thick tungsten nitride (WN
x) deposit layer 7;

Then, as shown in FIG. 2 (c), after applying the resist film, the resist film is patterned by photolithography to form a resist pattern 8. Then, the tungsten nitride layer 7 is patterned by reactive ion etching using the resist pattern 8 as a mask.

Then, as shown in FIG. 2 (d), etching is performed using the tungsten nitride layer 7 as a mask and a mixed solution of hydrogen peroxide and phosphoric acid as an etchant to form a highly doped silicon-doped n ⁺ InGaAs layer 6. Then, the silicon-doped n-AlGaAs layer 5 constituting the emitter layer is selectively removed sequentially. At this time, the etching time is lengthened so as to be slightly over-etched, and side etching is caused.

Thereafter, as shown in FIG. 2 (e), a 5000-nm-thick silicon oxide film is deposited by a plasma CVD method, and then etched by anisotropic etching to form an emitter electrode made of a s (AuGe / Au) alloy thin film. After the formation of the gate electrode 7, the emitter electrode 7 and the n ⁻ AlGaAs layer 4 are sequentially formed by photolithography.
Patterned and highly doped silicon doped n ⁺ In
GaAS layer 6, silicon-doped nAl constituting emitter layer
An over-etched portion of the side wall of the GaAs layer 5 is covered with a silicon oxide film 9.

Further, as shown in FIG. 2 (f), a 5 × 10 ¹⁹ / cm ³ zinc-doped GaAs layer 10 is epitaxially grown by MOCVD (metal organic chemical vapor deposition). At this time, the zinc-doped GaAs layer 10 grows only on the beryllium-doped p ⁺ AlGaAs layer 4 constituting the base layer, and does not grow on the tungsten nitride film 7 and the silicon oxide film 9.

Thereafter, as shown in FIG. 2 (g), a boron injection layer 11 and a proton injection layer 12 for element isolation and external base / collector insulation are formed.

Then, as shown in FIG. 2 (h), by the CVD method,
Forming a silicon oxide film 13 as a lift-off spacer, and further forming a resist pattern (not shown);
After forming the contact hole, an Au-Zn layer is vapor-deposited on the upper layer while the resist pattern is left, and the Au-Zn layer is patterned by a lift-off method. To form

Further, as shown in FIG. 2 (i), the silicon oxide film 13 as a lift-off spacer is removed, a resist pattern is formed by a photolithographic method, and using this as a mask, a mixture of a hydrogen peroxide solution and phosphoric acid is used. Perform wet etching using the solution as an etchant to form a zinc-doped GaAs layer 10.
Is selectively removed, and the high concentration silicon-doped n ⁺ GaAs layer 2 on which the collector electrode 16 is to be formed is exposed. At the same time, the high-concentration zinc-doped GaAs layer 10 between the elements having carriers that cannot be killed in the boron / proton ion implantation step is removed.

Further, as shown in FIG. 2 (j), after depositing a silicon oxide film 15 as a lift-off spacer, a resist pattern is formed by a photolithographic method, and after patterning the silicon oxide film 15, the resist pattern is left. The Au-Ge layer is deposited as it is, and the Au-Ge layer is
The layer is patterned, and a collector electrode 16 is formed through an alloying step at 360 ° C. for 40 seconds.

According to the HBT thus formed, an ohmic contact to the base region 4 which is a beryllium-doped p ⁺ AlGaAs layer is formed by a high carrier concentration (5 × 10 5) epitaxially grown on the p ⁺ AlGaAs layer. ¹⁹ / cm ³⁾
And is formed on the zinc-doped GaAs layer 10 which is convenient for obtaining a low-resistance ohmic contact, so that an ohmic contact resistance of about 1 × 10 ⁻⁷ Ωcm ² , which was impossible with the prior art, It is possible to obtain.

In addition, since the epitaxial growth is performed using the tungsten nitride film 7, which is a high melting point metal thin film, as a mask, the tungsten nitride film 7 does not react with the compound semiconductor even under high temperature conditions during the epitaxial growth step, and is stable. Will be maintained. Therefore, this tungsten nitride film 7 can be used as it is as an extraction electrode of the emitter layer.

Further, since the epitaxial growth layer is selectively formed using the tungsten nitride film 7 as a mask, the electrode formed on the epitaxial growth layer and the emitter electrode formed of the tungsten nitride film 7 are formed close to each other in a self-aligned manner. Will be. For this reason, the emitter electrode 7
To the base electrode 14 on the epitaxial growth layer, the parasitic resistance caused by the sheet resistance of the p ^- GaAlAs layer constituting the base region can be reduced.
Speed can be sufficiently brought out.

With this structure, the external base resistance is about 1 / 10-
It will be as low as 1/100.

Further, the maximum oscillation frequency f _MAX of the HBT is improved to about 150 GHz, compared with about 100 GHz in the past.

In the above-described embodiment, the heterojunction bipolar transistor has been described. However, the present invention is not limited to the heterojunction bipolar transistor but can be applied to the formation of a contact with another p-type compound semiconductor layer.

[Effects of the Invention] As described above, according to the present invention, when forming an ohmic contact of a compound semiconductor, a refractory metal layer pattern is formed on the surface of a substrate including a compound semiconductor region having an npn structure. Is used as a mask to expose the substrate surface to expose the p-layer. Further, using this pattern as a mask, a p-layer for ohmic contact of a desired concentration is selectively grown on the p-layer surface by an epitaxial growth method. Since a metal electrode is formed at a distance of 1 × 10
An ohmic contact of about ^-7 Ωcm ² can be obtained.

In the present invention, the metal electrode formed on the surface of the p-layer in this method is used as a first electrode, and the refractory metal layer pattern used as a mask for epitaxial growth is used as a second electrode.
, The first and second electrodes are formed in a self-aligned manner, and the element can be miniaturized.

[Brief description of the drawings]

FIG. 1 is a view showing an HBT according to an embodiment of the present invention, FIGS. 2 (a) to 2 (j) are views showing a manufacturing process of the HBT according to the embodiment of the present invention, and FIG. FIG. 1 .... non-doped gallium arsenide (GaAs) substrate, 2 .... n ⁺ Ga
As layer (collector region), 3 ... p ^- GaAs layer (base region),
4 ... n ^- AlGaAs layer (emitter region), 5 ... collector electrode,
6 base electrode, 6a Pt layer, 6b Zn layer, 6c WNx layer, 7
... Emitter electrode.

Claims (2)

(57) [Claims] 1. A semiconductor device comprising a first electrode on a p-layer surface exposed on a part of a substrate surface including a compound semiconductor region having an npn structure and a second electrode on an n-layer surface. The first electrode includes a p-layer for ohmic contact having a desired concentration epitaxially grown using the refractory metal layer pattern formed on the surface of the n-layer as a mask, and a conductor layer formed on the surface of the p-layer; The semiconductor device, wherein the second electrode is the high melting point metal layer pattern. 2. A high melting point metal layer pattern forming step of forming a high melting point metal layer pattern on a substrate surface including a compound semiconductor region having an npn structure, using the pattern as a mask, etching the substrate surface to expose a p layer. An exposing step, and further using the pattern as a mask, an epitaxial growth step of selectively growing a p-layer for ohmic contact at a desired concentration on the p-layer surface by an epitaxial growth method; and a metal electrode for forming a metal electrode on the p-layer surface. Forming a semiconductor device.