JPH02188964A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce an ohmic-contact resistance while a performance of an intrinsic active part is being maintained satisfactorily in a compound semiconductor device ot an n-p-n structure by a method wherein a p-layer for ohmic contact use is grown selectively on the surface of the p-layer by an epitaxial growth method and a metal electrode is formed on the surface of the p-layer. CONSTITUTION:In a semiconductor device, the following are provided: first electrodes 10, 14 on the surface of a p-layer 4 exposed in one part of the surface of a substrate including compound semiconductor regions 3 to 5 of an n-p-n structure; and a second electrode 7 on the surface of an n-layer 5. In this semiconductor device, said first electrodes 10, 14 are composed of the following: a desired-concentration p-layer 10, for ohmic contact use, which has been grown epitaxially by using a mask of a high-melting-point-metal layer pattern 7 formed on the surface of the n-layer 5; and a conductor layer 14 formed on the surface ot the p-layer 10. Said second electrode 7 is formed as the high-melting-point- metal layer pattern 7. For example, said second electrode 7 is formed as a WNx layer 7 which has been formed on an n-AlGaAs layer 5 via an n<+> InGaAS layer 6; and first electrodes 10, 14 are formed as a p<-> GaAs layer 10 and an AuZn layer 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to the formation of an ohmic contact to a p-type compound semiconductor layer.

[Conventional technology]

A petrojunction bipolar transistor, which is made by joining different semiconductor materials to form a heterojunction, has superior high frequency characteristics and switching characteristics compared to a homojunction bipolar transistor made using a single material, and is used as a microwave transistor, It is extremely promising as a transistor for high-1 logic circuits and a transistor for high-speed analog circuits.

However, due to manufacturing technology reasons such as the difficulty of forming a heterojunction with good interfacial properties and the extremely difficult formation of a multilayer thin film in which the doping depth of each layer is carefully controlled, development has been delayed. No progress was being made.

In recent years, with the development of superior epitaxy technologies such as molecular beam epitaxy (MBC) and metal-organic chemical vapor deposition (MOCVD), heterojunction bipolar transistors as ultra-high-speed devices are once again attracting attention. There is.

As an example of such a heterojunction bipolar transistor, as shown in the cross-sectional view of the structure in FIG.
'Collector region of GaAs layer 2 and pGaAs layer 2
A base region consisting of a layer 3 and an emitter region consisting of an n^1 GaAs layer 4 are sequentially laminated by the MBC method, and a collector electrode 5, a base electrode 6, and an emitter electrode 7 are formed on the surface of each region, respectively. has been done.

In such a heterojunction bipolar transistor, an electrode is formed on the base region made of the p GaAs layer 3 by etching the n layer of the compound semiconductor substrate having the npn structure. This is done by exposing the N (D GaAs layer 3) and depositing a metal layer such as a gold-zinc (AuZn) layer on its surface.

By the way, the impurity HrU of ptU is set to a condition that increases the performance of the intrinsic operation part of this transistor, and its value is about 5 x 10-/cm. On the other hand, the resistance of ohmic contact 1 to a p-type compound semiconductor decreases as the p-type carrier concentration increases.
A p-layer with an impurity concentration of 17 or more is required.

Similarly, for the purpose of improving the performance of the intrinsic operating part of a transistor, p-type compound semiconductors are used, for example, p-type (IAAs).
p-type Ga^IAs is often used instead of p-type Ga^IAs, but p
Desired GaA IAs often has a higher ohmic contact resistance to the Auzn layer than p-type GaAs.

For these two reasons, in the conventional heterojunction bipolar transistor, the contact resistance of the electrode for contacting the base region cannot be reduced, which is one of the major reasons for preventing high-speed operation.

This has been a factor that prevents improvements in performance such as high speed not only in heterojunction bipolar transistors but also in compound semiconductor devices in general, including electrode formation on p-type compound semiconductors.

That is, the high speed performance of such a compound semiconductor device is determined by the performance of the intrinsic operating portion of the semiconductor device and the magnitude of parasitic capacitance and parasitic resistance associated therewith. Especially nl)n4M
In the case of a built-in bipolar transistor, the size of the external base of the p-type base significantly affects high speed. by the way,
The external base resistance consists of two components: the sheet resistance of the base electrode and the ohmic contact resistance of the base electrode. For this reason, there has been a strong desire to form electrodes that can reduce ohmic contact resistance while maintaining good performance of the intrinsic operating portion.

(Problems to be Solved by the Invention) As described above, in the conventional npnli compound semiconductor device, it has not been possible to form a contact with low ohmic contact resistance while maintaining good performance of the intrinsic operating portion.

The present invention has been made in view of the above-mentioned circumstances, and provides an electrode formation in the p layer that can reduce the ohmic contact resistance while maintaining good performance of the intrinsic operating part in an npn patterned compound semiconductor device. The purpose is to provide a method.

Another object of the present invention is to miniaturize a compound semiconductor device having an npn structure.

(Structure of the Invention) (Means for Solving the Problems) Therefore, in the method of the present invention, a pattern made of a high melting point metal layer is formed on the surface of a substrate including an npnH compound semiconductor region, and this pattern is used as a mask to form a pattern. The substrate surface is etched to expose the p-layer, and using this pattern as a mask, an ohmic contact layer with a desired concentration is selectively grown on the p-layer surface by epitaxial growth, and a metal electrode is formed on the p-layer surface. I'm trying to form it.

Further, in the semiconductor device of the present invention, the metal electrode formed on the surface of the p layer in the above method is used as the first electrode, and the high melting point metal pattern used as a mask for epitaxy cell growth is used as the second electrode. ing.

<Function> According to the above structure, the formation of an ohmic contact to the p layer is convenient for obtaining an ohmic contact with a desired high xerium concentration and low resistance, which is epitaxially grown on the 9th layer. Since it is formed on a contact ρ-type compound semiconductor layer of a good type, it becomes possible to obtain an ohmink contact resistance of about 1X=7 1o Qc11, which was impossible with the conventional technology.

In addition, since epitaxial growth is performed using the high melting point metal +1 film as a mask, the high melting point metal thin film does not react with compound semiconductors and is maintained stably even under the stagnation conditions during the epitaxial cell growth process. Ru. Therefore, this refractory metal +1 film can be used as it is as an extraction electrode for the n-layer.

Furthermore, according to this apparatus, since the epitaxial growth layer is selectively formed using the high melting point thin film as a mask, the electrode formed on the epitaxial growth layer and the electrode made of the high melting point metal thin film are self-aligned. They will be formed close together. Therefore, the parasitic resistance caused by the sheet resistance of the p layer from the high melting point U film electrode to the electrode on the epitaxial growth layer can be reduced, and as a result, the high speed performance of the compound semiconductor device can be fully exploited. be able to.

In this way, by reducing the contact resistance and shortening the length of the p layer leading to the contact, it is possible to reduce the parasitic resistance caused by the sheet resistance.

(Example) Hereinafter, examples of the present invention will be described with reference to the drawings.
Explain to Tsuna.

FIG. 1 is a diagram showing a heterojunction bipolar transistor (HBT) according to an embodiment of the present invention, and FIGS.
h) is a manufacturing process diagram when the method of the present invention is applied to a heterojunction bipolar transistor 11 of one embodiment.

As shown in FIG. 1, this 118T is constructed in the same manner as the conventional HBT shown in FIG. 3, and constitutes a base region. - The formation of an ohmic contact to the GaAlAs layer is performed using a heavily Zn-doped p-p layer grown epitaxially using the tungsten nitride <14N
- through the GaAs1il^1J2r1 layer 10 (base electrode) and the tungsten nitride (1
4Nx) layer 7 is used as it is as an emitter electrode.

That is, first, as shown in FIG. 2 [a], a highly silicon-doped n'' GaAs layer 2 and a silicon-doped n'' GaAs layer 2 constituting the collector layer are formed on the surface of a chromium-doped n-type GaAs substrate 1 by MBE. Beryllium-doped p+ AlGaAs 11 forming the GaAs layer 3 and the base.
4 (beryllium concentration lx10''/ci), a silicon-doped n^1 GaAs decoy 5 constituting the emitter layer, and a highly silicon-doped n+InGaAs layer 6 are sequentially deposited.

After this, as shown in FIG. 2(b), tungsten nitride (
WNx) Deposit IW7.

Then, as shown in FIG. 2C, the resist film coated with the resist film is patterned by photolithography to form a resist pattern 8. Then, using this resist pattern 8 as a mask, the tungsten nitride layer 7 is patterned by reactive ion etching.

Next, as shown in FIG. 2(d), using the tungsten nitride layer 7 as a mask, etching is performed using a mixture of hydrogen peroxide and phosphoric acid as an edging agent to form a highly silicon-doped n'' InGaAsff16 emitter. Silicon-doped n^lGaAs1l forming the layer
5 are sequentially and selectively removed. At this time, the etching time is increased so that the etching is slightly overetched, and side etching is caused.

After this, as shown in FIG. 2(e), after depositing a silicon oxide film on the film 15000 by plasma CVD method,
S (AuGe
/^U) After forming the emitter electrode 7 made of an alloy thin film, the emitter electrode 7 and n A are formed by photolithography.
The lGaAs layer 4 is sequentially buttered, and then a highly silicon-doped n''InGaAsInGaAs layer 6 is formed.
The over-etched portion of the sidewall of the silicon-doped n AIGaAsfl 5 is covered with silicon oxide IFJ9
Cover with

Furthermore, as shown in FIG. 2(f), a zinc-doped GaAs layer 10 of 5×10”/cI! is epitaxially grown by MOCVD (metallic chemical vapor deposition). Layer 10 is made of beryllium-doped p'' AIGa constituting the base layer.
It grows only on the ASIifl 4 and does not grow on the tungsten nitride film 7 or the silicon oxide film 9.

Thereafter, as shown in FIG. 2(g), a poron injection layer 11 and a proton injection layer 12 for isolation between elements and external base/collector insulation are formed.

Then, as shown in FIG. 2(h), by CVD method,
After forming a silicon oxide film 13 as a lift-off spacer and further forming a resist pattern (not shown) to form a contact hole, a ^u-1n layer is formed on top of this while leaving this resist pattern. The ^u-2n layer was deposited and patterned by a lift-off method, and 36
The base electrode 14 is formed through an alloying process at 0° C. for 40 seconds.

Furthermore, as shown in FIG. 2m, the silicon oxide film 13 as a lift-off spacer is removed, a resist pattern is formed by photolithography, and this is used as a mask.
Wet etching was performed using a mixture of hydrogen peroxide and phosphoric acid as an etchant to form the zinc-doped GaAs layer 1.
By selectively removing 0, the top of the heavily silicon-doped n'' GaAs layer 2 on which the collector electrode 16 is to be formed is determined.

At the same time, the highly zinc-doped GaAs layer 10 between the elements, which has carriers that cannot be killed by the boron proton ion implantation step described above, is removed.

Furthermore, as shown in FIG. 2(j), after depositing a silicon oxide film 15 as a lift-off spacer, a resist pattern was formed by photolithography, and after patterning the silicon oxide film 15, the resist pattern was left. An Au--Ge layer is deposited as it is, and the u--Ge layer is patterned by a lift-off method, and a collector electrode 16 is formed through an alloying process of 360" and 040 seconds.

According to the HBT thus formed, the formation of an ohmic contact to the base region 4, which is a beryllium-doped p''AlGaAs layer, is achieved by forming a high carrier concentration (
5X 1019/ctrl> and is convenient for obtaining low resistance ohmic contacts.
s1l10, it becomes possible to obtain an ohmic contact resistance of about 1x100-, which was impossible with conventional technology.

Furthermore, since epitaxial growth is performed using the tungsten nitride film 7, which is a high melting point metal thin film, as a mask, the tungsten nitride film 7 does not react with compound semiconductors even under high temperature conditions during the epitaxial growth process. Maintained stably. Therefore, this tungsten nitride film 7 can be used as it is as a lead-out electrode for the emitter layer.

Furthermore, since the epitaxial growth layer is selectively formed using this tungsten nitride W17 as a mask, the electrode formed on this epitaxial growth layer and the emitter electrode made of the tungsten nitride film 7 are formed close to each other in self-alignment. It turns out. Therefore, the emitter electrode 7
to the base electrode 14 on the epitaxial growth layer. pGaAI^S comprising
It is possible to reduce the eccentric resistance caused by the sheet resistance of the decoy, and as a result, the high speed performance of H[3T can be fully exploited.

With this structure, the external base resistance is approximately 1/10 compared to the conventional one.
It becomes as low as ~1/100.

Furthermore, the maximum oscillation frequency f of the HBT is 100GHz4! i! 150Gl
Improved to about -12.

Note that although the above embodiments have been described with reference to a heterojunction bipolar transistor, the present invention is not limited to a heterojunction bipolar transistor, and can be applied to forming contacts to other p-type compound semiconductor layers.

(Effects of the Invention) As described above, according to the present invention, a high melting point metal layer pattern is formed on the surface of the substrate including the compound semiconductor region of the npn structure when forming an ohmic contact to the chemically proboscis-hemiprosthetic body. Using this pattern as a mask, the surface of the substrate is etched to expose PLH, and using this pattern as a mask, an 0 layer for ohmic contact with a desired concentration is selected on the surface of the p layer by the taxi V growth method. Since the gold li1 electrode is formed on the same surface of the p layer, it is possible to obtain an ohmic contact of about 1×10 Ωd, which was impossible with conventional techniques.

Furthermore, in the present invention, in this method, the metal electrode formed on the surface of the p layer is used as the first electrode, and the melting point metal layer pattern used as a mask for epitaxial growth is made to function as the second electrode. The first and 26th electrodes are formed in a self-aligned manner, making it possible to miniaturize the device.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the HBT according to the embodiment of the present invention, Figure 2 (a
) to FIG. 2(j) are diagrams showing the manufacturing process of the 1-IBT according to the embodiment of the present invention, and FIG. 3 is a diagram showing the HBT of the conventional example. 1...Non-doped gallium arsenide (GaAs) substrate, 2-n'' GaAs layer (collector region), 3-D
-GaAs layer (base region), 4...n^1GaA
s layer (emitter region), 5... collector electrode, 6...
・Base electrode, 6a...pt layer, 6b...2n layer,
6C...-NX layer, 7... Emitter electrode. Figure 1 Figure 2 (Part 1) Figure 2 (T' 2) Figure 2 (F 4) Figure 2 (T 3) Figure 2 (Part 5)

Claims (2)

[Claims] (1) In a semiconductor device having a first electrode on the surface of the p-layer exposed to a part of the surface of the substrate including a compound semiconductor region having an npn structure, and a second electrode on the surface of the n-layer, The first electrode consists of a p-layer for ohmic contact with a desired concentration epitaxially grown using a refractory metal layer pattern formed on the surface of the n-layer as a mask, and a conductor layer formed on the surface of the p-layer; A semiconductor device characterized in that the second electrode is the high melting point metal layer pattern. (2) A high melting point metal layer pattern forming step of forming a high melting point metal layer pattern on the substrate surface including a compound semiconductor region with an npn structure, and an exposure step of etching the substrate surface using this pattern as a mask to expose the p layer. an epitaxial growth step in which a p-layer for ohmic contact with a desired concentration is selectively grown on the surface of the p-layer by an epitaxial growth method using this pattern as a mask; and a metal electrode formation step in which a metal electrode is formed on the surface of the p-layer. A method for manufacturing a semiconductor device, comprising: