JPH0536709A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To miniaturize an element by selectively etching a predetermined indium arsenide.aluminum layer with respect to an indium arsenide.gallium layer by using etchant mixture solution containing hydrogen bromide and phosphoric acid. CONSTITUTION:A subcollector layer 2 made of InGaAs, a collector layer 3, a base layer 4, an emitter layer 5 made of InAlAs and an emitter contact layer 6 are sequentially grown on a semiinsulating InP substrate wafer 1, and an etching mask 7 is formed. Then, the layer 6 and the layer 5 are etched by a mixture etchant solution of phosphoric acid, hydrogen peroxide and water, and the layer 5 remains only in thickness 6. Here, etchant containing 1: 1 of hydrobromic acid and phosphoric acid in mixture, is prepared, and the side of the layer 5 is etched. Then, an emitter mesa of a reverse mesa shape is formed, and the layer 5 of the thickness delta is completely etched without reducing the thickness of the layer 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high performance and miniaturization of a semiconductor device made of indium gallium arsenide and indium arsenide aluminum on an indium phosphide semiconductor substrate.

[0002]

2. Description of the Related Art Electronic devices made of compound semiconductors are widely used as ultra-high speed / ultra high frequency devices and ultra low noise devices. Although gallium arsenide (GaAs) is most often used as a semiconductor material, an indium phosphide (InP) substrate that realizes higher performance devices as the required frequency region shifts from microwaves to millimeter waves is used. It is expected that the demand for semiconductor devices will continue to increase. The next generation I
Indium gallium arsenide (InGaAs) and indium aluminum arsenide (InAlAs) are typical semiconductors lattice-matched to the nP substrate. These semiconductor materials have the following features. InGaAs
Has a large electron mobility and is excellent as a material for an active layer of a semiconductor device, and has a small energy band gap (0.
Since it is 75 eV), it is excellent in ohmic contact with the metal electrode. InAlAs is 1.45 eV and InGaAs
Since it has a large energy forbidden band width about twice that of, it is used as an effective energy potential barrier layer for carriers in InGaAs. InP is also used as the energy potential barrier layer. Actually, from the viewpoint of the manufacturing process, for example, the method of independently etching each material is established.
nP / InGaAs-based heterojunction is better than InAlAs /
There are some aspects that are easier to handle than the InGaAs-based heterojunction.
However, depending on the semiconductor device, the heterojunction FE
InAl, which has a larger electron confinement effect like T
As may be selected. Further, the molecular beam epitaxy method (MBE), which is widely used as a crystal growth method, has an advantage that various characteristics of a semiconductor material can be uniformly grown as compared with the metal organic chemical vapor deposition method (MOCVD), but Since MBE cannot introduce a phosphorus-based source, InAlAs is often selected as a wide bandgap material over InP. InAlAs /
InP / InGaAs is used for the InGaAs heterojunction.
Since there are many advantages that the system heterojunction does not have, the development of the process technology of the same material is desired.

InA will be described below with reference to FIGS. 4 and 5.
As a conventional example of a method for manufacturing a 1As / InGaAs heterojunction device, a heterojunction bipolar transistor (H
BT) will be described as an example. In FIG. 4A, n ⁺ − is formed by MBE on the semi-insulating InP substrate wafer 1.
InGaAs (silicon impurity doping concentration: 1 × 1
0 ¹⁹ cm ^-3) Thickness 5000 Å subcollector layer ² made of, n - -InGaAs (silicon impurity doping concentration: Thickness consisting 5 × 10 ¹⁶ cm ^-3) 5
000 Å collector layer 3, p ⁺ -InG
aAs (Beryllium impurity doping concentration: 4 × 10 ¹⁹
cm ^-3 ), a base layer 4 having a thickness of 500 angstroms, an N-InAlAs (silicon impurity doping concentration: 5 × 10 ¹⁷ cm ^-3 ) emitter layer 5 having a thickness of 3,000 angstroms, and n ⁺ -InGaAs (silicon impurity doping concentration). The emitter contact layer 6 having a thickness of 2000 angstroms, which is made of 1 × 10 ¹⁹ cm ⁻³ ), is sequentially grown. Next, after forming a 2000 angstrom silicon oxide film on the wafer, by reactive ion etching (RIE) using CF ₄ gas,
An etching mask 7 for processing the emitter mesa is formed.

Next, in FIG. 4B, the emitter cap layer 6 and the emitter layer 5 are etched with a mixed etching solution of phosphoric acid, hydrogen peroxide and water to expose the base layer 4. Since this etching solution etches InAlAs and InGaAs at substantially the same etching rate, the utmost care must be taken not to attack the base layer 4.

Next, in FIG. 4C, a photoresist 9 defines a base electrode region, and titanium (Ti), platinum (Pt), and gold (Au) are added to 500, 500, and 1000, respectively.
Angstroms are sequentially deposited to lift off unnecessary metal films.

Next, in FIG. 5D, a photoresist 9 is applied to the wafer to planarize it, and then a TiPtAu metal film is deposited on the head of the emitter by RIE using a mixed gas of CF ₄ and oxygen. Exposed and removed by argon ion milling 12.

Next, in FIG. 5E, the oxide film 7 is removed, a TiPtAu metal film is vapor-deposited again on the emitter contact layer 6, and unnecessary metal films are lifted off. Finally,
The HBT is completed by exposing the sub-collector layer 2 to form the collector electrode 10c and depositing a TiPtAu electrode by a lift-off method.

[0008]

In the above HBT manufacturing method, since the base electrode 10b is formed in a self-aligned manner with respect to the emitter electrode 10e, parasitic resistance and parasitic capacitance are reduced in the entire device, and high frequency characteristics are reduced. Contribute to improving. The current gain cutoff frequency (f _T ) which is one of the indicators of the high frequency characteristics of the bipolar transistor is expressed as follows.

[0009]

[Equation 1]

[0010]

In order to improve f _T , R in equation 1
_EE, to reduce the parasitic resistance, such as R _C, the base layer, _B tau by thinning the active layer, such as the collector layer, it is necessary to reduce the tau _C. Since τ _C and C _bc have a trade-off relationship with respect to the thickness of the collector layer, there is a limit to thinning the collector layer. Therefore, it is necessary to make the base layer as thin as possible to reduce τ _B. However, conventional InAlAs / I
In the nGaAs HBT manufacturing method, as the thickness of the base layer becomes thinner, it becomes difficult to stop the etching just at the InGaAs / InAlAs heterojunction interface. InAlAs remaining on the surface of the base layer due to insufficient etching
The layer increases the contact resistance of the base electrode. Also,
When the etching reaches the base layer, the external base layer is thinned to increase the base resistance, or in the extreme case, the remaining base layer is completely depleted.

InAlAs / InGaAs HB
In order to reduce the power consumption of T, the operating collector current I _C of the HBT must be reduced. Figure 5
As shown in (e), the charging time of 1 even with a small operating current, in order not to increase the _{r e (C bc + C be} ) , especially C _BE, hence the base-emitter junction area size W2 (in the figure It is necessary to make 11b) as small as possible.
In the conventional manufacturing method, when the etching mask is made small in order to miniaturize the emitter, the size W1 of the region where the emitter electrode 10e contacts the emitter contact layer 6 is reduced.
(11a in the figure) becomes smaller than W2, and the emitter resistance R _EE increases, resulting in deterioration of f _T.

In view of the above problems, the object of the present invention is to
It is possible to stop the etching of the InAlAs layer at the InGaAs layer in the process in which the InAlAs layer of the semiconductor device using the nAlAs / InGaAs heterojunction must be etched with extremely high accuracy, and the InAlAs / InGaAs HBT The purpose is to miniaturize the device without sacrificing high-frequency performance.

[0014]

SUMMARY OF THE INVENTION The present invention provides a multi-layered thin film structure in which semiconductor layers of indium gallium arsenide and indium arsenide aluminum which are lattice-matched to indium phosphide are stacked on an indium phosphide semiconductor substrate. The method for manufacturing a semiconductor device having the above-mentioned method further includes the step of selectively etching a predetermined indium arsenide / aluminum layer with respect to the indium arsenide / gallium layer using an etching liquid mixture of hydrogen bromide and phosphoric acid. To do.

The present invention also provides a collector layer, a collector layer, and a collector layer made of indium gallium arsenide and indium arsenide aluminum which are lattice-matched to indium phosphide on an indium phosphide semiconductor substrate having a (001) crystal orientation.
In a method for manufacturing a heterojunction bipolar transistor in which main layers of a base layer, an emitter layer, and an emitter contact layer are sequentially stacked, and particularly, the emitter contact layer and the emitter layer are each made of indium gallium arsenide and indium aluminum arsenide. A longitudinal direction of a predetermined etching protection film that defines the emitter region is a [110] direction, at least the step of etching the emitter contact layer with the etching protection film, and then an etching mixture containing hydrogen bromide and phosphoric acid. Is used to etch the emitter layer made of indium aluminum arsenide.

[0016]

The etching mixture of hydrogen bromide and phosphoric acid is an etchant having a material selectivity that etches only InAlAs and does not attack InGaAs. Therefore, even if the InGaAs layer below the InAlAs layer to be etched is extremely thin, In, the etching can be stopped with good controllability. Further, since this etching mixed solution also has a crystal orientation dependency, it is possible to select a forward mesa shape or an inverted mesa shape for the etching cross section by selecting the direction of the etching mask. When a (001) InP substrate is used and the longitudinal direction of the emitter is set to [110], the emitter mesa has an inverted mesa shape, and the emitter electrode contact area W2 can be made larger than the base-emitter junction area W1. As a result, the device can be miniaturized without degrading f _T of HBT.

[0017]

EXAMPLE An example of the present invention will be described with reference to FIGS. All HBT cross-sections shown in Figure 1 are (110)
It is a crystal plane. In FIG. 1A, MB is formed on the semi-insulating InP substrate wafer 1 having the (001) crystal orientation.
A sub-collector layer 2 made of n ⁺ -InGaAs (silicon impurity doping concentration: 1 × 10 ¹⁹ cm ^-3 ) and having a thickness of 5000 Å, and n ⁻ -InGaAs
(Silicon impurity doping concentration: 5 × 10 ¹⁶ cm ⁻³ )
A collector layer 3 of 5000 Å in thickness, a base layer 4 of p ⁺ -InGaAs (beryllium impurity doping concentration: 4 × 10 ¹⁹ cm ⁻³ ) and a thickness of 500 Å, and N-InAlAs (silicon impurity doping concentration: 5 × 10 5). ¹⁷ cm ⁻³ ), 3000 Å thick emitter layer 5, n ⁺ -In
GaAs (silicon impurity doping concentration: 1 × 10 ¹⁹
cm ⁻³ ) and the emitter contact layer 6 having a thickness of 2000 angstroms is successively grown. Next, after forming a 2000 angstrom silicon oxide film on the wafer, an etching mask 7 for processing the emitter mesa is formed by reactive ion etching (RIE) using CF ₄ gas. Here, the longitudinal direction of the emitter is selected to be the [110] direction.
The cross-sectional view of BT represents a cross-sectional view of the etching stripe divided horizontally.

Next, in FIG. 1B, the emitter cap layer 6 and the emitter layer 5 are etched by a mixed etching solution of phosphoric acid, hydrogen peroxide and water to expose the base layer 4, or the emitter layer 5 is exposed. Not completely removed, thickness δ
You may leave only (indicated by 8 in the figure). In this example, since the base layer 4 is a relatively thin layer of 500 angstrom, the allowable amount of overetching in the etching for exposing the base layer is extremely small. Therefore, here, δ is set to 500 Å to avoid the risk of etching a part of the thickness of the base layer 4 beyond the etching stop point. Next, in FIG. 1C, an etching solution (hereinafter abbreviated as HBr etchant) is prepared by mixing hydrobromic acid (HBr) and phosphoric acid (H ₃ PO ₄ ) at a ratio of 1: 1. At a liquid temperature of 25 ° C., an etching rate of 2700 Å / min can be obtained. Therefore, when the side surface of the emitter layer 5 is etched for 1 minute using this,
At the same time that an inverted mesa-shaped emitter mesa is formed, the emitter layer 5 having the thickness δ that was left previously is also completely etched and the base layer 4 is exposed. Since the HBr etchant does not etch InGaAs at all, the base layer 4 does not become thin, and the emitter contact layer 6 and the emitter layer 5 do not become thin.
On the other hand, a T-shaped emitter is formed, which remains as an eaves shape. The oxide film 7 on the emitter contact layer 6 is removed by buffered hydrofluoric acid. Next, FIG. 2 (d)
In, a base electrode region is defined by a photoresist 9, titanium (Ti), platinum (Pt), and gold (Au) are sequentially deposited in a thickness configuration of 500, 500, and 1000 angstroms, respectively, and an unnecessary metal film is lifted off. . In this embodiment, the TiPtAu electrode 10 deposited in this step is formed on the emitter contact layer 6 and the base layer 4 at the same time. Since the emitter layer 5 is under the eaves of the emitter contact layer 6, the emitter and the base are not electrically short-circuited. Finally, in FIG. 2E, the HBT is completed by exposing the subcollector layer 2 to provide the collector electrode 10c and depositing a TiPtAu electrode by a lift-off method.

As can be seen from FIG. 2E, in the HBT of this embodiment, the size W2 (11b in the figure) of the base-emitter junction region is the region where the emitter electrode 10e contacts the emitter contact layer 6. Size W1 (1 in the figure
It is smaller than 1a) and has a relationship of W1> W2.
This corresponds to the conventional InAlAs / shown in FIGS.
This is in contrast to the relationship of W1 <W2 in the InGaAs HBT. Therefore, the HBT manufacturing method of the present invention utilizes the property that the HBr etchant does not etch InGaAs, and the emitter resistance R
It is possible to reduce the size of the base-emitter junction region without increasing the _EE . Further, both the base electrode and the emitter electrode can be simultaneously formed by utilizing the shape of the T-shaped emitter, so that the manufacturing process is reduced. further,
In the etching process for exposing the base layer, even if the uppermost surface of the base layer is not strictly exposed, the exposure of the base layer 4 is completed when the T-type emitter is formed by using the HBr / H ₃ PO ₄ mixed etchant. Will stop automatically.

In the embodiment shown in FIGS. 1 and 2, the emitter layer 5 made of InAlAs was left with a thickness δ = 500 angstroms in the etching process for forming the emitter mesa, but this reduces the etching amount by the HBr etchant as much as possible. This is because the eaves of the shaped emitter are not unnecessarily enlarged. However, the δ value is not particularly limited to this value, and for example, the thickness of all emitter layers may be left.

In the above embodiment, the InAlAs emitter layer having a relatively large thickness of 3000 angstrom is laterally etched into the InGaAs emitter contact layer 6 for the purpose of separating the base electrode and the emitter electrode. However, a thin InAlAs emitter layer having a thickness of, for example, 800 angstrom may be employed, and in the embodiment shown in FIG. 3, the base electrode 10b and the emitter electrode 10e are separated by the side wall 13 made of a nitride film (SiN _x ). The advantage of this structure is that δ = 5 as the thickness of the InAlAs to be left as in the embodiment shown in FIGS. 1 and 2.
The point is that it is not necessary to control the delicate value of 00 Å. That is, if the InGaAs emitter contact layer 6 is etched using, for example, reactive ion etching (RIE) using CH ₃ Br gas,
Since the etching stops at the InAlAs emitter layer 5, only the remaining thin InAlAs layer may be etched with the HBr etchant.

In the above embodiment, the HBr etchant is hydrobromic acid (HBr), phosphoric acid (H ₃ PO ₄ ) 1:
The etching liquid was mixed at a ratio of 1, but the mixing ratio of the etchant to which the present invention is applied is not limited to the ratio of 1: 1. Since the etching selectivity of InAlAs and InGaAs does not depend on the mixing ratio but only the etching rate of InAlAs changes, the optimum mixing ratio may be adopted depending on the structure of the semiconductor device. As an example of the present invention, InA
Although the lAs / InGaAs HBT is taken up, the semiconductor device which is the subject of the present invention is not limited to the heterojunction bipolar transistor, and a hot electron transistor, a heterojunction field effect transistor, a heterojunction metal insulation using an InAlAs / InGaAs heterojunction is used. Membrane gates and transistors are also covered.

[0023]

According to the method of manufacturing a semiconductor device according to the present invention, HBr / H ₃ PO ₄ is used in the step where the InAlAs layer must be etched with extremely high accuracy.
By using a mixed etchant, the etching
It is possible to automatically stop at the nGaAs layer.
For example, when applied to InAlAs / InGaAs HBT, the base layer can be easily exposed even with an ultrathin base layer.

The crystal orientation dependence of the etchant and I
Taking advantage of the etching selectivity between nAlAs and InGaAs, InAlAs / with a T-shaped emitter
As a result of forming the InGaAs HBT, it becomes possible to miniaturize the size of the emitter junction region without sacrificing the high frequency characteristics of the device.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a manufacturing process of an HBT according to the present invention.

FIG. 2 is an explanatory view showing a manufacturing process of an HBT according to the present invention.

FIG. 3 is an explanatory view showing an HBT manufactured by the manufacturing method of the present invention.

FIG. 4 is an explanatory view showing a manufacturing process of a conventional HBT.

FIG. 5 is an explanatory view showing a manufacturing process of a conventional HBT.

[Explanation of symbols]

1 semiconductor substrate 2 sub-collector layer 3 collector layer 4 base layer 5 emitter layer 6 emitter cap layer 7 insulating film 8 InBr to be etched with HBr etchant
Thin film of lAs layer 9 Photoresist 10, 10b, 10c, 10e Electrode metal 11a Size of contact region between emitter electrode and emitter contact layer 11b Size of junction region between emitter and base 12 Argon ion 13 Side wall of insulating film

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a multi-layered thin film structure, comprising a semiconductor layer of indium gallium arsenide and indium arsenide aluminum, each of which is lattice-matched with indium phosphide, stacked on an indium phosphide semiconductor substrate. A method of manufacturing a semiconductor device, comprising the step of selectively etching a predetermined indium arsenide / aluminum layer with respect to an indium arsenide / gallium layer using an etching liquid mixture of hydrogen bromide and phosphoric acid. 2. A collector layer, a collector layer, a base layer, an emitter layer, and an emitter which are made of indium gallium arsenide and indium aluminum arsenide lattice-matched to indium phosphide on an indium phosphide semiconductor substrate having a (001) crystal orientation. The main layers of the contact layer are sequentially laminated, and in particular, the emitter contact layer and the emitter layer are formed of indium gallium arsenide and indium arsenide.
A method of manufacturing a heterojunction bipolar transistor made of aluminum, wherein a longitudinal direction of a predetermined etching protection film defining an emitter region is a [110] direction, and at least the emitter contact layer is etched by the etching protection film; And then etching the emitter layer made of indium arsenide aluminum using an etching mixture of hydrogen bromide and phosphoric acid.