JP4558161B2 - Method for manufacturing heterojunction bipolar transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is made such group III-V compound semiconductor, it relates to high-speed operation characteristics method for producing superior heterojunction bipolar transient scan data in (frequency characteristics).
[0002]
[Prior art]
Heterojunction bipolar transistors made of III-V compound semiconductors are attracting attention not only as high-power electronic devices but also as ultrahigh-speed electronic devices for microwaves, millimeter waves, or ultrahigh-speed optical communications. In general, a heterojunction bipolar transistor has an element structure in which a subcollector layer, a collector layer, a base layer, and an emitter layer are sequentially stacked on a semiconductor substrate, and the emitter layer is processed into a mesa shape. The emitter electrode is formed on the emitter cap layer. The base electrode is formed on the base layer on the side of the emitter forming the mesa. The collector electrode is formed on the subcollector layer.
[0003]
There is a maximum oscillation frequency fmax as one index of high-speed operation characteristics. The maximum oscillation frequency fmax is a frequency at which the power gain is 1, and is expressed by the following equation (1).
fmax = √ (fT / (8πRb · Cbc)) (1)
Here, fT is a frequency at which the current gain becomes 1, that is, a cutoff frequency. Rb is a resistance parasitic to the base, and Cbc is a junction capacitance parasitic between the base and the collector. Therefore, as is clear from the above equation (1), it is important to reduce the parasitic resistance Rb and the parasitic capacitance Cbc in order to ensure the high-speed operation characteristics of the heterojunction bipolar transistor, that is, to increase the maximum oscillation frequency fmax. is there.
[0004]
Conventionally, as a method of reducing the parasitic capacitance Cbc, in a GaAs-based heterojunction bipolar transistor, a region under the mesa-type emitter layer of the base layer (hereinafter referred to as an external base region) is excluded. A method is known in which oxygen or hydrogen is ion-selectively ion-implanted into a collector portion and a sub-collector portion that are located. This is because the lower part of the external base region is semi-insulated by ion implantation to increase the resistance, thereby reducing the substantial junction area between the base and the collector and reducing the base-collector parasitic capacitance Cbc. It is.
[0005]
In addition, in an InP heterojunction bipolar transistor, it is difficult to increase resistance by ion implantation as in GaAs. Therefore, a method of reducing the parasitic capacitance Cbc by selectively etching away the subcollector portion located under the external base region and embedding an undoped semiconductor layer in this removed region is known.
[0006]
The parasitic capacitance Cbc described above is a base-collector capacitance that is reverse-biased when the heterojunction bipolar transistor is driven with the grounded emitter, that is, p acting as a parallel plate capacitor when the intrinsic collector layer is depleted. It appears as a capacitance between the type base layer and the n-type subcollector layer and is expressed by the following equation (2).
Cbc = εS · Sbc / dc (2)
Where εS is the dielectric constant of the collector layer, Sbc is the base-collector junction area, and dc is the thickness of the collector layer. Specifically, the relative permittivity (εS / ε0) of the compound semiconductor forming the collector layer with respect to the dielectric constant ε0 of air is about 11 to 13, which is 13.2 for GaAs and 12.4 for InP.
[0007]
[Problems to be solved by the invention]
However, in the above-described method of implanting ions into the collector portion and sub-collector portion under the external base region, the semiconductor layer is damaged by the implanted ions, leading to an increase in resistance Rb parasitic on the base. Therefore, even if the parasitic capacitance Cbc can be reduced, there is a concern that the maximum oscillation frequency fmax cannot be increased as shown in the equation (1).
[0008]
Further, in the above-described method of etching the sub-collector portion under the external base region, it is difficult to remove the portion directly under the external base region with good controllability due to factors such as misalignment of the etching mask, and the parasitic capacitance is sufficient. There is a problem that it cannot be removed.
[0010]
The present invention has been made in view of the above problems , and is capable of manufacturing a heterojunction bipolar transistor with improved controllability by reducing the parasitic capacitance Cbc between the base and the collector and improving the maximum oscillation frequency fmax. It is providing the manufacturing method for doing.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a heterojunction bipolar transistor according to the present invention includes forming a collector region by removing a part of a subcollector layer and a collector layer stacked on a substrate by etching, and a buffer layer. A buried region made of a compound semiconductor containing Al is grown on the exposed portion. The steps so far are performed in the same growth apparatus. Then, after forming the base layer, the mesa-shaped emitter region, the emitter electrode, and the base electrode, the buried region is oxidized to form an insulating region having a lower dielectric constant than the collector region, and a collector electrode is further formed. It is a thing.
[0014]
According to the present invention, since an insulator made of a compound obtained by oxidizing a compound semiconductor containing Al is formed under the external base region without performing ion implantation, the parasitic capacitance Cbc between the base and the collector is reduced. In addition, a heterojunction bipolar transistor having an improved maximum oscillation frequency fmax can be manufactured. Further, in order to perform the stacking of the buffer layer, the subcollector layer and the collector layer on the substrate, the etching of the subcollector layer and the collector layer, and the growth of the buried region made of the compound semiconductor containing Al in the same growth apparatus, Since the surface of the semiconductor layer can be prevented from being oxidized, a favorable film can be formed. Moreover, the trouble of removing the oxide film generated on the surface of the semiconductor layer can be saved.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Will be explained below in detail with reference to FIGS. 1-8 embodiments of heterojunction bipolar transitional scan data producing method according to the present invention.
[0016]
FIG. 1 is a perspective view showing an example of the structure of a heterojunction bipolar transistor manufactured by the method of manufacturing a heterojunction bipolar transistor according to the present invention, and FIG. 2 is a longitudinal section taken along a cutting line II-II in FIG. FIG.
In this heterojunction bipolar transistor, a buffer layer 2 is stacked on a substrate 1, and a subcollector region 3 is formed on a partial region of the buffer layer 2. An insulating region 4 is formed on the remaining region of the buffer layer 2.
[0017]
A collector contact layer 5 is stacked on the subcollector region 3, and a collector region 6 is formed on a partial region of the collector contact layer 5. A collector electrode 7 is formed on the remaining region of the collector contact layer 5. A cap layer 8 is laminated on the insulating region 4, and a base layer 9 is laminated on the cap layer 8 and the collector region 6.
[0018]
An emitter region 10 is formed on the base layer 9, and a base electrode 11 is formed so as to surround the periphery thereof. A part of the base electrode 11 is located above the insulating region 4. That is, the insulating region 4 is below a part of the external base region. The emitter region 10 and the base electrode 11 are insulated from each other by an insulator such as SiN or polyimide (not shown). An emitter electrode 12 is formed on the emitter region 10. In FIG. 1 and FIG. 2, reference numeral 13 denotes a metal layer laminated together with the base electrode 11.
[0019]
The substrate 1 is not particularly limited, but is, for example, a semi-insulating InP substrate having a (100) plane as a main surface. The buffer layer 2 is made of a compound semiconductor containing Al, for example, InAlAs. The subcollector region 3 is made of, for example, InP containing a high concentration of n-type impurities, and has the function of improving the heat dissipation characteristics and lowering the collector resistance. The collector contact layer 5 is an InGaAs thin film containing, for example, a high concentration of n-type impurities, and has a function of bringing the collector electrode 7 into ohmic contact with the subcollector region 3. The collector region 6 is made of, for example, intrinsic InP not doped with impurities.
[0020]
The insulating region 4 is made of a compound formed by oxidizing a compound semiconductor containing Al, for example, a compound formed by oxidizing intrinsic InAlAs. The cap layer 8 is made of, for example, InP, and is provided to prevent the surface of the element being manufactured during the manufacturing process from being oxidized. Base layer 9 is made of, for example, GaAsSb containing a high concentration of p-type impurities. The emitter region 10 is made of a material having a band gap larger than that of the base layer 9, for example, an emitter layer made of n-type InAlAs and an emitter cap layer made of n-type InGaAs. The emitter electrode 12 and the base electrode 11 are made of a laminated body such as WSi or Ti / Pt / Au, for example. The collector electrode 7 is made of a laminated body such as Ti / Pt / Au.
[0021]
Although not shown, the heterojunction bipolar transistor configured as shown in FIGS. 1 and 2 is covered with an interlayer insulating film made of an insulator such as SiN or polyimide. Then, wirings made of a laminate of Ti / Pt / Au or the like are connected to the collector electrode 7, the base electrode 11 and the emitter electrode 12 through contact holes opened in the interlayer insulating film, respectively, and the outermost surface thereof is passivation. Covered by a membrane.
[0022]
Next, an example of a method for manufacturing the heterojunction bipolar transistor having the configuration shown in FIGS. 1 and 2 will be described with reference to FIGS.
[0023]
First, a compound semiconductor having a (100) plane as a main surface, for example, a wafer made of semi-insulating InP is placed in a growth apparatus, and a metal organic chemical vapor deposition (MOCVD) method or a molecule is formed on a substrate 1 made of the wafer. The buffer layer 2 made of, for example, InAlAs is epitaxially grown using a line epitaxy (MBE) method. Similarly, for example, a sub-collector layer 31 made of InP containing high-concentration n-type impurities, a collector contact layer 51 made of InGaAs containing high-concentration n-type impurities, and an intrinsic dopant not doped with impurities. A collector layer 61 made of InP is epitaxially grown in order. The state up to here is shown in FIG.
[0024]
Subsequently, a layer made of a dielectric material such as SiN is stacked on the collector layer 61, and a resist is applied thereon. Then, the resist film is patterned by a photolithography technique, and a layer made of SiN or the like is dry-etched using the remaining resist portion as a mask to form a selective growth mask 201.
[0025]
Using this selective growth mask 201, the inside of the growth apparatus is controlled to 70 Torr (93.3 hPa), and a gas such as PH ₃ is flowed at a flow rate of about 500 sccm, and the temperature is raised to, for example, 600 ° C. near the growth temperature. Then, while flowing a gas such as PH ₃ , a methane compound containing chlorine or bromine, for example, carbon tetrabromide (CBr ₄ ) is simultaneously flowed at a flow rate of about 50 to 100 sccm, and the collector layer 61, the collector contact layer 51, and The subcollector layer 31 is etched. As a result, the subcollector region 3, the collector contact layer 5, and the collector layer 62 are formed under the selective growth mask 201 as shown in FIG.
[0026]
In this etching, InAlAs constituting the buffer layer 2 is hardly etched by CBr _4. Therefore, the InP constituting the subcollector layer 31 and the collector layer 61 and the collector contact layer 51 can be obtained without specially managing the etching time. Only InGaAs that constitutes is selectively etched and removed. Note that HCl can be used as an etching gas instead of CBr ₄ .
[0027]
In that case, since InAlAs is also etched, it is necessary to control the etching time so that only InP and InGaAs are etched.
In addition, as an etching gas, a gas containing another halogen element (for example, CCl ₄ or Cl ₄ gas) or a gas having a different number of halogen elements (for example, CH _x Br _4-x (x = 1, 2, 3). )) Etc. can also be used.
[0028]
Subsequently, a buried region 41 made of, for example, InAlAs is selectively grown on the surface of InAlAs exposed by the above-described etching until the height of the interface between the selective growth mask 201 and the collector layer 62 is increased. In order to prevent oxidation, a cap layer 81 made of, for example, an InP thin film for preventing oxidation is grown on the surface of the buried region 41.
[0029]
During the growth of the buried region 41, an etching gas such as CBr ₄ is supplied at a flow rate of about 10 sccm, for example. This is in order not to impair the removability when removing the selective growth mask 201 later. The state up to here is shown in FIG. The process from the step of growing the buffer layer 2 on the substrate 1 to the step of growing the cap layer 81 is performed in the same growth apparatus.
[0030]
Subsequently, the wafer is taken out from the growth apparatus, and the selective growth mask 201 is removed by BHF or the like. Thereafter, the wafer is again put in the growth apparatus, and the base layer 91 made of, for example, GaAsSb containing high-concentration p-type impurities and the emitter layer 101 are grown at a growth temperature of about 530 ° C. across the surfaces of the collector layer 62 and the cap layer 81. Grow in order. The emitter layer 101 includes, for example, an emitter layer portion made of n-type InAlAs and an emitter cap layer portion made of n-type InGaAs. The state up to this point is shown in FIG.
[0031]
Subsequently, an emitter electrode made of a laminated body of WSi or Ti / Pt / Au is selectively formed on the emitter layer 101 by using a technique such as lift-off. Then, using this emitter electrode as a mask, the InGaAs of the emitter cap layer is selectively wet-etched using, for example, a mixed solution of sulfuric acid, hydrogen peroxide solution, and water to expose the InAlAs emitter layer. At this time, the InAlAs emitter layer is not etched, but the InGaAs emitter cap layer is side-etched laterally by the same length as the depth etched in the direction perpendicular to the substrate 1 (that is, the longitudinal direction). .
[0032]
Thereafter, the base layer 91 is exposed by selectively wet etching the InAlAs of the emitter layer using, for example, a mixture of hydrochloric acid and water. The GaAsSb of the base layer 91 is not etched. By etching the emitter layer 101 in this manner, a mesa-shaped emitter, that is, an emitter mesa is formed as shown in FIG. In FIG. 7, reference numeral 10 denotes an emitter region, and reference numeral 12 denotes an emitter electrode.
[0033]
Subsequently, as shown in FIG. 7, a laminated body such as WSi or Ti / Pt / Au is deposited on the exposed base layer 91 and the emitter mesa to form the base electrode layer and the metal layer 13. Thereafter, the base electrode layer is processed by a method such as ion milling using a dummy mask 211 such as SiO _x to form the base electrode 11. The state up to this point is shown in FIG.
[0034]
Subsequently, the base layer 91, the cap layer 81, the collector layer 62, and a part of the buried region 41 are removed by, for example, dry etching, and a part of the collector contact layer 5 is selectively exposed. By this etching, the base layer 9, the collector region 6 and the cap layer 8 are formed.
[0035]
Next, InAlAs in the buried region 41 is selectively oxidized by a method of heating while flowing water vapor in an oxidation furnace. As a result, the remaining portion of the buried region 41 becomes the insulating region 4. At this time, since only the portion containing Al is selectively oxidized to become an insulator Al _x In _1-x O _y , it is not necessary to manage the oxidation time so much. The state up to this point is shown in FIG.
[0036]
Here, the formation of the isolation mesa is not necessarily performed. The reason for this is that when the buried region 41 is oxidized, the buffer layer 2 made of InAlAs is exposed, so that the vicinity of the surface of the buffer layer 2 is oxidized together with the oxidation of the buried region 41 and is insulated to increase the resistance. is there. It should be noted that the isolation mesa may be formed by etching to the semi-insulating substrate 1 or by ion implantation to the semi-insulating substrate 1 as is conventional.
[0037]
Subsequently, the dummy mask 211 is removed, and the collector electrode 7 made of a laminate of Ti / Pt / Au or the like is formed on the exposed portion of the collector contact layer 5 by a lift-off method or the like (see FIG. 2). Thereafter, although not particularly shown, the entire element is filled with an insulator such as SiN or polyimide, contact holes are opened in the respective electrode portions, and a laminated body such as Ti / Pt / Au is wired as a lead electrode, thereby forming an emitter mesa. A heterojunction bipolar transistor having a structure is completed.
[0038]
According to the above-described heterojunction bipolar transistor , the lower portion of the external base region is the insulating region 4 made of Al _x In _1-x O _y, so the heterojunction bipolar transistor in which the collector region 6 is made of InP. Without sacrificing the device characteristics, the parasitic capacitance Cbc between the base and the collector can be effectively reduced, and the high-speed operation characteristics can be sufficiently enhanced.
[0039]
Further, since the insulating region 4 is formed by selectively oxidizing the buried region 41 made of InAlAs, the base layer is damaged by the ion implantation, unlike the conventional method of selectively increasing the resistance of the collector region by ion implantation. In response, there is no inconvenience that the resistance Rb parasitic on the base increases. Accordingly, the maximum oscillation frequency fmax is improved, and an ultrahigh-speed and high-output heterojunction bipolar transistor excellent in high-speed operation characteristics can be realized.
[0040]
Further, according to the above-described embodiment, from the epitaxial growth of the buffer layer 2, the subcollector layer 31, the collector contact layer 51, and the collector layer 61, through the etching of the subcollector layer 31, the collector contact layer 51, and the collector layer 61, Since the process up to the growth of the buried region 41 is performed in the same growth apparatus, the surface of the semiconductor layer can be prevented from being oxidized, so that a good film can be formed. In addition, it is possible to manufacture an ultrahigh-speed, high-output heterojunction bipolar transistor that eliminates the trouble of removing the oxide film generated on the surface of the semiconductor layer, improves the throughput, is simple and effective, and has a high yield. it can.
[0041]
Incidentally, in the heterojunction bipolar transistor manufactured according to the present embodiment, since the dielectric constant of the insulating region 4 under the external base region is 8, the parasitic capacitance Cbc between the base and the collector is under the external base region. Compared to the case of InP (relative permittivity is 12.4), which is the same as that of the collector region 6, it is reduced by about 50%.
[0042]
When the emitter size is 2 × 10 μm ² and the base-collector junction area is 3 × 15 μm ² , the maximum oscillation frequency fmax of the heterojunction bipolar transistor manufactured according to the present embodiment is (1 ) To 85 GHz. On the other hand, when the same InP as the collector region 6 is used under the external base region, the maximum oscillation frequency fmax is 60 GHz. Therefore, according to the present embodiment, it was confirmed that an ultrafast heterojunction bipolar transistor can be obtained.
[0043]
In the above-described embodiment, the case where the present invention is applied to a GaAsSb / InP heterojunction bipolar transistor has been described as an example. However, the present invention is applied to a GaAsSb / InP heterojunction bipolar transistor. For example, the present invention can be applied to a system made of a material lattice-matched to a GaAs substrate, for example, a GaAs / InGaP heterojunction bipolar transistor. The thickness, layer structure, etc. of each layer may be determined according to the required operating characteristics, and the present invention can be variously designed and modified without departing from the scope of the invention.
[0045]
【The invention's effect】
As described above, according to the present invention, the buffer layer, the sub-collector layer and the collector layer are stacked on the substrate, the sub-collector layer and the collector layer are etched, and the buried region made of the compound semiconductor containing Al is grown. Since it is performed in the same growth apparatus, the surface of the semiconductor layer can be prevented from being oxidized, so that a good film can be formed and the trouble of removing the oxide film generated on the surface of the semiconductor layer can be reduced. Thus, it is possible to manufacture a heterojunction bipolar transistor which is simple, effective, high yield and high yield.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an example of a structure of a heterojunction bipolar transistor manufactured by a method for manufacturing a heterojunction bipolar transistor according to the present invention.
FIG. 2 is a longitudinal sectional view taken along a cutting line II-II shown in FIG.
FIG. 3 is a diagram showing stages up to the middle of the manufacturing process of the heterojunction bipolar transistor having the configuration shown in FIGS. 1 and 2;
4 is a diagram showing a continuation of the manufacturing stage shown in FIG. 3. FIG.
FIG. 5 is a diagram showing a continuation of the manufacturing stage shown in FIG. 4;
6 is a diagram showing a continuation of the manufacturing stage shown in FIG. 5. FIG.
7 is a diagram showing a continuation of the manufacturing stage shown in FIG. 6. FIG.
FIG. 8 is a diagram showing a continuation of the manufacturing stage shown in FIG. 7;

Claims (2)

A step of laminating a buffer layer made of a compound semiconductor containing Al, a subcollector layer and a collector layer in order on the substrate;
A part of the collector layer and the sub-collector layer is removed by etching to form a collector region, and a part of the buffer layer is exposed; and a compound semiconductor containing Al in the exposed part of the buffer layer Growing a buried region and growing an oxidation protection cap layer on the surface;
Laminating a base layer over the collector region and the cap layer;
Forming a mesa-shaped emitter region and emitter electrode on the base layer above the collector region;
Forming a base electrode on part or all of the base layer excluding the emitter region;
Removing a part of the collector region, the cap layer and the buried region by etching and oxidizing the remaining buried region to form an insulating region having a lower dielectric constant than the collector region;
Forming a collector electrode in a portion removed by etching of the collector region;
A method of manufacturing a heterojunction bipolar transistor, comprising:   The step of laminating the buffer layer, the subcollector layer, and the collector layer in sequence, the collector region is formed by etching, a part of the buffer layer is exposed, and the buried region and the cap layer are grown 2. The method of manufacturing a heterojunction bipolar transistor according to claim 1, wherein the steps are performed in the same growth apparatus.

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