JP3228431B2 - Method of manufacturing collector-up structure heterojunction bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an ultra-high-speed heterojunction bipolar transistor, and more particularly to a method for manufacturing a heterojunction bipolar transistor having a collector-up structure.

[0002]

2. Description of the Related Art A heterojunction bipolar transistor (hereinafter abbreviated as HBT) using a group III-V compound semiconductor is known.
Basically, it is a vertical transistor having a mesa structure, and is roughly classified into an emitter-up structure in which an emitter is provided on the semiconductor surface side and a collector-up structure in which a collector is provided on the semiconductor surface side. Since the HBT has a mesa structure, the base-collector junction capacitance C _BC is smaller in a collector-up with a small collector area than in an emitter-up. Especially in the emitter-up structure, the ratio of the external base element dimensions occupies the base-emitter junction area the more finely rapidly increases, it is overwhelmingly advantageous collector-up structure to reduce the C _BC.

The high frequency characteristics of the HBT can be understood from an equivalent circuit including an intrinsic transistor and an external parasitic effect. The figure of merit of the ultra-high frequency characteristic is a current gain cutoff frequency f _T and a maximum oscillation frequency f _max , wherein f _T is related to a delay time when minority carriers flow from the emitter to the collector, It is expressed by the expression 1).

F _T = 1 / (2π · τ _EC ) = 1 / 2π [r _E (C _BE + C _BC ) + ( _RE + R _C ) C _BC + τ _B + τ _C ] (1) , R _E are internal emitter resistances and depend on the amount of emitter current. C _BE is the junction capacitance between the base and the emitter.
R _E and R _C are resistance components added to the intrinsic transistor as viewed from the terminals, and are equivalent resistances including those distributed inside. τ _B and τ _C are the base and collector transit times, respectively, and are determined mainly by the structure _, film thickness _{, and} impurity concentration of each of the base and emitter layers. After all, the component dependent on the structure is only the second term of equation (1), R _E, R _C is no difference from the symmetry of the structure, C _BC
Overwhelmingly small collector-up structure is reduced delay time, which is advantageous to an increase in f _T.

On the other hand, f _max greatly depends on the base resistances R _B and C _BC as expressed by equation (2).

F _max = (f _T / 8πR _B C _BC ) ^1/2 (2) R _B is determined by the sheet resistance of the internal intrinsic base, the sheet resistance of the external base, and the contact resistance. There is no structural difference in the up. Therefore, a collector-up structure with a small C _BC is extremely advantageous for increasing f _max . In addition to this, the collector-up structure has an advantage that the emitter can be provided on the semiconductor substrate side, so that there is little influence of surface wiring or the like which poses a problem in integration and mounting.

As described above, the collector-up structure is excellent in ultra-high speed and high integration, and can be expected as a power transistor because of its high f _max. However, as described above, the emitter area is larger than the collector area. Therefore, the current amplification factor is lower than that of the emitter-up structure. Further, also occurs a problem that C _BC is increased by carriers stored in the external base lower. In order to solve these problems, it is first necessary to suppress carrier injection from the emitter to the external base region. For example, npn-type AlGaAs /
In a GaAs HBT, a PN junction is formed in a wide band gap emitter layer by ion-implanting an acceptor impurity such as Be, Mg, or C from an external base.
By utilizing the difference in barrier potential between the intrinsic transistor portion and the hetero PN junction, carrier injection into the external emitter-base junction can be suppressed.

However, a PN junction formed by ion implantation in an AlGaAs wide emitter has a higher ideal count n value, which is a figure of merit of a PN junction, than a junction formed by an epitaxial growth method. Many coupling current components. In the collector-up structure, the PN junction under the external base is forward-biased during the operation of the transistor, and in a high current density region, the leakage current due to the recombination current increases, and the transistor characteristics are remarkably deteriorated. Even if the emitter-base junction is under forward bias, it is most effective to provide an electrically insulated high resistance barrier layer in the external emitter-base junction for the transistor to operate normally. It is a measure. In particular, a high-resistance semiconductor layer having a wide band gap has electrons,
A high hetero barrier is generated for all holes, which is effective for suppressing carrier injection. In such a high resistance region, a method of forming an inert gas such as proton, oxygen, or argon by an ion implantation method is the simplest in practice and has excellent reliability. Layers have excellent thermal stability and are being used for element isolation. In this regard, for example, S.
A paper by J. Pearton et al.
stable high-resistivity AlGaAs by Oxygen-Implantat
ion] (Appl. Phys. Lett., 52.pp. 395-397, 198
As disclosed in 8).

As described above, to improve f _max , it is important to reduce not only C _BC but also R _B. However, if oxygen ion implantation is performed through an external base layer, the base resistance R due to defects due to radiation damage is reduced. _B increases significantly and does not exhibit normal transistor operation. For this reason, it is essential to further introduce a p-type impurity after oxygen ion implantation to increase the surface concentration. For this purpose, zinc diffusion is most effective. Indeed, performing the zinc diffusion after the oxygen ion implantation improves the base resistance to a considerable extent, indicating normal transistor operation. However, by introducing zinc diffusion outside the base layer, the rest also influence performing oxygen ion implantation, the reduction of R _B is limited. Further, zinc has a larger diffusion coefficient than other p-type dopants, and excessive zinc diffuses into the intrinsic transistor region, thereby deteriorating transistor characteristics. Therefore, it is desirable that the diffusion of zinc be the minimum necessary. Reliable,
And to thereby achieve a faster transistor operation, it is necessary to further reduce the R _B without using zinc diffusion.

[0008]

The above problems will be further described with reference to the drawings. FIG. 10 shows an n-type conventional conventional collector-up structure in which a high-concentration p-GaAs external base layer formed by diffusion of zinc is formed after forming an AlGaAs external emitter layer having increased resistance by oxygen ion implantation.
FIG. 2 is a cross-sectional structural view of a pn-type AlGaAs / GaAs HBT. On a semi-insulating GaAs substrate 1, Si-doped n-GaAs (Si doping concentration; 5 × 10 ¹⁸ cm)
^-3 ) 0.7 μm buffer layer 2 and Si-doped N-AlG
aAs (Si doping concentration; 2 × 10 ¹⁸ cm ^{−3 to} 3 × 1
0 ¹⁷ , Al-As composition; 0 to 0.3) The emitter layer 3 is 0.4 μm, the C-doped p-GaAs (C doping concentration: 2.5 × 10 ¹⁸ cm ⁻³ ) base layer 4 is 0.08 μm,
Si-doped n-GaAs (Si doping concentration; 5 × 1
0 ¹⁶ cm ^{−3 to} 2 × 10 ¹⁷ ) The collector layer 10 is 0.5 μm,
Si-doped n-GaAs (Si doping concentration; 5 × 1
0 ¹⁸ cm ^-3 ) Oxygen ions are implanted at an accelerating voltage of 100 keV by using a wafer in which the cap layer 11 is 0.1 μm and each of which is epitaxially grown by the molecular beam epitaxial growth (MBE) method, and the N-AlGaAs external emitter layer is raised. Resistance was further increased, and zinc diffusion was performed on the external base layer 16 at 550 ° C. for 3 minutes by an open tube method to increase the surface concentration.
Thereafter, a collector electrode 13 of AuGe / Ni / Ti / Pt / Au and a non-alloy base electrode 1 of Ti / Pt / Au
4, the AuGe / Ni / Ti / Pt / Au emitter electrode 15 is provided, to produce a transistor performs inter-element isolation. The semiconductor processing technology such as mesa etching uses a dry etching method.

FIG. 11 shows the conventional collector-up HBT shown in FIG. 10 at f _T , at an element size of 2 μm × 10 μm and a collector current density of 2.5 × 10 ⁴ A / cm ² .
The _graph shows the dependence of f _{max on} the dose of oxygen ion implantation dose.
Black circles represent f _T and white circles represent f _max . When the oxygen ion implantation dose is increased, the resistance of the N-AlGaAs external emitter layer is increased, and the high concentration p-G diffused by zinc.
Carrier injection into the aAs external base layer 14 is suppressed, and C
_{As BC} is reduced, f _T increases and saturates to a value of approximately f _T = 50 GHz at an implantation dose of 1.5 × 10 ¹⁴ cm ⁻² . On the other hand, if f _max exceeds this dose, R
_It starts to decrease as _B increases.

FIG. 12 shows a transmission line model (T
The sheet resistance R _{S of} the high-concentration p-GaAs external base layer 14 subjected to oxygen ion implantation and zinc diffusion obtained by the LM) method,
The graph also shows the dependence of the contact resistivity ρ _{C on} the oxygen implantation dose. It is evident that both R _S and ρ _C increase with an increase in the implantation dose. Therefore, the decrease in the implantation dose of f _max of 1.5 × 10 ¹⁴ cm ⁻² or more shown in FIG. It is apparent that this is apparently caused by an increase in the external base resistance. When zinc diffusion is performed under the same conditions in GaAs where oxygen ion implantation is not performed, R _S is 260 Ω / sq.
Even when the implantation dose shown in FIG. 11 is the smallest (5 × 10 ¹³ cm ⁻² ), R _S increases three times as much. If the implantation dose is less than this, it is not possible to sufficiently suppress the carrier injection into the external emitter-base junction, which is the original purpose of introducing the oxygen ion implantation, and the transistor characteristics will be deteriorated. As a result, even if oxygen ion implantation and zinc diffusion are used, the high-frequency characteristics f _max have a limit, and at present, the performance of the collector-up HBT has not been sufficiently brought out.

As described above, the resistance of the N-AlGaAs external emitter layer is increased by the conventional oxygen ion implantation.
In the method of forming a high-concentration p-GaAs external base layer by diffusing zinc, there is a limit to the reduction of R _B, high-frequency characteristics, can not be expected, especially the improvement of f _max. Improvement of R _B on pulling out the potential of the collector-up HBT is essential. At the same time, it is also apparent that the conventional method of forming the external base layer in the HBT having the emitter-up structure has the same problem as the collector-up structure.

The present invention has been proposed in order to improve the above-mentioned drawbacks, and it has been proposed to sufficiently reduce the parasitic leakage current and further reduce the base resistance to achieve high-frequency characteristics, especially f
An object of the present invention is to provide a method for manufacturing a heterojunction bipolar transistor having a collector-up structure capable of improving _max .

[0013]

According to the present invention, there is provided an emitter layer comprising a first semiconductor layer having n-type conductivity on a substrate, and an emitter layer formed on the emitter layer. A second insulating layer having a p-type second semiconductor layer having a band gap smaller than that of the first semiconductor layer; and forming a first insulating film on the base layer. Selectively removing the first insulating film by an etching process using the deposited and patterned first photoresist pattern as a mask; and removing the patterned first photoresist and the first insulating film. Removing a part or the entirety of the base layer by an etching process using a mask to form a mesa structure; and masking the patterned first photoresist and first insulating film. Selectively forming a high-resistance region in the emitter layer made of the first semiconductor layer having the n-type conductivity by oxygen ion implantation to remove the first photoresist; An epitaxially regrowth method using the first insulating film as a mask forms an ultra-highly doped third semiconductor layer having a p-type conductivity on the external emitter layer having a high resistance by the oxygen ion implantation. base layer made of the second semiconductor layer and
Selectively contacting the first insulating layer continuously ;
In addition, a step of depositing the first insulating film so as to have the same height as the first insulating film, and a second insulating film on the external base layer made of the regrown third semiconductor layer and the first insulating film deposited, by the etching process to the first photoresist pattern mask formed opening pattern so that the inside of, selectively removing then preparative said second insulating film
In particular, a portion is left on the inner wall of the third semiconductor layer.
Etching the first insulating film to expose an internal intrinsic base layer made of the second semiconductor layer; and epitaxially regrowing using the second insulating film and the first insulating film as a mask. Thus, a collector layer made of a fourth semiconductor layer having an n-type conductivity or an undoped fourth semiconductor layer is selectively formed on the exposed base layer made of the second semiconductor layer, and furthermore, the second semiconductor layer is formed. Depositing the same height as the insulating film; and forming a collector electrode on the collector layer including the fourth semiconductor layer and the second insulating film, using the collector electrode as a mask. by etching, the second insulating film is selectively removed, the third consisting of a semiconductor layer to expose the external base layer, forming a self-aligned manner the base electrode on the exposed external base layer It is a manufacturing method of the collector-up structure heterojunction bipolar transistor, which comprises a.

In order to solve the problem associated with the base resistance, it is necessary to completely eliminate the effect of oxygen ion implantation for increasing the resistance of the N-AlGaAs external emitter layer on the external base layer. For this purpose, instead of performing oxygen ion implantation for increasing the resistance through the external base layer, the external base layer is removed in advance by etching, and after the oxygen ion implantation, a new ultra-high concentration A GaAs layer doped with a p-type impurity is embedded. This method allows the formation of an external base layer that is completely unaffected by oxygen ion implantation. Also,
When the external base layer is selectively regrown using the conventional epitaxial crystal grown in the order of emitter, base, and collector, the collector layer and the external base layer must be removed by etching beforehand. As the thickness of the collector layer increases, it becomes difficult to control the etching. In addition, there is a problem that the inner base and the outer base do not continuously contact with each other due to the protective film provided on the side of the collector mesa so that the etched side surface of the collector mesa does not contact the regrown external base. On the other hand, when a similar regrowth method is performed using the epitaxial crystal grown up to the base layer, only the external base layer needs to be removed in advance by etching, so that the control of etching is easy, and the selective regrowth after that is performed. There is no problem in contact between the outer base layer and the inner base layer.

[0015]

The ultra-high-concentration external base formed in the present invention is not affected by oxygen ion implantation for increasing the resistance of the underlying AlGaAs external emitter layer at all.
In addition, since the connection can also be made smoothly and continuously with the inner base layer, the contact resistance between the intrinsic base layer and the outer base can be reduced. In addition, since the collector layer is also epitaxially grown by the regrowth method, the base electrode can be formed very close to the collector mesa by the self-alignment technique using the collector electrode as a mask. The resistance of the lead-out region is drastically reduced as compared with the case where it is formed. Therefore, the overall base resistance is dramatically reduced as compared with the conventional method. Further, with respect to increasing the resistance of the AlGaAs external emitter layer, the dose of oxygen ion implantation can be further increased, and a highly reliable high resistance layer can be formed. As a result, it is possible to provide a hetero-junction bipolar transistor having a collector-up structure excellent in high-frequency characteristics and reliability.

[0016]

An embodiment will be described below with reference to the drawings. It should be noted that the embodiments are merely examples, and it is needless to say that various changes or improvements can be made without departing from the gist of the present invention. 1 to 9 illustrate a manufacturing process of an npn collector-up structure HBT according to the present invention, and all show sectional structural views. In this embodiment, as a crystal material of a transistor, Al is epitaxially grown on a semi-insulating GaAs substrate.
A description will be given by taking a GaAs / GaAs semiconductor crystal as an example.

FIG. 1 shows that a semi-insulating GaAs substrate 1
Doped n-GaAs (Si doping concentration; 5 × 10 ¹⁸⁾
cm ^-3 ) 0.7 μm buffer layer 2 and Si-doped N-Al
GaAs (Si doping concentration; 3 × 10 ¹⁷ cm ⁻³ , Al
-As composition; 0 to 0.3) 0.3 μm
C-doped p-GaAs (C doping concentration: 5 × 10 ¹⁹
cm ^-3 ) 0.05 μm organic metal pyrolysis (MO)
After a first silicon nitride film (Si ₃ N ₄ ) 5 is deposited by a plasma CVD method to a thickness of 0.15 μm on the entire surface of a wafer which has been sequentially epitaxially grown by a CVD method, patterning is performed by a first photolithography. The Si ₃ N ₄ film 5 is etched by C ₂ F ₆ gas reactive ion etching (RIE) and SF ₆ gas RIE using the photoresist (thickness: about 1.1 μm) 6 as a mask to form the p-GaAs base layer 4. This is a view showing a step of exposing. In this embodiment, the silicon nitride film 5 is deposited by the plasma CVD method. However, the silicon nitride film 5 can be deposited by an optical CVD method that causes less damage to the semiconductor layer to be deposited. In this embodiment, the epitaxial growth is performed by using the MOCVD method in order to increase the doping concentration of the base layer. However, the MOMBE method can be used. The MOMBE method uses a gas source as a raw material,
The gas source MBE method and vacuum MOCVD method are performed at a degree of vacuum (about 10 ⁻⁵ Torr) in the intermediate region between the MOCVD method and MOCVD method.
The method is also called a chemical beam epitaxy (CBE) method.

FIG. 2 shows the photoresist 6 and the S
Using the i ₃ N ₄ film as a mask, the exposed p-GaAs
After the base layer 4 is removed by a dry etching method with a small side etching amount, oxygen ions are implanted with the same mask to increase the resistance of the N-AlGaAs emitter layer 3 and selectively form the external emitter layer 7 serving as a barrier. 4 shows a process. In this embodiment, RIE using electron cyclotron resonance (ECR) is used as a dry etching method. In the reaction gas chlorine Cl _2, the ECR-
The use of the RIE apparatus has an advantage that the etched semiconductor surface is less damaged. The acceleration voltage for oxygen ion implantation varies with the thickness of the emitter layer (to increase the resistance over the entire area of the external emitter layer), but is set to 100 keV in this embodiment. R _P projected range at this time, 0.1
It is about 5 μm. The implantation dose is 2 × 10 ¹⁴ cm ^-2 ,
Under these implantation conditions, the resistance of the external emitter layer is increased over the entire area as shown by 7 in the figure. The same effect can be expected if the implantation dose is larger than this value.

FIG. 3 shows that after removing the photoresist 6 and cleaning the surface of the external emitter layer 7 into which oxygen ions have been implanted,
By the MOMBE method, trimethylgallium (TMG),
Using As ₄ as a growth material, C at a growth temperature of 450 to 550 ° C.
This shows a step of regrowing the doped ultra-high concentration p-GaAs external base layer 8 on the external emitter layer 7 by 0.2 μm. In this case, the outer base layer 8 is insulated from the base layer 4.
It is formed so as to be in continuous contact with the edge layer 5. The control of the carrier concentration is performed by controlling the As ₄ pressure while keeping the TMG supply amount constant. In this embodiment, using the MOMBE method as a method for regrowth, it is also possible to use a MOCVD method, the the Si ₃ N ₄ film 5 With either
No semiconductor layer is deposited on top of this and has excellent selectivity.
In particular, in the MOMBE method, the hole concentration exceeds 1 × 10 ²¹ cm ⁻³ by using C as the p-type dopant. In this regard, for example, a paper by T. Yamada et al. [Heavil
y Carbon Doped p-Type GaAsAnd GaAlAs Grown Metalor
ganic Molecular Beam Epitaxy] (J. Cryst. Growth.
95, pp. 145-149, 1989). Thus, even if the dopant is introduced into GaAs at an extremely high concentration, there is no problem of diffusion into the emitter layer and the collector layer because C having an extremely small diffusion coefficient is used. In addition, the thickness of the regrown p-GaAs external base layer 8 in the figure is set to be substantially the same as the combined thickness of the Si ₃ N ₄ film 5 and the intrinsic base layer 4. .

FIG. 4 shows the p-GaAs external base layer 8.
And a step of depositing a 0.4 μm second Si ₃ N ₄ film 9 on the Si ₃ N ₄ film 5 by a plasma CVD method.

[0021] Figure 5 is off on the second Si ₃ N ₄ film 9
Forming an opening pattern inside the pattern of photoresist 6
The second performs a photolithography as a mask patterned photoresist, a part of the second Si ₃ N ₄ film 9 and the first Si ₃ N ₄ film 5 C ₂ F ₆ gas RI to
Etching by E and SF ₆ gas RIE, p-Ga
This shows a step of exposing the As intrinsic base layer 4. The lateral width of the first Si ₃ N ₄ film 5 left on the side wall of the external base layer 8 by this etching is set to 0.1 mm by the second photolithography and SF ₆ gas RIE (isotropically etched). Adjust so as to be about 2 μm.

[0022] Figure 6, after cleaning the surface on the p-GaAs intrinsic base layer 4 mentioned above exposed, trimethyl gallium (TMG) by MOMBE method, Si-doped n-GaAs collector layer as the growth material AS ₄ (doping concentration 3
× 10 ¹⁶ cm ⁻³ ) 10 is 0.4 μm, Si-doped high concentration n
The -GaAs layer (doping concentration 5 × 10 ¹⁸ cm ⁻³ ) 11 is 0.05 μm, and the Si-doped high concentration n-InGaAs cap layer (doping concentration 2 × 10 ¹⁹ cm ⁻³ , In-As composition 0.6) 12 is 12 μm. This shows the step of regrowth in the order of 0.1 μm. The growth temperature when the InGaAs cap layer 12 was regrown was 450 ° C., the raw materials were TMG, trimethyl iridium (TMI) and As ₄ , and disilane (Si ₂ H ₆ ) was used as a dopan gas. The method of regrowth is, of course, also possible by MOCVD. In general, the regrown pn junction characteristic has a higher recombination current ratio,
The base-collector pn junction provided in GaAs is relatively good, and in normal transistor operation, the base-collector pn junction is reverse-biased and therefore forward-biased. The increase in recombination current is not so important as compared to the base-emitter pn junction characteristics. In order to increase the collector breakdown voltage when applying to a power transistor, it is indispensable to increase the thickness of the collector layer 10. In this case, the second Si ₃ N ₄ film 9 is used. By adjusting the thickness, the height of the second Si ₃ N ₄ film 9 and the height of the regrown n-InGaAs cap layer 12 can be made approximately the same.

FIG. 7 shows that a third photolithography is performed on the regrown n-InGaAs cap layer 12 and the second Si ₃ N ₄ film 9 to form a collector electrode Ti / Pt / Au 13 by a normal lift-off method. 3 shows a forming process. In this embodiment, the collector electrode 13
Third photolithography is performed so as to extend outward by about 0.3 μm from the regrown n-InGaAs cap layer 12. The film thickness of the collector electrode used in this embodiment is Ti 20 nm, Pt 20 nm, and Au 150 nm.

FIG. 8 shows that the collector film 13 is used as a mask to form the second Si ₃ N ₄ film 9 on a C ₂ F ₆ gas RIE.
And SF ₆ gas RIE to etch ultra-high concentration p
FIG. 6 shows a step of forming a base electrode Pt / Ti / Pt / Au14 in a self-aligned manner by an electron beam evaporation method after exposing the GaAs external base layer 8; As shown in the figure, isotropically etched SF ₆ -RI
By increasing the E etching time, the second Si ₃ N
_By etching the _four films 9 in the lateral direction to realize a T-shaped collector electrode / collector mesa structure, a base electrode can be easily formed in a self-aligned manner so that the collector electrode and the base electrode do not come into contact with each other. The base electrode film used in this embodiment, Pt 10 nm, Ti 20 nm, Pt 50 nm, Au15
0 nm. Also, a Ti / Pt / Au non-alloy base electrode can be used.

FIG. 9 shows that the fifth photolithography is performed to cover the semiconductor layer between the base electrode 14 and the collector electrode 13 with a photoresist, and then the external base layer 8 and the oxygen ions are dry-etched. The implanted high-resistance AlGaAs external emitter layer is removed, and n-G
The aAs buffer layer 2 is exposed, and the emitter electrode AuG is formed by the sixth photolithography and the normal lift-off method.
5 shows a step of forming e / Ni / Ti / Pt / Au 15 . The thickness of the emitter electrode used in this embodiment is AuGe 85 nm, Ni 15 nm, Ti 100 nm, Pt
20 nm and Au 150 nm. 360 Ohmic treatment
C. in an N ₂ gas atmosphere. Thereafter, an SiO ₂ interlayer insulating film is deposited by a plasma CVD method. After separation between the elements, holes (through holes) are formed in the respective electrode portions by RIE, and wiring is finally provided to complete the element manufacturing process.

In the present invention, the resistance of the external AlGaAs emitter layer is increased by oxygen ion implantation, but the high resistance layer formed by ion implantation of another dopant species is
The effect is easily extinguished by the relatively high temperature regrowth process (500-550 ° C.). The reason is that the high-resistance layer formed by ion implantation of a dopant other than oxygen ions is caused by damage due to radiation damage, and the damage is recovered as the annealing temperature increases. On the other hand, the layer in which oxygen ions are implanted in the AlGaAs layer also recovers high resistance due to radiation damage as the process temperature rises, but newly shows high resistance due to a deep level. The high resistance layer caused by this deep level
It is peculiar to oxygen ions doped in the AlGaAs layer and has excellent thermal stability. It is effective not only in device performance but also in device reliability. In this regard, for example, a paper by SJ Pearton et al., [Fo
rmation of thethermally stable high-resistivity Al
GaAs by Oxygen Implantation] (Appl. Phys. Lett.,
52, pp. 395-397, 1988).

High resistance AlGaAs as an external emitter layer
The layer (the region corresponding to 7 in FIGS. 1 to 9) can also be formed by the selective regrowth method. In the process shown in FIG. 2, the photoresist 6 and the first Si ₃ N ₄ film 5 are used as masks to form an IC.
The p-GaAs base layer 4 and the N-AlGaAs emitter layer 3 in the external region are selectively removed by dry etching using the R-RIE method,
By regrowing the undoped AlGaAs external emitter layer and the high-concentration external base layer in this order by the VD method, a structure similar to that shown in FIG. 3 can be formed. However, trimethyl aluminum (TMA), TM
Undoped AlGa using G, AS ₄ or Algin
When an As external emitter layer is grown, a large amount of C of methyl group enters the crystal and shows the behavior of a p-type dopant.
It is difficult to increase resistance. In addition, even if triethylaluminum (TEA), in which C is relatively hard to enter, is made of a high-resistance AlGaAs that can be achieved by an oxygen ion implantation method.
It is difficult to realize an external emitter layer (sheet resistance of about 10 ⁸ Ω / sq). In addition, the undoped AlGa
It is difficult to control the thickness of the As external emitter layer and the high-concentration p-GaAs external base layer, and the oxygen ion implantation that can easily and uniformly form a high-resistance layer is more advantageous in terms of improvement in throughput and reliability. is there.

[0028]

As described above in detail, according to the present invention, in forming the external base region of the collector-up structure AlGaAs / GaAs heterojunction bipolar transistor, the hole concentration is 1 × 10 ²¹ cm ⁻³ or more. Concentration p-G
By depositing the aAs external base layer on the AlGaAs external emitter layer whose resistance has been increased by oxygen ion implantation by the regrowth method, it is possible to form an ultra-high-concentration external base layer unaffected by oxygen ion implantation. Became. In particular,
The biggest problem when forming the external base layer by the regrowth method is to regrow so as to be continuously connected to the intrinsic base layer and not to be in contact with the collector layer. Since the external base layer is regrown using the epitaxial crystal which has been grown up to the p-GaAs base layer in advance, the above problem is solved. In addition, by adjusting the film thickness of Si ₃ N ₄ used as a mask material at the time of regrowth, even if the film thickness of the external base layer and the collector layer by regrowth are arbitrarily changed, the process steps shown in the present invention can be performed Can be easily executed. As a result,
The base electrode can be formed in close proximity to the intrinsic base layer in a self-aligned manner, and together with the formation of the ultra-high concentration external base, the base resistance can be significantly reduced,
Improvement of the current amplification factor at high collector current density region has the effect that the high-frequency characteristics, in particular the improvement of f _max, it is possible to provide a bipolar transistor the collector-up structure AlGaAs / GaAs heterojunction excellent reliability.

For example, in the collector-up structure AlGaAs / GaAs HBT manufactured according to the present invention, 2 × 10
With an element size of μm, the base resistance is reduced to about 5Ω corresponding to 1/20 of the conventional example, and as a result, f _max = 200 GH
Is achieved, and a remarkable improvement in high frequency characteristics is realized.
In this embodiment, an AlGaAs / GaAs heterostructure material has been described. However, the present invention does not limit the choice of crystal material, and may be, for example, InP / InGaAs, InAlAs / InGaAs.
It is also applicable to III-V group compound semiconductors such as s and II-VI group compound semiconductors.

Further, according to the method of manufacturing an HBT according to the present invention, since the characteristics of the HBT device having the collector-up structure are remarkably improved, it is possible to expect the integrated formation at the same time as the device having the emitter-up structure. That is, since the manufacturing method of the present invention can be applied to both the collector-up structure and the emitter-up structure, a logic circuit configuration combining these two elements can be effectively realized. For example, by integrating transistors of both structures,
The performance of a logic circuit equivalent to I ² L / MTL, STL, ECL / CML can be greatly improved. Further, by configuring the conductivity type to be opposite, a logic circuit or the like having a complementary configuration can also be configured. Further, light receiving elements such as PIN photodiodes and APDs, and LEs
By integrating with a light emitting element such as a laser diode or a laser diode, the present invention can be applied to a method of manufacturing an optoelectronic integrated circuit (OEIC). Furthermore, the HB according to the invention
By superposing these HBTs in parallel according to the manufacturing method of T, it is possible to realize a power bipolar transistor having an ultra-high frequency and high output.

[Brief description of the drawings]

FIG. 1 is an element cross-sectional structure diagram showing a manufacturing process of an npn-type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 2 is an element cross-sectional view showing a manufacturing process of an npn-type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 3 is a cross-sectional structural view of an element showing a manufacturing process of an npn-type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 4 is an element cross-sectional view showing a manufacturing process of an npn-type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 5 is a cross-sectional structural view of a device showing a manufacturing process of an npn-type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 6 is a sectional view showing an element in a manufacturing process of an npn-type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 7 is an element cross-sectional structure diagram showing a manufacturing process of an npn-type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 8 is an element cross-sectional view showing a manufacturing process of an npn-type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 9 is an element cross-sectional view showing a manufacturing process of an npn-type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 10 is a cross-sectional structural view of a conventional typical npn type collector-up structure AlGaAs / GaAs HBT.

FIG. 11 is a characteristic showing the dependency of the current gain cutoff frequency f _T (GHz) and the maximum oscillation frequency f _max (GHz) on the oxygen ion implantation dose in a conventional typical collector-up structure HBT having an element size of 2 μm × 10 μm. FIG.

FIG. 12 shows the dependence of the sheet resistance R _S and the contact resistivity ρ _C of the C-doped p-type GaAs layer corresponding to the external base, which was subjected to zinc diffusion after oxygen ion implantation, on the oxygen ion implantation dose, as determined by the TLM method. FIG.

[Explanation of symbols]

Reference Signs List 1 semi-insulating GaAs substrate 2 Si-doped n-type GaAs buffer layer 3 Si-doped N-type AlGaAs emitter layer 4 C-doped p-type GaAs base layer 5 first plasma CVD silicon nitride film (Si
₃ N ₄ ) 6 Photoresist 7 AlGaAs external emitter region whose resistance is increased by oxygen ion implantation 8 Ultra-high concentration p-GaAs external base layer selectively regrown 9 Second plasma CVD silicon nitride film (Si
₃ N ₄ ) 10 Selectively regrown Si-doped n-type GaAs collector layer 11 Selectively regrown high-concentration Si-doped GaAs cap layer 12 Selectively regrown high-concentration Si-doped InGaAs cap layer 13 Ti / Pt / Au collector electrode 14 Pt / Ti / Pt / Au base electrode 15 AuGe / Ni / Ti / Pt / Au emitter electrode 16 High concentration p-GaAs external base layer with zinc diffusion

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-251660 (JP, A) JP-A-63-263761 (JP, A) JP-A-63-16665 (JP, A) JP-A-62 47158 (JP, A) JP-A-62-18762 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/737 H01L 21/331 H01L 29/205

Claims (1)

(57) [Claims] 1. An emitter layer comprising a first semiconductor layer having n-type conductivity on a substrate, and a p-type emitter having a band gap smaller than that of the first semiconductor layer formed on the emitter layer. In forming a semiconductor laminated structure including a base layer made of a second semiconductor layer having a conductivity type, a first insulating film is deposited on the base layer, and a patterned first photoresist pattern is used as a mask. Selectively removing the first insulating film by performing an etching process, and partially or entirely removing the base layer by performing an etching process using the patterned first photoresist and the first insulating film as a mask. Removing to form a mesa structure; and implanting oxygen ions using the patterned first photoresist and first insulating film as a mask. Selectively forming a high-resistance region in an emitter layer made of a first semiconductor layer having: a) removing the first photoresist and then using an epitaxial regrowth method using the first insulating film as a mask By
A third semiconductor layer having a p-type conductivity type doped with an ultra-high concentration is provided on an external emitter layer having a high resistance by the oxygen ion implantation, a base layer made of the second semiconductor layer, and the first insulating layer. Depositing selectively so as to make continuous contact with the layer and at the same height as the first insulating film; and an external base layer comprising the regrown third semiconductor layer; wherein the first insulating film by depositing a second insulating film, the etching process of the first photoresist pattern mask formed opening pattern so that the inside of the second insulating film Is selectively removed , and the third
The first insulating layer so that a part thereof remains on the inner wall of the semiconductor layer.
Etching the edge film to expose the internal intrinsic base layer made of the second semiconductor layer; and epitaxially growing again using the second insulating film and the first insulating film as a mask, thereby forming an n-type A collector layer made of a fourth semiconductor layer having a conductivity type or an undoped fourth semiconductor layer is selectively formed on the exposed base layer made of the second semiconductor layer, and at the same level as the second insulating film. A collector electrode is formed on the collector layer made of the fourth semiconductor layer and the second insulating film, and the etching process is performed using the collector electrode as a mask. a second insulating film is selectively removed, exposing the external base layer made of the third semiconductor layer, and a step of forming a self-aligned manner the base electrode on the exposed external base layer Method of manufacturing a collector-up structure heterojunction bipolar transistor according to claim.