JP5290909B2 - Heterojunction Bipolar Transistor Manufacturing Method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heterojunction bipolar transistor which has a high current amplification factor, and is excellent in high-frequency characteristics, and in element service life, and to provide a method of manufacturing the heterojunction bipolar transistor. <P>SOLUTION: The heterojunction bipolar transistor is constituted by laminating an intrinsic emitter layer 16 made of an n-type semiconductor, a base layer 9 doped with a p-type dopant to a high concentration and having a narrower band gap than the intrinsic emitter layer 16, and a collector layer 10 made of the same semiconductor with the base layer 9 in this order on a semi-insulating substrate 1, wherein a high-resistance region 15 is provided around the intrinsic emitter layer 16, a guard ring region 17 made of the same semiconductor with the intrinsic emitter layer 16 is provided between the high-resistance region 15 and intrinsic emitter layer 16, and a junction surface between the intrinsic emitter layer 16 and base layer 9 is disposed below an upper surface of the guard ring region 17. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

The present invention relates to a method for manufacturing a heterojunction bipolar transistor .

  Heterojunction bipolar transistor (HBT) uses a semiconductor material with a wider band gap than the base for the emitter, and maintains a high current gain even when the impurity concentration of the base is higher than that of the emitter, compared to the homojunction bipolar transistor. In addition, since the base layer can be thinned and the base resistance can be reduced at the same time, ultra-high speed operation is possible.

Furthermore, when a III-V compound semiconductor is used, advantages such as widening the degree of freedom of combination of heterojunctions depending on the selection of materials and integration with optical devices as well as electronic devices are increased. In the III-V compound semiconductor HBT, in particular, in the npn type InP / InGaAs HBT using InP as the emitter material and InGaAs as the base material, the current gain cutoff frequency f, which is an index of high-speed performance, due to the excellent electron transport characteristics of InGaAs. _T exceeds 700GHz, and the best performance among transistors is obtained. In addition, InP / InGaAs HBTs have a low emitter / base junction turn-on voltage, which is advantageous in reducing the power consumption of integrated circuits.

  Further, in the process, particularly in the etching process, a complete selective wet etching solution can be used for InGaAs and InP, respectively, so that the etching uniformity within the wafer surface is excellent. The InP / InGaAs HBT is advantageous as a device constituting a large-scale integrated circuit, in combination with the excellent in-wafer uniformity of the turn-on voltage between the emitter and the base corresponding to the threshold value.

These HBTs are vertical transistors having a mesa type because they are usually stacked by epitaxial growth, and are roughly divided into an emitter-up structure in which the emitter is the top of the stacked structure and a collector-up structure in which the collector is the top. Is done. While the emitter-up structure for ease in manufacturing is the mainstream, characteristic of the collector-up structure is that the collector area, in particular the base-collector junction capacitance C _BC can be reduced as compared with the emitter-up structure. The ratio of the external base region element dimensions occupies the base-emitter junction area the more finely the emitter-up structure increases, to decrease the C _BC is advantageously collector-up structure (Non-Patent Document 1 p. 124-133).

  The problem with the collector-up structure is that the emitter-base junction area becomes larger than the collector-base junction area, so that it is necessary to suppress carrier injection from the emitter to the external base region. For example, in an npn type HBT, an acceptor impurity is ion-implanted from an external base and activation annealing is performed to form a pn junction in a wide bandgap semiconductor emitter, and due to the difference in barrier potential from the heterojunction of the intrinsic transistor portion. Carrier injection into the external emitter-base junction can be suppressed.

  However, a pn junction formed by ion implantation in a wide band semiconductor has a higher n value and a larger recombination current component than a pn junction formed by epitaxial growth. In particular, in the high current density region, the leakage current increases and the current gain is significantly reduced. In order to maintain current gain even when the emitter-base junction is in a forward bias state, it is effective to provide an electrically isolated high-resistance barrier layer in the external emitter-base junction .

The high-resistance layer of the wide band gap semiconductor has a high hetero barrier against both electron and hole carriers, and is effective in suppressing carrier injection. In the case of InP / InGaAs HBT, a stable high-resistance layer can be formed in the InP layer by Fe ion implantation, as described in Patent Document 1 “Method for producing heterojunction bipolar transistor” below. However, the Fe ion implantation p ⁺ -InGaAs performed from the base layer p ⁺ -InGaAs base layer also high resistance because the base resistance increases significantly, with Fe ion implantation multilayer structure is epitaxially grown to InP emitter layer The resistance of the external emitter region is increased, and then a p ⁺ -InGaAs base layer, an undoped InGaAs collector layer, and an n ⁺ -InGaAs collector contact layer are sequentially grown by epitaxial regrowth to form a collector-up type HBT structure.

  FIG. 13 shows a cross-sectional view of a conventional collector-up type HBT. As shown in the figure, a sub-emitter layer 3 made of a semiconductor doped with a dopant of the first conductivity type (in this case, n-type) is formed on a semi-rimmed substrate 1, and on the sub-emitter layer 3, An emitter contact layer 4 made of a semiconductor having a band gap narrower than that of the sub-emitter layer 3 is formed by doping with one conductivity type dopant at a high concentration, and the first conductivity type dopant is doped on the emitter contact layer 4; An intrinsic emitter layer 16 made of a semiconductor having a wider band gap than the emitter contact layer 4 is formed, and a second conductivity that is opposite to the first conductivity type (p-type conductivity) is formed on the intrinsic emitter layer 16. A base layer 9 made of a semiconductor doped with a conductive dopant at a high concentration and having a narrower band gap than the emitter layer 5 is formed. In a collector-up type HBT in which a collector layer 10 made of the same semiconductor as the base layer 9 is formed on the layer 9, a high resistance region 15 (high resistance barrier layer) is provided around the intrinsic emitter layer 16. Yes.

  Further, for such an HBT, a process is generally performed in which elements are separated by etching, and the semiconductor surface is passivated with a spin coating organic insulating film such as polyimide or BCB.

Japanese Patent Application Laid-Open No. 07-122573 Japanese Patent Laid-Open No. 08-288297

Jiann S. Yuan, “SiGe, GaAs, and InP Heterojunction Bipolar Transistors” (John Wiley & Sons, Inc. 1999)

  In the emitter-up type HBT, a surface recombination base current is generated between the peripheral portion of the emitter mesa and the external base region as the emitter mesa plane size is reduced, and the current amplification factor is remarkably lowered. This becomes prominent as the ratio of the peripheral length to the emitter intrinsic region increases. In order to suppress this surface recombination leakage current, it is effective to provide a recombination base current suppression region called a guard ring structure (synonymous with a ridge structure) around the emitter mesa on the surface of the external base layer. In InP / InGaAs HBT, for example, as shown in Patent Document 2, the InP emitter layer is thinned by dry etching so that the protruding region on the base layer functions as a guard ring region. This thin InP layer on the base layer is sufficiently depleted and is effective in suppressing surface recombination leakage current.

  On the other hand, in the collector-up type HBT, sufficient measures are not taken to suppress the surface recombination leakage current around the emitter-base junction and the side surface of the emitter layer as described above. There is concern about a significant decrease in amplification factor. In addition, the long-term reliability of the element is insufficient. In particular, when a high resistance region is formed by ion implantation in an external emitter that is a wide band gap semiconductor, damage during ion implantation promotes surface recombination leakage current around the emitter-base junction and the side of the emitter layer, Further reduction of the current gain can be caused.

The present invention has been made in view of the above problems, and the problem to be solved by the present invention is to produce a heterojunction bipolar transistor having a high current amplification factor and excellent high-frequency characteristics and device lifetime. It is to provide.

In the present invention, in order to solve the above problem, as described in claim 1 ,
A method of manufacturing a heterojunction bipolar transistor for manufacturing a collector-up type heterojunction bipolar transistor having a guard ring region around an intrinsic emitter layer, comprising: a semiconductor doped with a first conductivity type dopant at a high concentration on a substrate; Forming an emitter contact layer comprising: forming an emitter lower layer made of a semiconductor doped with a high concentration of a first conductivity type dopant and having a wider band gap than the emitter contact layer on the emitter contact layer; Forming an intrinsic emitter layer doped with a first conductivity type dopant on the emitter underlayer and made of the same semiconductor as the underlying contact layer; and forming a band gap narrower than the intrinsic emitter layer on the intrinsic emitter layer. Process for forming a cap layer made of semiconductor If, depositing an insulating film on the cap layer performs photoresist pattern training on the insulating film, forming an insulating film pattern by reactive ion etching using a mask a photoresist pattern, the insulating film Etching the cap layer, the intrinsic emitter layer and the lower emitter layer using the pattern as a mask to expose the emitter contact layer; and at least a band gap equal to or wider than the emitter layer on the exposed emitter contact layer the external emitter layer composed of a semiconductor having a photoresist pattern to the lower height of at least the insulating film pattern and the step of epitaxially regrown to cover the insulating film pattern surface of the photoresist pattern as a mask, the external Performing ion implantation on the entire surface of the emitter layer; Serial removing the photoresist pattern and the insulating film pattern, a step of further removing by selective etching said cap layer, said regrown external emitter layer, and the intrinsic emitter layer exposed by the removal of the cap layer, Forming a base layer doped with a high concentration of a second conductivity type dopant having conductivity opposite to that of the first conductivity type, and forming a collector layer made of the same semiconductor as the base layer on the base layer; And a process for manufacturing a heterojunction bipolar transistor.

In the present invention, as described in claim 2 ,
6. The method of manufacturing a heterojunction bipolar transistor according to claim 5, further comprising a step of forming a collector contact layer made of a semiconductor doped with a high concentration of a first conductivity type dopant on the collector layer. .

In the present invention, as described in claim 3 ,
A heterojunction bipolar transistor manufacturing method for manufacturing a collector-up type heterojunction bipolar transistor having a guard ring region in the periphery of an intrinsic emitter layer, wherein the first conductivity type dopant is doped on a semi-insulating substrate. Forming an emitter layer; forming an emitter contact layer made of a semiconductor doped with a first conductive dopant at a high concentration on the sub-emitter layer and having a narrower band gap than the sub-emitter layer; A first conductivity type dopant is doped on the emitter contact layer at a high concentration to form an emitter lower layer made of a semiconductor having a wider band gap than the emitter contact layer, and the first conductivity type dopant is formed on the emitter lower layer. Doped with the lower contact layer. Forming an intrinsic emitter layer made of a semiconductor; forming a cap layer made of a semiconductor having a narrower band gap than the intrinsic emitter layer on the intrinsic emitter layer; and depositing an insulating film on the cap layer and performs photoresist pattern training on the insulating film, forming an insulating film pattern by reactive ion etching using a mask a photoresist pattern, the insulating film pattern as a mask, the cap layer, the intrinsic emitter Etching the layer and the emitter lower layer to expose the emitter contact layer, and at least an external emitter layer made of a semiconductor having at least the same or a wide band gap as the emitter layer on the exposed emitter contact layer epitaxial SaiNaru to the lower height of the insulating film pattern A step of the insulating film pattern to form a photoresist pattern to cover the surface, as a mask the photoresist pattern, and performing ion implantation into the outer emitter layer over the entire surface, and removing the photoresist pattern and the insulating film pattern Further, the step of removing the cap layer by selective etching, and a first conductivity type opposite to the first conductivity type on the external emitter layer and on the intrinsic emitter layer exposed by removing the cap layer. Forming a base layer doped with a high concentration of two-conductivity-type dopant; forming a collector layer made of the same semiconductor as the base layer on the base layer; and forming a first conductivity-type dopant on the collector layer Forming a collector contact layer doped at a high concentration with at least a previous step on the collector contact layer A photoresist pattern is formed on a surface including the intrinsic emitter layer and not including the ion-implanted region, and the collector cap layer and the collector layer are etched using the photoresist pattern as a mask. A step of exposing a layer, a step of forming a collector electrode and a base electrode on the collector contact layer and the base layer, respectively, and a photoresist pattern formed at least outside the base electrode, and then the photoresist pattern And etching the base emitter layer and the external emitter layer including the ion implantation region to expose the emitter contact layer and forming an emitter electrode in the exposed portion. The manufacturing method of the bipolar transistor is configured.

  In the present invention, a guard ring region that is not provided in the conventional collector-up HBT structure is provided around the intrinsic emitter layer, and the junction surface between the intrinsic emitter layer and the base layer is lower than the upper surface of the guard ring region. Thus, it is possible to effectively suppress the emitter-base junction surface recombination leakage current, and to mitigate the decrease in the current amplification factor (size effect) accompanying the miniaturization of the element.

1 is a cross-sectional structure diagram of a collector-up InP / InGaAs HBT having a guard ring region manufactured by a method of manufacturing a heterojunction bipolar transistor according to the present invention. FIG. 2 is a process flow diagram showing a method for manufacturing the collector-up type InP / InGaAs HBT shown in FIG. 1 . FIG. 3 is a process flow diagram following FIG. 2. FIG. 4 is a process flow diagram following FIG. 3. FIG. 5 is a process flowchart subsequent to FIG. 4. FIG. 6 is a process flowchart subsequent to FIG. 5. FIG. 7 is a process flowchart following FIG. 6. FIG. 8 is a process flowchart subsequent to FIG. 7. FIG. 9 is a process flowchart subsequent to FIG. 8. FIG. 10 is a process flow diagram following FIG. 9. FIG. 11 is a process flow diagram following FIG. 10. FIG. 12 is a process flow diagram following FIG. 11. It is a cross-sectional structure diagram of a conventional collector-up InP / InGaAs HBT.

[Example of embodiment]
An example of a heterojunction bipolar transistor manufactured by the method of manufacturing a heterojunction bipolar transistor according to the present invention is shown in FIG. As shown in the figure, a semiconductor doped with a first conductivity type (in this case, n-type) dopant (InP doped with a high concentration of n-type impurities) on a semi-insulating substrate 1 made of semi-insulating InP. A sub-emitter layer 3 is formed, and a semiconductor having a narrower band gap than the sub-emitter layer 3 (high-concentration n-type doped InGaAs) is doped on the sub-emitter layer 3 with a high concentration of the first conductivity type dopant. An emitter contact layer 4 is formed, and an intrinsic emitter layer made of a semiconductor (n-type doped InP) doped with a first conductivity type dopant and having a wider band gap than the emitter contact layer 4 is formed on the emitter contact layer 4. 16 is formed and exhibits conductivity (p-type conductivity) opposite to the first conductivity type on the intrinsic emitter layer 16. A base layer 9 made of a semiconductor (high-concentration p-type InGaAs) doped with a two-conductivity-type dopant at a high concentration and having a narrower band gap than the emitter layer 5 is formed, and is the same as the base layer 9 on the base layer 9 A collector layer 10 made of a semiconductor (undoped InGaAs) is formed, and a collector contact layer 11 made of a semiconductor (high-concentration n-type InGaAs) doped with a first conductivity type dopant at a high concentration is formed on the collector layer 10. As a result, a collector-up type heterojunction bipolar transistor is formed.

  In the above embodiment, the guard ring region 17 that was not provided in the conventional collector-up HBT structure is provided around the intrinsic emitter layer 16, and the junction surface between the intrinsic emitter layer 16 and the base layer 9 is By being positioned below the upper surface of the guard ring region 17, the emitter-base junction surface recombination leakage current is effectively suppressed, and the reduction in current amplification factor (size effect) associated with device miniaturization is mitigated. It becomes possible to do.

  As a result, it is possible to provide an HBT having a high current amplification factor and excellent high-frequency characteristics and device lifetime, and a low power consumption large-scale integrated circuit composed of such an HBT can be provided.

  Next, the manufacturing method of the collector up type | mold HBT which concerns on this invention is demonstrated using the HBT cross-section figure of FIGS.

  First, as shown in FIG. 2, a buffer layer 2 made of InP and InGaAs is formed on a semi-insulating substrate 1 made of semi-insulating InP by an epitaxial growth method such as MBE or MOCVD. A sub-emitter layer 3 made of InP doped with an n-type impurity as a first conductivity type dopant is formed, and a high-concentration n-type doping for forming an ohmic electrode on the emitter is formed on the sub-emitter layer 3. An emitter contact layer 4 made of InGaAs is formed, and an emitter layer 5 composed of a high-concentration n-type doped InP layer (emitter lower layer) and an n-type doped InP layer (intrinsic emitter layer 16) is formed on the emitter contact layer 4. The emitter layer 5 is made of InGaAs that is not intentionally doped (undoped). The cap layer 6 of the membrane by sequentially epitaxially grown to form an epitaxial multilayer structure.

  Next, as shown in FIG. 3, a silicon nitride film (insulating film 7) is deposited on the thin film InGaAs layer (cap layer 6) by plasma CVD.

Next, as shown in FIG. 4, the silicon nitride film (insulating film 7) is removed by reactive ion etching using C ₂ F ₆ gas and SF ₆ gas using a photoresist patterned by photolithography as a mask. Then, the thin film InGaAs cap layer 6 is exposed, and then the photoresist of the mask is removed to form a pattern for leaving a silicon nitride film.

  Next, as shown in FIG. 5, the thin film InGaAs cap layer 6 and the emitter layer 5 (n-type InP emitter layer and high-concentration n-type InP emitter layer are formed using the silicon nitride film remaining pattern (insulating film 7) as a mask. The n-type InGaAs emitter contact layer 4 is exposed by selective wet etching. At this time, the n-type doped InP layer in the emitter layer 5 remaining without being etched becomes the intrinsic emitter layer 16.

Next, as shown in FIG. 6, an undoped InP layer (regrown emitter layer 8) serving as an external emitter region is epitaxially regrown on the n-type InGaAs emitter contact layer 4. Since InP is not grown on the silicon nitride film pattern mask (insulating film 7), undoped InP is grown in a shape surrounding the entire side surfaces of the intrinsic emitter layer 16 and the cap layer 6. The InP layer (regrowth emitter layer 8) is epitaxially regrown to at least the height below the insulating film remaining pattern ( insulating film pattern, insulating film 7).

  Next, as shown in FIG. 7, a photoresist pattern is formed outside the silicon nitride film pattern (insulating film 7), and Fe ions are implanted onto the regrowth emitter layer 8 using the photoresist pattern as a mask. . At this time, the portion of the regrowth emitter layer 8 masked by the photoresist pattern and not subjected to the ion implantation becomes the guard ring region 17.

  Next, as shown in FIG. 8, the photoresist pattern and the silicon nitride film pattern (insulating film 7) are removed, and the regrowth emitter layer 8 and the InGaAs cap layer 6 are exposed.

  Next, as shown in FIG. 9, the surface of the regrowth InP emitter layer 8 is cleaned, the thin film InGaAs cap layer 6 is removed by selective wet etching, and the n-type InP intrinsic emitter layer 16 is exposed. A base layer 9 made of p-type InGaAs, a collector layer 10 made of undoped InGaAs, and a collector contact layer 11 made of high-concentration n-type InGaAs are successively epitaxially regrown. A stable high-resistance region 15 is formed in the regrown InP emitter into which Fe ions are implanted at the growth temperature during this epitaxial regrown.

  Next, as shown in FIG. 10, after forming a photoresist pattern having the same size as the photoresist pattern used for the Fe ion implantation, the high-concentration n-type InGaAs collector contact layer 11 and the undoped InGaAs collector layer 10 are dry-etched. Etching is performed by wet etching to expose the high concentration p-type InGaAs base layer 9.

  Next, as shown in FIG. 11, after removing the photoresist pattern, the collector electrode 12 is deposited on the high-concentration n-type InGaAs collector contact layer 11 and the base electrode 13 is deposited on the high-concentration p-type InGaAs base layer 9. Form by law. Ti / Pt / Au / Pt / Ti was used as the collector electrode 12 and Pt / Ti / Pt / Au / Pt / Ti was used as the base electrode 13.

  Next, as shown in FIG. 12, the regrowth emitter layer 8 implanted with Fe ions is partially etched to expose the high-concentration n-type doped InGaAs emitter contact layer 4 and to form the emitter electrode 14 by vapor deposition lift-off. Ti / Pt / Au / Pt / Ti was used as the emitter electrode 14.

  In this way, the collector up type HBT according to the present invention shown in FIG. 1 is completed. The manufacturing method of the collector-up type HBT according to the present invention is characterized in that a semiconductor having the same or wide band gap as that of the intrinsic emitter layer 16 is provided at least around the intrinsic emitter layer 16 whose upper surface is covered with the cap layer 6. The guard ring region 17 is formed by epitaxial regrowth to the height of the upper surface of the layer 16.

  Thereafter, element isolation is performed by wet etching, and a passivation film is coated on the entire surface of the transistor. For the etching of each semiconductor layer, selective wet etching using a citric acid aqueous solution / hydrogen peroxide solution and a hydrochloric acid / phosphoric acid / acetic acid solution is used. As the passivation film, an organic insulating film such as BCB or polyimide and an inorganic insulating film such as a silicon oxide film or a silicon nitride film can be used.

In this embodiment, a typical structure of InP / InGaAs HBT has been described. However, the present invention is not limited to these, and an InAlAs / InGaAs using an InAlAs layer as an emitter.
Needless to say, the present invention can also be applied to a double heterojunction bipolar transistor structure in which an InGaAsP layer and an InP layer are introduced into the HBT or collector to increase the breakdown voltage.

  1: semi-insulating substrate, 2: buffer layer, 3: sub-emitter layer, 4: emitter contact layer, 5: emitter layer, 6: cap layer, 7: insulating layer, 8: regrown emitter layer, 9: base layer 10: collector layer, 11: collector contact layer, 12: collector electrode, 13: base electrode, 14: emitter electrode, 15: high resistance region, 16: intrinsic emitter layer, 17: guard ring region.

Claims (3)

A method of manufacturing a heterojunction bipolar transistor for manufacturing a collector-up type heterojunction bipolar transistor having a guard ring region around an intrinsic emitter layer,
Forming an emitter contact layer made of a semiconductor doped with a high concentration of a first conductivity type dopant on a substrate;
A first conductivity type dopant is doped on the emitter contact layer at a high concentration to form an emitter lower layer made of a semiconductor having a wider band gap than the emitter contact layer, and the first conductivity type dopant is formed on the emitter lower layer. Forming an intrinsic emitter layer doped with the same semiconductor as the underlying contact layer;
Forming a cap layer made of a semiconductor having a narrower band gap than the intrinsic emitter layer on the intrinsic emitter layer;
Depositing an insulating film on the cap layer, performing photoresist patterning on the insulating film, and forming an insulating film pattern using reactive ion etching using the photoresist pattern as a mask;
Etching the cap layer, the intrinsic emitter layer and the emitter lower layer using the insulating film pattern as a mask to expose the emitter contact layer;
Epitaxially re-growing an external emitter layer made of a semiconductor having at least the same or a wide band gap as the emitter layer on the exposed emitter contact layer to at least a height below the insulating film pattern ;
Forming a photoresist pattern covering the surface of the insulating film pattern , and performing ion implantation on the entire surface of the external emitter layer using the photoresist pattern as a mask;
Removing the photoresist pattern and the insulating film pattern , and further removing the cap layer by selective etching;
A base doped with a high concentration of a second conductivity type dopant exhibiting conductivity opposite to the first conductivity type on the regrowth outer emitter layer and on the intrinsic emitter layer exposed by removing the cap layer Forming a layer;
Forming a collector layer made of the same semiconductor as the base layer on the base layer. 2. The method of manufacturing a heterojunction bipolar transistor according to claim 1 , further comprising a step of forming a collector contact layer made of a semiconductor doped with a high concentration of a first conductivity type dopant on the collector layer. A method of manufacturing a heterojunction bipolar transistor for manufacturing a collector-up type heterojunction bipolar transistor having a guard ring region around an intrinsic emitter layer,
Forming a sub-emitter layer doped with a first conductivity type dopant on a semi-insulating substrate;
Forming an emitter contact layer made of a semiconductor doped with a high concentration of a first conductivity type dopant on the sub-emitter layer and having a narrower band gap than the sub-emitter layer;
A first conductivity type dopant is doped on the emitter contact layer at a high concentration to form an emitter lower layer made of a semiconductor having a wider band gap than the emitter contact layer, and the first conductivity type dopant is formed on the emitter lower layer. Forming an intrinsic emitter layer doped with the same semiconductor as the underlying contact layer;
Forming a cap layer made of a semiconductor having a narrower band gap than the intrinsic emitter layer on the intrinsic emitter layer;
Depositing an insulating film on the cap layer, performing photoresist patterning on the insulating film, and forming an insulating film pattern using reactive ion etching using the photoresist pattern as a mask;
Etching the cap layer, the intrinsic emitter layer and the emitter lower layer using the insulating film pattern as a mask to expose the emitter contact layer;
Epitaxially re-growing an external emitter layer made of a semiconductor having at least the same or a wide band gap as the emitter layer on the exposed emitter contact layer to at least a height below the insulating film pattern ;
Forming a photoresist pattern covering the surface of the insulating film pattern , and performing ion implantation on the entire surface of the external emitter layer using the photoresist pattern as a mask;
Removing the photoresist pattern and the insulating film pattern , and further removing the cap layer by selective etching;
On the outer emitter layer and the intrinsic emitter layer exposed by removing the cap layer, a base layer doped with a second conductivity type dopant exhibiting a conductivity opposite to the first conductivity type at a high concentration is formed. Forming, and
Forming a collector layer made of the same semiconductor as the base layer on the base layer, and forming a collector contact layer doped with a first conductivity type dopant at a high concentration on the collector layer;
A photoresist pattern is formed on a surface that includes at least the intrinsic emitter layer on the collector contact layer and does not include the ion-implanted region, and the collector cap layer and the collector layer are formed using the photoresist pattern as a mask. Etching to expose the base layer;
Forming a collector electrode and a base electrode on the collector contact layer and the base layer, respectively;
After forming a photoresist pattern at least outside the base electrode, the base contact layer and an external emitter layer including an ion implantation region are etched using the photoresist pattern as a mask to expose the emitter contact layer. And a step of forming an emitter electrode in the exposed portion.

Images