JP2008218636A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a reliable semiconductor device, and to provide the semiconductor device. <P>SOLUTION: In the method of manufacturing a hetero-junction bipolar transistor, an InGaAs buffer layer 2, InP sub-collector layer 3, InGaAs collector contact layer 4, InP layer 5, InGaAs collector layer 6, InGaAs base layer 7, and thin-film InP layer 8 are stacked in order on a semi-insulating InP substrate 1, and a silicon nitride film 9 is deposited on the thin-film InP layer 8. In each opening, an InP emitter layer 10, an InP layer 11, and an InGaAs emitter contact layer 12 are grown in order by epitaxial regrowth, and an emitter electrode metal 13 is so formed as to encompass the entire surface of the emitter contact layer 12. This manufacturing method includes a process wherein the silicon nitride film 9 is removed, leaving only a part existing in the periphery of the opening and the exposed thin-film InP layer 8 is removed to expose the base layer 7. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device taking a heterojunction bipolar transistor as an example.

  The heterojunction bipolar transistor (HBT) uses a semiconductor material having a wider band gap than the base for the emitter, so that a higher current amplification factor can be obtained even when the impurity concentration of the base is higher than that of the emitter. It can be maintained, and the thinning of the base layer and the reduction of the base resistance can be realized at the same time.

  Furthermore, when a III-V compound semiconductor is used, advantages such as widening the degree of freedom of combination of heterojunctions depending on the selection of materials and integration with optical devices as well as electronic devices are increased.

In III-V compound semiconductor HBTs, current gain, which is an indicator of high-speed performance, is excellent in the electron transport characteristics of InGaAs especially in npn type InP / InGaAs HBTs using InP as the emitter material and InGaAs as the base material. cutoff frequency _{f T} is the best performance is achieved in the in the transistor in excess of 700 GHz. Actually, as described in Non-Patent Document 1 below, an InP / InGaAs HBT having a fine emitter with a planar transistor size of 0.25 μm × 3 μm was prototyped, and a current gain cutoff frequency f _{T as} high as 710 GHz has been reported. In addition, InP / InGaAsHBT has a low turn-on voltage at the emitter / base junction, which is advantageous for reducing the power consumption of the integrated circuit.

  Further, in the manufacturing process, since a complete selective wet etching solution can be used for InGaAs and InP, respectively, particularly in etching processing, the etching wafer surface uniformity is excellent.

  InP / InGaAs HBT is advantageous as a device constituting a large-scale integrated circuit, in combination with excellent in-wafer uniformity of the turn-on voltage between the emitter and base junction corresponding to the threshold value.

  Regarding the manufacture of these HBTs, a manufacturing method has been adopted in which an HBT structure laminated by normal epitaxial growth is etched in order from the upper layer side, each semiconductor layer is exposed, and emitter, base, and collector electrodes are formed. A mesa transistor structure is formed.

InP / InGaAsHBT effectively utilizes selective etching of InGaAs and InP layers to expose the base layer and collector contact layer, and by evaporation lift-off method, p-type ohmic electrode metal is used as the base layer and n-type ohmic electrode metal is used as the emitter. It forms in a contact layer and a collector contact layer, respectively. Further, a process is generally performed in which elements are separated by etching, and a semiconductor surface is passivated with a spin coating organic insulating film such as polyimide or BCB.
JP-A-8-288297 Paper `` Walid Hafez, William Snodgrass, and Milton Feng, APPLIED PHYSICS LETTERS 87, 252109 (2005) '' Paper "Fukai et al., IEICE Transactions C, VOL. J89-C NO.9 SEPTEMBER, 2006, pp. 589-596"

  As the emitter mesa plane size is reduced, a surface recombination base current is generated between the periphery of the emitter mesa and the external base region, and the current amplification factor is significantly reduced. This becomes prominent as the ratio of the peripheral length to the emitter intrinsic region increases. In order to suppress this surface recombination leakage current, it is effective to provide a recombination base current suppression region called a guard ring (GR) structure (synonymous with the ridge structure) around the emitter mesa on the surface of the external base layer. This is often used in a GaAs-based HBT epitaxially grown on a GaAs substrate (for example, AlGaAs / GaAsHBT, InGaP / GaAsHBT), and is generated between the emitter mesa and the base layer when the thinned emitter layer is depleted. This suppresses unnecessary recombination base current.

  Even in an InP / InGaAs HBT using InGaAs with a relatively low surface recombination velocity as a base layer, the formation of the emitter GR structure is desirable, and the formation of the GR structure is effective in suppressing the surface recombination base current. It has been confirmed that a significant effect is also shown in terms of improving the device lifetime (see Non-Patent Document 2 above), and in the mesa type HBT, formation of the emitter GR structure is indispensable.

  As a method for forming the InP emitter layer GR structure, for example, as shown in Patent Document 1, the InP emitter layer is etched halfway to form a staircase shape, and the protruding region of the lower InP functions as a guard ring region. ing. However, in this method, in order to completely deplete the InP layer GR region, it is necessary to leave the thin InP emitter layer with good uniformity and reproducibility, and the etching control of the InP emitter layer for that purpose is difficult.

  The present invention has been made in view of the above problems, and a problem to be solved by the invention is to provide a semiconductor device manufacturing method and a semiconductor device excellent in reliability.

In order to solve the above problems, in the present invention, as described in claim 1,
A first semiconductor layer and a second semiconductor layer having an area smaller than the area of the first semiconductor layer and made of the same material as the first semiconductor layer are stacked in this order on the substrate. A method of manufacturing a semiconductor device having a structure comprising: forming a dielectric film having an opening on the first semiconductor layer; and forming the dielectric film on the first semiconductor layer exposed in the opening. And a step of epitaxially growing the second semiconductor layer.

In the present invention, as described in claim 2,
A first emitter layer and a second emitter layer having an area smaller than the area of the first emitter layer and made of the same material as the first emitter layer are stacked in this order on the substrate. A method of manufacturing a heterojunction bipolar transistor having a structure comprising: forming a dielectric film having an opening on the first emitter layer; and on the first emitter layer exposed in the opening. And a step of epitaxially growing the second emitter layer.

In the present invention, as described in claim 3,
A sub-collector layer highly doped with a first conductivity type dopant, a collector contact layer heavily doped with a first conductivity type dopant, a collector layer, and a conductivity opposite to the first conductivity type are formed on a substrate. A base layer heavily doped with a second conductivity type dopant, a first emitter layer having a wider band gap than the base layer, doped with a first conductivity type dopant, and doped with a first conductivity type dopant, A method for manufacturing a heterojunction bipolar transistor having a structure in which a second emitter layer having a wider band gap than a base layer and an area smaller than the area of the first emitter layer is laminated in this order. Then, a thin film semiconductor layer having a portion to be the first emitter layer is epitaxially grown on the base layer. A second step of depositing a dielectric film on the thin film semiconductor layer, a photoresist patterning on the dielectric film, and etching opening the dielectric film using reactive ion etching. A third step of exposing the surface of the thin film semiconductor layer to a portion, and a fourth step of epitaxially re-growing the second emitter layer and the emitter contact layer in this order on the thin film semiconductor layer exposed in the opening. A fifth step of forming an emitter electrode metal so as to cover at least the entire surface of the emitter contact layer, and leave other portions around the opening of the dielectric film with reactive ions remaining. A sixth step of removing the thin film semiconductor layer by etching and exposing the thin film semiconductor layer, and then removing the thin film semiconductor layer in an exposed portion to expose the base layer. Constitute a method for manufacturing a semiconductor device according to claim and.

In the present invention, as described in claim 4,
4. The method of manufacturing a semiconductor device according to claim 1, wherein the dielectric film is a silicon nitride film.

In the present invention, as described in claim 5,
A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1, 2, 3, or 4 is configured.

  For example, a thin film semiconductor layer serving as a guard ring can be easily formed with a uniform thickness, and a semiconductor device manufacturing method and a semiconductor device with excellent reliability can be provided.

  In the present invention, for example, a thin film semiconductor layer having a portion corresponding to a guard ring (GR) region is provided in advance on the entire surface of the wafer by continuous epitaxial growth, and the intrinsic emitter layer and the emitter contact layer are selectively formed by the subsequent epitaxial selective regrowth method. It is formed by epitaxial regrowth. Therefore, in the method for manufacturing a semiconductor device according to the present invention, the thin film semiconductor layer corresponding to the GR region is formed to have a desired thickness from the beginning, and the film thickness is not regulated by etching. A remarkable feature is that the thickness is excellent in film thickness controllability and uniformity in the wafer surface.

  In addition, the method for manufacturing a heterojunction bipolar transistor according to the present invention also has a feature that a dielectric film (for example, a silicon nitride film) for protecting the GR region and the surface of the intrinsic emitter layer can be efficiently formed.

  Accordingly, it is possible to provide a low power consumption large scale integrated circuit composed of an HBT having a high current amplification factor and excellent high frequency characteristics and device lifetime.

(Embodiment example)
As an embodiment of the semiconductor device manufacturing method according to the present invention, an InP / InGaAsHBT manufacturing method will be described with reference to the drawings. In this case, the n-type is the first conductivity type and the p-type is the second conductivity type.

  FIG. 1 shows an InP and InGaAs buffer layer 2, an InP subcollector layer 3 doped with high-concentration n-type impurities, and an ohmic electrode on a collector by an epitaxial growth method such as MBE on a semi-insulating InP substrate 1 that is a substrate. A high-concentration n-type doped InGaAs collector contact layer 4 for forming, a high-concentration n-type doped InP etching stopper layer 5 serving as an etching stopper layer during selective wet etching, an intentionally undoped (undoped) InGaAs collector layer 6; A p-type InGaAs base layer 7 highly doped with carbon and an n-type doped thin InP layer 8 that is a thin-film semiconductor layer having a portion serving as a first emitter layer (first semiconductor layer) are epitaxially grown in this order. Epitaxial product It shows the structure. A step of epitaxially growing the thin InP layer 8 on the InGaAs base layer 7 is a first step.

  FIG. 2 shows a step (second step) of depositing a silicon nitride film 9 as a dielectric film on the thin InP layer 8 by a plasma CVD method.

FIG. 3 shows that the silicon nitride film 9 is removed by reactive ion etching using C ₂ F ₆ gas and SF ₆ gas, using a photoresist with a width of about 0.3 μm patterned with fine dimensions by photolithography as a mask. A process of forming an opening and exposing the thin-film InP layer 8 only in the opening (third process) is shown.

FIG. 4 shows an n-type doped InP emitter layer 10 (n− in the figure) that is a second emitter layer (second semiconductor layer) on the thin InP layer 8 exposed in the opening of the silicon nitride film 9 in the above process. display in InP 10), the high concentration InP layer 11 (in the figure that the n-type impurity doped, displayed in n ⁺ -InP 11), InGaAs emitter contact layer 12 doped with high concentration n-type impurity (in the drawing, n ^{+ -} A step (fourth step) in which epitaxial regrowth is sequentially performed by MBE or the like is shown. During this epitaxial regrowth, InP and InGaAs semiconductor layers are not grown on the silicon nitride film mask other than the silicon nitride film opening, so that the InP emitter layer 10 is formed only on the thin InP layer 8 in the opening provided in the silicon nitride film. The InP layer 11 and the InGaAs emitter contact layer 12 are selectively epitaxially grown.

  FIG. 5 shows a step of forming an n-type ohmic metal composed of Ti / Pt / Au / Pt / Ti as the emitter electrode metal 13 by vapor deposition lift-off so as to cover at least the entire surface of the InGaAs emitter contact layer 12. (5th process) is shown.

In FIG. 6, a photoresist pattern is formed so as to leave only the silicon nitride film 9 surrounding the InP emitter layer 10, InP layer 11 and InGaAs emitter contact layer 12 grown in the opening in the silicon nitride film, and the InP emitter layer 10. All of the silicon nitride film 9 except the periphery of the InP layer 11 and the InGaAs emitter contact layer 12 is removed by the reactive ion etching method using C ₂ F ₆ gas and SF ₆ gas, and the exposed thin InP layer 8 is thereby removed. The process (6th process) removed by the selective wet etching method by hydrochloric acid / phosphoric acid / acetic acid solution is shown. As a result, the thin InP layer 8 is only a portion corresponding to the first emitter layer, and the thin InP layer 8 is formed immediately below the silicon nitride film 9 in contact with the side walls of the InP emitter layer 10, InP layer 11 and InGaAs emitter contact layer 12. A guard ring region is formed.

  FIG. 7 shows a step (seventh step) of forming a p-type ohmic metal composed of Pt / Ti / Pt / Au / Pt / Ti as the base electrode metal 14 by the vapor deposition lift-off method.

  FIG. 8 shows a p-type InGaAs base layer 7, an undoped InGaAs collector layer 6, and an n-type InP etching stopper using a photoresist mask patterned on the emitter-base mesa structure including the emitter electrode metal 13 and the base electrode metal 14. After removing the layer 5 by selective wet etching and exposing the heavily doped n-type InGaAs collector contact layer 4, an ohmic collector electrode metal 15 is formed on the InGaAs collector contact layer 4 by vapor deposition and lift-off, The process (8th process) which performs isolation | separation between elements is shown. For the etching of each semiconductor layer, selective wet etching using a citric acid aqueous solution / hydrogen peroxide solution and a hydrochloric acid / phosphoric acid / acetic acid solution is used. A Ti / Pt / Au laminated structure is used as the collector electrode.

  Thereafter, a passivation film is coated on the entire surface of the transistor. As the passivation film, an organic insulating film such as BCB or polyimide and an inorganic insulating film such as a silicon oxide film or a silicon nitride film can be used.

  The layer thickness and doping concentration of each layer of the epitaxial structure in a typical heterojunction bipolar transistor (HBT) are, for example, as follows.

1-4,
InP of buffer layer 2 is non-doped, thickness 200 mm
N ⁺ -InP of the subcollector layer 3 has a doping concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 3500 mm.
The n ⁺ -InGaAs of the collector contact layer 4 has a doping concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 300 μm.
The n ⁺ -InP of the etching stopper layer 5 has a doping concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 200 μm.
The InGaAs of the collector layer 6 is non-doped and has a thickness of 3000 mm.
The p ⁺ -InGaAs of the base layer 7 has a doping concentration of 4 × 10 ¹⁹ cm ⁻³ and a thickness of 500 mm.
The n-InP of the emitter layers 8 and 10 has a doping concentration of 1 × 10 ^{16 to} 3 × 10 ¹⁷ cm ⁻³ and a thickness of 700 mm.
The InP layer 11 is n ⁺ -InP, has a doping concentration of 2 × 10 ¹⁹ cm ⁻³ , and a thickness of 200 μm.
The n ⁺ -InGaAs of the emitter contact layer 12 has a doping concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 1000 mm.

  The thickness of the emitter guard ring layer (corresponding to the peripheral portion of the thin-film InP layer 8 and the first emitter layer in the portion immediately below the silicon nitride film 9 in FIGS. 6 to 8 when formed by the first step) In order to obtain the effect of passivation, a minimum of 100 mm is required. Further, if this thickness is larger than 400 mm, the effect of depletion is reduced.

  The width of the guard ring is a minimum of 0.1 μm in consideration of processing accuracy, and a maximum of 0.5 μm is appropriate in consideration of parasitic resistance and parasitic capacitance. Here, the width of the guard ring is the distance from the side wall of the thin film InP layer 8 as the first emitter layer to the side wall of the InP emitter layer 10 as the second emitter layer in FIGS. If the width of the InP layer 8 is W1, and the width of the InP emitter layer 10 is W2, this corresponds to (W1-W2) / 2.

  The width of the opening of the silicon nitride film 9 is at least about 0.1 μm considering the processing accuracy of electron beam exposure. From the viewpoint of miniaturizing the emitter for high-speed device and low power consumption, the width of the opening is preferably 1.0 μm or less.

  The thickness of the silicon nitride film 9 in the film forming direction is preferably 0.15 μm or more in consideration of the film quality, and preferably 0.3 μm or less in consideration of thermal stress during the process.

  The distance between the base electrode and the emitter mesa (the distance between the side wall of the base electrode metal 14 and the side wall of the thin-film InP layer 8 in FIGS. 7 and 8) is at least 0.1 μm due to processing accuracy, and is larger than 0.5 μm. Since the high frequency characteristics deteriorate due to an increase in parasitic capacitance, the thickness is preferably 0.5 μm or less.

  In this embodiment, plasma CVD is used to form the dielectric film, but sputtering can also be used. MOVPE can also be used for epitaxial growth of the semiconductor layer.

  FIG. 9 is an example of a schematic plan view of the HBT.

  The expected characteristics and yield improvement effect of the HBT according to the present invention are as follows.

Current gain (β): 50
Cutoff frequency f _T : 177 GHz
Maximum oscillation frequency f _max : 260 GHz
Expected yield improvement:
In the conventional method of forming an InP emitter GR structure by etching, the distribution of β was ± 10%, but it was improved to ± 3% by the method of forming an InP emitter GR structure according to the present invention. Scaling becomes possible.

  In this embodiment, a typical structure of InP / InGaAsHBT has been described. However, the present invention is not limited to these, and an InAlAs / InGaAsHBT using an InAlAs layer as an emitter or InGaAsP as a collector. Needless to say, the present invention can also be applied to a double hetero HBT structure in which layers and InP layers are introduced to increase the breakdown voltage.

  In this embodiment, application to HBT has been described, but application to other devices such as a photodiode is also possible.

  In the above description, the n-type is the first conductivity type and the p-type is the second conductivity type. However, the p-type is the first conductivity type and the n-type is the second conductivity type. The effect of the present invention appears similarly.

  As described above, for example, by using the manufacturing method of the HBT as the manufacturing method of the present invention, it is possible to solve the problems of the prior art and provide an HBT having excellent high frequency characteristics and reliability. Can do.

It is a figure explaining the 1st process in the embodiment of the present invention. It is a figure explaining the 2nd process in the example of an embodiment of the invention. It is a figure explaining the 3rd process in the example of an embodiment of the invention. It is a figure explaining the 4th process in the example of an embodiment of the invention. It is a figure explaining the 5th process in the example of an embodiment of the invention. It is a figure explaining the 6th process in the example of an embodiment of the invention. It is a figure explaining the 7th process in the embodiment of the present invention. It is a figure explaining the 8th process in the example of an embodiment of the invention. It is an example of the plane schematic diagram of HBT.

Explanation of symbols

  1: semi-insulating InP substrate, 2: InP, InGaAs buffer layer, 3: InP subcollector layer, 4: InGaAs collector contact layer, 5: InP etching stopper layer, 6: InGaAs collector layer, 7: InGaAs base layer, 8 : Thin InP layer, 9: Silicon nitride film, 10: InP emitter layer, 11: InP layer, 12: InGaAs emitter contact layer, 13: emitter electrode metal, 14: base electrode metal, 15: collector electrode metal.

Claims (5)

A first semiconductor layer and a second semiconductor layer having an area smaller than the area of the first semiconductor layer and made of the same material as the first semiconductor layer are stacked in this order on the substrate. A method of manufacturing a semiconductor device having a structure comprising:
Forming a dielectric film having an opening on the first semiconductor layer;
And a step of epitaxially growing the second semiconductor layer on the first semiconductor layer exposed in the opening. A first emitter layer and a second emitter layer having an area smaller than the area of the first emitter layer and made of the same material as the first emitter layer are stacked in this order on the substrate. A method of manufacturing a heterojunction bipolar transistor having the structure:
Forming a dielectric film having an opening on the first emitter layer;
And a step of epitaxially growing the second emitter layer on the first emitter layer exposed in the opening. A sub-collector layer highly doped with a first conductivity type dopant, a collector contact layer heavily doped with a first conductivity type dopant, a collector layer, and a conductivity opposite to the first conductivity type are formed on a substrate. A base layer heavily doped with a second conductivity type dopant, a first emitter layer having a wider band gap than the base layer, doped with a first conductivity type dopant, and doped with a first conductivity type dopant, A method for manufacturing a heterojunction bipolar transistor having a structure in which a second emitter layer having a wider band gap than a base layer and an area smaller than the area of the first emitter layer is laminated in this order. And
A first step of epitaxially growing a thin film semiconductor layer having a portion to be the first emitter layer on the base layer;
A second step of depositing a dielectric film on the thin film semiconductor layer;
A third step of performing photoresist patterning on the dielectric film, opening the dielectric film by etching using reactive ion etching, and exposing the surface of the thin film semiconductor layer in the opening;
A fourth step of epitaxially re-growing the second emitter layer and the emitter contact layer in this order on the thin film semiconductor layer exposed in the opening;
A fifth step of forming an emitter electrode metal so as to cover at least the entire surface of the emitter contact layer;
The other part of the dielectric film is removed using reactive ion etching while leaving the part around the opening, and after exposing the thin film semiconductor layer, the exposed thin film semiconductor layer is removed, And a sixth step of exposing the base layer.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the dielectric film is a silicon nitride film.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.

Images