KR20210058620A - Hetero junction bipolar transistor - Google Patents

Abstract

Provided is a hetero-junction bipolar transistor including: a sub-collector layer sequentially stacked on a substrate; a collector layer and a base layer; an emitter structure disposed on the base layer, in which an emitter structure has an emitter layer sequentially stacked, an emitter cap layer, and an emitter electrode; a first electrode disposed on an upper surface of the emitter electrode; a second electrode disposed on the base layer and spaced apart from the emitter structure; an insulating film covering the first electrode, the second electrode, and the emitter structure on the base layer; and an emitter cap electrode connected to the first electrode through the insulating film on the first electrode, and extending from an upper surface of the first electrode onto the second electrode, wherein the emitter layer has a reverse mesa shape and having a width smaller than the width of the emitter electrode, and the insulating layer is interposed between the second electrode and the emitter cap electrode on the second electrode.

Description

Heterojunction bipolar transistor {HETERO JUNCTION BIPOLAR TRANSISTOR}

The present invention relates to a heterojunction bipolar transistor, and more particularly, to a heterojunction bipolar transistor including a compound semiconductor.

Compound semiconductor (HBT) heterojunction bipolar transistor (HBT) is attracting attention as an ultra-high-speed / ultra-high frequency semiconductor device that can be used in the transmitting and receiving end of an ultra-high-speed broadband communication network.

In recent years, research is being conducted to realize faster ultra-high speed/ultra-high frequency operation by improving the characteristics of the device by scale-down and reducing the parasitic component of the device.

Compound semiconductor (HBT) heterojunction bipolar transistor (HBT) is attracting attention as an ultra-high-speed / ultra-high frequency semiconductor device that can be used in the transmitting and receiving end of an ultra-high-speed broadband communication network.

In recent years, research is being conducted to realize faster ultra-high speed/ultra-high frequency operation by improving the characteristics of the device by scale-down and reducing the parasitic component of the device.

The heterojunction bipolar transistor according to embodiments of the present invention for solving the above-described technical problems includes a sub-collector layer, a collector layer and a base layer sequentially stacked on a substrate, an emitter structure disposed on the base layer, the The emitter structure has an emitter layer, an emitter cap layer, and an emitter electrode that are sequentially stacked, a first electrode disposed on an upper surface of the emitter electrode, and a first electrode disposed spaced apart from the emitter structure on the base layer. 2 electrodes, an insulating film covering the first electrode, the second electrode, and the emitter structure on the base layer, and an insulating film on the first electrode through the insulating film and connected to the first electrode, It may include an emitter cap electrode extending from an upper surface onto the second electrode. The emitter layer may have a reverse mesa shape, but may have a width smaller than that of the emitter electrode. On the second electrode, the insulating layer may be interposed between the second electrode and the emitter cap electrode.

In a method of manufacturing a heterojunction bipolar transistor according to embodiments of the present invention, a preliminary emitter cap layer and a preliminary emitter layer under the emitter electrode may be patterned using an emitter electrode. Accordingly, the emitter electrode, the emitter cap layer, and the emitter layer may be self-aligned, and a heterojunction bipolar transistor having improved structural stability may be manufactured.

According to the present invention, as the emitter cap electrode is formed to have a large area, the resistance of the emitter electrode, the first electrode, and the emitter cap electrode may be low, and the heterojunction bipolar transistor having a small size and improved electrical characteristics Can be prepared.

1 to 10 are cross-sectional views illustrating heterojunction bipolar transistors according to embodiments of the present invention.
11 is an SEM photograph of a heterojunction bipolar transistor manufactured according to embodiments of the present invention.

In order to fully understand the configuration and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms and various modifications may be made. However, it is provided to complete the disclosure of the present invention through the description of the present embodiments, and to completely inform the scope of the present invention to those of ordinary skill in the art to which the present invention pertains. Those of ordinary skill in the art will understand that the inventive concept may be practiced in any suitable environment.

The terms used in the present specification are for describing exemplary embodiments and are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated in the phrase. As used in the specification,'comprises' and/or'comprising' means the presence of one or more other components, steps, actions and/or elements in addition to the mentioned elements, steps, actions and/or elements. Or does not preclude additions.

When a film (or layer) is referred to herein as being on another film (or layer) or substrate, it may be formed directly on the other film (or layer) or substrate, or a third film ( Or a layer) may be interposed.

In various embodiments of the present specification, terms such as first, second, and third are used to describe various regions, films (or layers), and the like, but these regions and films should not be limited by these terms. do. These terms are only used to distinguish one region or film (or layer) from another region or film (or layer). Accordingly, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Parts indicated by the same reference numerals throughout the specification represent the same elements.

Terms used in the embodiments of the present invention may be interpreted as meanings commonly known to those of ordinary skill in the art, unless otherwise defined.

Hereinafter, a heterojunction bipolar transistor according to the concept of the present invention will be described with reference to the drawings. 1 to 12 are cross-sectional views illustrating heterojunction bipolar transistors according to embodiments of the present invention.

Referring to FIG. 1, a substrate 100 may be provided. The substrate 100 may be a semi-insulating compound semiconductor substrate. For example, it may be a gallium arsenide (GaAs) or indium phosphorus (InP) substrate.

Layers constituting a heterojunction bipolar transistor (HBT) may be formed on the substrate 100. A sub-collector layer 110, a pre-collector layer 120, a pre-base layer 130, a pre-emitter layer 140, and a pre-emitter cap layer 150 may be formed on the substrate 100. The layers 110 to 150 may be epitaxial layers. The layers 110 to 150 are gallium arsenide (GaAs), indium phosphorus (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), indium gallium phosphorus ( InGaP), aluminum gallium arsenide (AlGaAs), or indium aluminum gallium arsenide (InAlGaAs) may be formed by a combination of a compound semiconductor composed of a III-V group material. For example, when the substrate 100 is indium phosphorus (InP), the n+ conductivity type sub-collector layer 110 may be formed using _{indium gallium arsenide (In x} Ga _{1-x As).} The sub-collector layer 110 may have a thickness of about 200 nm, and a doping concentration of about 2×10 ¹⁹ cm ^-3 . An n-conductive pre-collector layer 120 may be formed using indium aluminum gallium arsenide (In _x Al _y Ga _{1-xy As).} The pre-collector layer 120 may have a thickness of about 48 nm, and a doping concentration of about 1×10 ¹⁶ cm ^-3 . The p+ conductivity type preliminary base layer 130 may be formed using indium gallium arsenide (In _x Ga _{1-x As).} The preliminary base layer 130 may have a thickness of about 35 nm, and a doping concentration of about 5.7×10 ¹⁹ cm ^-3 . An n-type preliminary emitter layer 140 may be formed using indium phosphorus (InP). The preliminary emitter layer 140 may have a thickness of about 50 nm, and a doping concentration of about 5×10 ¹⁷ cm ^-3 . An n+ conductivity type preliminary emitter cap layer 150 may be formed using indium phosphorus (InP) or indium gallium arsenide (In _x Ga _{1-x As).} The preliminary emitter cap layer 150 may have a thickness of about 90 to 200 nm, and a doping concentration of about 1×10 ¹⁹ to 3×10 ¹⁹ cm ^-3 . The layers 110 to 150 may be formed by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapor Deposition (MOCVD).

Referring to FIG. 2, an emitter electrode 160 may be formed on the preliminary emitter cap layer 150. For example, the emitter electrode 160 may be formed using a lift-off process. Specifically, after a photoresist film is formed on the preliminary emitter cap layer 150, a photoresist pattern may be formed by patterning the photoresist film. The photoresist layer may be patterned using an electron-beam lithography process. Thereafter, after depositing a metal layer on the photoresist pattern, the photoresist pattern may be removed. A portion of the metal layer formed on the photoresist pattern may be removed together when the photoresist pattern is dissolved. As described above, a part of the metal layer remaining in the pattern of the photoresist pattern may constitute the emitter electrode 160. In this case, since electron beam lithography having a very small wavelength of the light source is used, the width of the photoresist pattern may be very small, and the size of the emitter electrode 160 may also be small. Accordingly, a heterojunction bipolar transistor having a small size can be provided. The width of the emitter electrode 160 may be 0.1um to 0.3um. The emitter electrode 160 may include titanium (Ti), platinum (Pt), or gold (Au), or may include a multilayer film formed using at least one of them.

Referring to FIG. 3, the preliminary emitter cap layer 150 and the preliminary emitter layer 140 are etched to form the emitter cap layer 152 and the emitter layer 142, and the preliminary base layer 130 may be exposed. .

A first patterning process may be performed on the preliminary emitter cap layer 150. The first patterning process may be wet etching. For example, the first patterning process may be performed using an etching solution such as _{phosphoric acid (H 3} PO ₄ ), hydrochloric acid (HCl), aqueous ammonia (NH ₄ OH), or hydrogen peroxide (H ₂ O _{2 ).} For example, when the preliminary emitter cap layer 150 includes indium gallium arsenide (InGaAs), phosphoric acid (H ₃ PO ₄ ), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O) are 1:1:25 An etching solution mixed in a ratio may be used. The emitter cap layer 152 may be formed by etching the preliminary emitter cap layer 150 by the first patterning process. In this case, an undercut area UC may be formed under the emitter electrode 160. For example, as the first patterning process is performed by wet etching, a part of the preliminary emitter cap layer 150 under the emitter electrode 160 may be etched together. Accordingly, the width of the emitter cap layer 152 may be formed to be smaller than the width of the emitter electrode 160. The width of the emitter cap layer 152 may be formed to decrease toward the substrate 100. In some embodiments, the lower surface of the emitter electrode 160 may be exposed.

Alternatively, the first patterning process may be a dry etching process. The first patterning process may be performed by a reactive ion etching (RIE) or inductive coupled plasma (ICP) etching process using a reactive gas such as _{BCl 3} , Cl ₂ , CH ₄ , CHF ₃ , CCl ₄ or SF _6. . In this case, the side surface of the emitter cap layer 152 may be formed to be inclined with respect to the lower surface of the emitter electrode 160 by the etching process. In this case, the width of the emitter cap layer 152 may be formed to decrease toward the substrate 100.

A second patterning process may be performed on the preliminary emitter layer 140. The second patterning process may be wet etching. For example, the second patterning process may be performed using an etching solution such as _{phosphoric acid (H 3} PO ₄ ), hydrochloric acid (HCl), aqueous ammonia (NH ₄ OH), or hydrogen peroxide (H ₂ O _{2 ).} For example, when the preliminary emitter layer 140 contains indium phosphorus (InP), _{an etching solution in which hydrochloric acid (HCl) and phosphoric acid (H 3} PO ₄ ) are mixed in a ratio of 1:4 may be used. In this case, the width of the emitter layer 142 may be formed to decrease toward the substrate 100. Accordingly, the width of the formed emitter layer 142 may be smaller than the width of the emitter electrode 160.

The emitter electrode 160, the emitter cap layer 152 and the emitter layer 142 may constitute the emitter structure ES.

In embodiments of the present invention, the emitter electrode 160 may be used to pattern the preliminary emitter cap layer 150 and the preliminary emitter layer 140 under the emitter electrode 160. Accordingly, the emitter electrode 160, the emitter cap layer 152, and the emitter layer 142 may be self-aligned. That is, when the method of manufacturing a heterojunction bipolar transistor according to embodiments of the present invention is used, a heterojunction bipolar transistor with improved structural stability can be provided.

Referring to FIG. 4, a mask pattern MP may be formed on the preliminary base layer 130. The mask pattern MP may be disposed to be spaced apart from the emitter structure ES. The upper surface of the preliminary base layer 130 exposed by the mask pattern MP may include a region in which the second electrode 174 (refer to FIG. 5) is formed in a process to be described later.

A metal layer 170 may be formed on the preliminary base layer 130. For example, the metal layer 170 may be formed by depositing a metal material on the preliminary base layer 130. In this case, the metal layer may cover the emitter structure ES and the mask pattern MP. In this case, a metal material may not be deposited under the emitter electrode 160, and the emitter layer 142 having a width smaller than the width of the emitter electrode 160 may be spaced apart from the metal layer 170. For example, one half of the difference between the widths of the emitter electrode 160 and the emitter layer 142 may correspond to the first length in which the emitter layer 142 is undercut from the emitter electrode 160, The first length may be the same as the distance between the emitter layer 142 and the metal layer 170. The metallic material is a compound semiconductor with gold (Au), silver (Ag), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), or zinc (Zn) in ohmic contact with the compound semiconductor. It may contain the same metal.

Referring to FIG. 5, a first electrode 172 and a second electrode 174 may be formed. For example, the second electrode 174 may be formed using a lift-off process. In detail, the mask pattern MP may be removed, and in this case, a part of the metal layer 170 positioned on the mask pattern MP may be removed together. A part of the metal layer 170 positioned on the upper surface of the emitter electrode 160 may constitute the first electrode 172. A part of the metal layer 170 remaining on the upper surface of the preliminary base layer 130 may constitute the second electrode 174. The second electrode 174 may be spaced apart from the emitter layer 142 by the first length. That is, according to embodiments of the present invention, the distance at which the second electrode 174 is separated from the emitter layer 142 may be adjusted through the length at which the emitter layer 142 is undercut. Accordingly, the gap between the emitter layer 142 and the second electrode 174 may be formed to be small, and a heterojunction bipolar transistor having a small size may be provided. The second electrode 174 may be a base electrode connected to the preliminary base layer 130.

Referring to FIG. 6, a first insulating layer 180 covering the entire surface of the preliminary base layer 130 may be formed. The first insulating layer 180 may cover the entire surface of the preliminary base layer 130 including the emitter structure ES, the first electrode 172 and the second electrode 174. In this case, the first insulating layer 180 may extend between the emitter structure ES and the second electrode 174 to separate the emitter structure ES and the second electrode 174. The first insulating layer 180 may include at least one of a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer.

The opening OP may be formed by removing the first insulating layer 180 on the first electrode 172. The opening OP may be patterned by a photolithography process. The opening OP may expose the upper surface of the first electrode 172.

Referring to FIG. 7, an emitter cap electrode 192 may be formed on the insulating layer 180. The emitter cap electrode 192 may be formed by forming a metal layer on the insulating layer 180 and then performing a lift-off process on the metal layer. The emitter cap electrode 192 may be connected to the first electrode 172 through the opening OP of the first insulating layer 180. The emitter cap electrode 192 may extend from the top of the first electrode 172 to the top surface of the second electrode 174 through the side surface of the emitter structure ES. In this case, the first insulating layer 180 may be interposed between the second electrode 174 and the emitter cap electrode 192 on the second electrode 174. That is, the emitter cap electrode 192 may be spaced apart and insulated by the emitter structure ES, the second electrode 174 and the first insulating layer 180. A part of the first insulating layer 180 interposed between the second electrode 174 and the emitter cap electrode 192 may function as a dielectric layer of the capacitor.

The emitter electrode 160, the first electrode 172, and the emitter cap electrode 192 of the emitter structure ES may serve as electrodes of the emitter structure ES. At this time, since the emitter electrode 160 and the first electrode 172 are patterned to have a narrow width, the resistance may be very high. However, according to the present invention, as the emitter cap electrode 192 is formed to have a large area, the resistance of the emitter electrode 160, the first electrode 172, and the emitter cap electrode 192 may be low. , It is possible to provide a heterojunction bipolar transistor having a small size and improved electrical characteristics.

Referring to FIG. 8, a photoresist pattern covering the second electrode 174 and the emitter cap electrode 192 is formed on the preliminary base layer 130, and the photoresist pattern is used as a mask. And by etching the pre-collector layer 120, the base layer 132 and the collector layer 122 may be formed. In this case, the first insulating layer 180 may be etched together. The first insulating layer 182, the base layer 132, and the collector layer 122 patterned by the etching process may expose an upper surface of the sub-collector layer 110. The exposed upper surface of the sub-collector layer 110 may include a region in which the collector electrode 194 is formed in a process to be described later.

A collector electrode 194 may be formed on the sub-collector layer 110. For example, the collector electrode 194 may be formed using a lift-off process. The collector electrode 194 may be formed on the exposed upper surface of the sub-collector layer 110. In the collector electrode 194, the metal material is gold (Au), silver (Ag), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), which is in ohmic contact with a compound semiconductor. Alternatively, a multilayer film may be included that includes a metal such as zinc (Zn), or is formed using at least one of them.

Referring to FIG. 9, a second insulating layer 184 covering the entire surface of the sub-collector layer 110 may be formed. The second insulating layer 184 may cover the emitter cap electrode 192, the patterned first insulating layer 182, and the collector electrode 194, and may cover side surfaces of the collector layer 122 and the base layer 132. Can be covered. The second insulating layer 184 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

Thereafter, the emitter cap electrode 192 may be exposed by patterning the second insulating layer 184.

Referring to FIG. 10, a wiring layer 196 may be formed on the second insulating layer 184. The wiring layer 196 may be connected to the emitter cap electrode 192 exposed by the second insulating layer 184.

As described above, a heterojunction bipolar transistor according to embodiments of the present invention may be formed.

The heterojunction bipolar transistor according to the embodiments of the present invention includes a substrate 100, a sub-collector layer 110, a collector layer 122, a base layer 132, and an emitter layer sequentially stacked on the substrate 100. 142) and an emitter cap layer 152 may be included.

Referring to FIG. 10, a substrate 100 may be provided. The substrate 100 may be a semi-insulating compound semiconductor substrate.

The sub-collector layer 110, the collector layer 122, the base layer 132, the emitter layer 142, and the emitter cap layer 152 are composed of layers constituting a heterojunction bipolar transistor (HBT). I can. For example, when the substrate 100 is gallium arsenide (GaAs), the sub-collector layer 110 includes an n+ conductivity type gallium arsenide (GaAs) layer, and the collector layer 122 is an n conductivity type gallium arsenide ( GaAs) layer, the base layer 132 includes a p+ conductivity type gallium arsenide (GaAs) layer, the emitter layer 142 includes an n conductivity type aluminum gallium arsenide (AlGaAs), and the emitter cap layer Reference numeral 152 may include n+ conductivity type indium gallium arsenide (InGaAs).

The collector layer 122 and the base layer 132 may have a width smaller than that of the sub-collector layer 110 and may expose a portion of the upper surface of the sub-collector layer 110. The emitter layer 142 and the emitter cap layer 152 may have a width smaller than that of the collector layer 122 and the base layer 132, and may expose a portion of the upper surface of the base layer 132. The width of the upper surface of the emitter layer 142 may be greater than the width of the lower surface of the emitter cap layer 152. That is, the width of the emitter layer 142 or the width of the emitter cap layer 152 may have a shape that decreases toward the substrate 100.

The emitter electrode 160 may be provided on the upper surface of the emitter cap layer 152. The width of the emitter electrode 160 may be equal to or greater than the width of the upper surface of the emitter cap layer 152. The width of the emitter cap layer 152 may be less than or equal to the width of the emitter electrode 160, and the width of the emitter layer 142 may be less than the width of the emitter electrode 160. The emitter electrode 160 may include titanium (Ti), platinum (Pt), or gold (Au), or may include a multilayer film formed using at least one of them. The emitter layer 142, the emitter cap layer 152, and the emitter electrode 160 may constitute an emitter structure ES.

The first electrode 172 may be disposed on the emitter cap layer 152. The first electrode 172 is gold (Au), silver (Ag), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), or zinc (Ohmic contact) with the compound semiconductor. Zn) may include a metal such as.

The second electrode 174 may be disposed on the base layer 132. The second electrode 174 may be disposed to be spaced apart from the emitter structure ES. The second electrode 174 may directly contact the upper surface of the base layer 132. The second electrode 174 is formed of gold (Au), silver (Ag), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), or zinc (Ohmic contact) with the compound semiconductor. Zn) may include a metal such as. The second electrode 174 may be a base electrode connected to the preliminary base layer 130.

A first insulating layer 182 may be disposed on the base layer 132. The first insulating layer 182 may cover the first electrode 172, the second electrode 174, and the emitter structure ES. The first insulating layer 182 may extend between the emitter structure ES and the second electrode 174. The first insulating layer 180 may include at least one of a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer.

The emitter cap electrode 192 may be disposed on the first insulating layer 182. The emitter cap electrode 192 may pass through the first insulating layer 182 and be connected to the first electrode 172. The emitter cap electrode 192 may extend from the first electrode 172 to the second electrode 174. In this case, the emitter cap electrode 192 may be insulated from the second electrode 174 and the emitter structure ES by the first insulating layer 182.

A collector electrode 194 may be disposed on the sub-collector layer 110. The collector electrode 194 may be disposed to be spaced apart from the collector layer 122 and the base layer 132. The collector electrode 194 may directly contact the upper surface of the sub-collector layer 110. The collector electrode 194 is formed of gold (Au), silver (Ag), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), or zinc (Zn) in ohmic contact with the compound semiconductor. ) May include a metal such as.

A second insulating layer 184 may be disposed on the sub-collector layer 110. The second insulating layer 184 may cover the emitter cap electrode 192, the base layer 132, the collector layer 122, and the collector electrode 194 on the upper surface of the sub-collector layer 110. The second insulating layer 184 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

A wiring layer 196 may be disposed on the second insulating layer 184. The wiring layer 196 may pass through the second insulating layer 184 and be connected to the emitter cap electrode 192.

11 is an SEM photograph of a heterojunction bipolar transistor manufactured according to embodiments of the present invention.

11, it can be seen that the widths of the emitter layer 142 and the emitter cap layer 152 are formed to be smaller than the width of the emitter electrode 160. That is, according to embodiments of the present invention, the emitter layer 142 and the emitter cap layer 152 formed by using the emitter electrode 160 as an etching mask are self-aligned without a separate patterning process. It can be confirmed that it was done.

In addition, the first electrode 172 and the second electrode 174 are formed together by using the deposition of a metal layer. At this time, it can be seen that the second electrode 174 is not formed under the emitter electrode 160, but is formed to be spaced apart from the emitter layer 142 and the emitter cap layer 152. That is, the base electrode spaced apart from the emitter layer 142, that is, the second electrode 174 may be formed without a separate patterning process or an insulating pattern forming process.

As described above, embodiments of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features. You can understand that there is. Therefore, it should be understood that the embodiments described above are illustrative and non-limiting in all respects.

100: substrate 110: sub-collector layer
122: collector layer 132: base layer
142: emitter layer 152: emitter cap layer
160: emitter electrode 172: first electrode
174: second electrode 182: first insulating layer
184: second insulating layer 192: emitter cap electrode
194: collector electrode 196: wiring layer

Claims (1)

A sub-collector layer, a collector layer, and a base layer sequentially stacked on the substrate;
An emitter structure disposed on the base layer, the emitter structure having an emitter layer, an emitter cap layer, and an emitter electrode sequentially stacked;
A first electrode disposed on an upper surface of the emitter electrode;
A second electrode disposed on the base layer to be spaced apart from the emitter structure;
An insulating film covering the first electrode, the second electrode, and the emitter structure on the base layer; And
An emitter cap electrode that penetrates the insulating layer on the first electrode and is connected to the first electrode and extends from an upper surface of the first electrode to the second electrode,
The emitter layer has a reverse mesa shape, but has a width smaller than the width of the emitter electrode,
On the second electrode, the insulating layer is a heterojunction bipolar transistor interposed between the second electrode and the emitter cap electrode.

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