JP2005159112A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a substrate leakage current by suppressing the inflow of electric charge from a sub-collector layer of a hetero-junction bipolar transistor to a half-insulating substrate. <P>SOLUTION: A carrier block layer 2 is in contact with a half-insulating semiconductor substrate 1, and the sub-collector layer 3 is formed between the carrier block layer 2 and a collector layer 4. The carrier block layer 2 is a wide gap semiconductor to the sub collector layer, and the sub-collector layer 3 has sufficiently high density and a sufficient thickness so as to reduce collector resistance. Since the carrier block layer 2 uses the wide gap semiconductor to the sub-collector layer 3, it forms a barrier to electrons. Also, since the sub-collector layer 3 is in sufficiently high density, a roughly zero electric field is attained near a boundary with the carrier block layer 2. Of the electrons existing in the sub-collector layer 3, only the electrons having high energy exceeding the energy barrier of the carrier block layer can pass through. By the effect of the carrier blocking layer, since the inflow of the electrons from the sub collector layer 3 to the substrate 1 is suppressed, a leakage current is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using a III-V group compound semiconductor such as GaAs, InP, or InGaAs, and a method for manufacturing the same.

  Since III-V compound semiconductors such as GaAs have a high band gap, they are semi-insulating substrates with high substrate resistivity. In addition, an active element having excellent high frequency characteristics can be formed due to advantages such as high mobility and high Vsat. A heterojunction bipolar transistor (HBT) using a semiconductor material having a larger band gap than the base on the III-V compound semiconductor substrate can maintain a high emitter injection efficiency even when the concentration of the base is increased. It has an advantage and can operate at higher speed than a homojunction bipolar transistor.

  FIG. 4 is a cross-sectional view of a heterojunction bipolar transistor fabricated by the prior art. A subcollector layer 3, a collector layer 4, a base layer 5, an emitter layer 6, an emitter cap layer 7 and an emitter contact layer 8 are formed on a semi-insulating GaAs substrate 1, and an emitter electrode is formed on the emitter contact layer 8. WSi is formed as 13. Ti / Pt / Au is formed as a base electrode 12 on the base layer 5. AuGe / Ni / Au is formed on the subcollector layer 3 as the collector electrode 11.

  The elements of the heterojunction bipolar transistor are electrically isolated from each other by mesa isolation (see, for example, Patent Document 1). As an example of the prior art, there is a mesa type element isolation method by wet etching using a phosphoric acid-based etchant, but since it is a very general technique, a description of a specific method is omitted.

  The resistivity of GaAs not doped with impurities is a semi-insulating substrate having a resistivity of 10 MΩ to 100 MΩ at room temperature. Therefore, mesa-isolated heterojunction bipolar transistors have been considered to be electrically independent of each other.

  However, actually, even in a substrate that is said to be semi-insulating, a leakage current is generated through the level between transistors such as the presence of crystal defects and impurities, and the interface level of the etched surface.

FIG. 5 shows the transition of the inter-element leakage of the lot / slice in the HBT manufactured using the conventional technique. The inter-element leakage current value fluctuates due to various factors such as epitaxial growth conditions or processing process variations. When the substrate leakage current is increased, device characteristics and circuit characteristics are degraded due to a decrease in isolation and an increase in parasitic capacitance.
JP-A-3-283624

  As described above, in the heterojunction bipolar transistor manufactured using the conventional technique, when the inter-element leakage current increases, the electrical isolation between the elements decreases. As a result, the substrate capacity increases and the high frequency characteristics also deteriorate.

  Thus, the reduction in substrate resistivity in the semi-insulating substrate deteriorates element characteristics and circuit characteristics, so how to reduce substrate leakage is an important issue.

  The present invention eliminates the above-described conventional problems, and suppresses the inflow of charges from the subcollector layer of the heterojunction bipolar transistor to the semi-insulating substrate, thereby reducing the substrate leakage current, and It aims at providing the manufacturing method.

In order to achieve the above object, the present invention provides the following four configurations that suppress the inflow of carriers from a heterojunction bipolar transistor formed on a semi-insulating substrate to the substrate.
1) A structure in which a wide gap semiconductor for the subcollector layer exists between the semi-insulating substrate and the subcollector layer of the heterojunction bipolar transistor.
2) A structure in which a superlattice layer including a wide gap semiconductor with respect to the subcollector layer exists between the semi-insulating substrate and the heterojunction bipolar transistor.
3) In a configuration in which an npn bipolar transistor is formed on a semi-insulating substrate, a p-type doped spacer layer exists between the substrate and an n-type doped subcollector layer. Configuration to do.
4) A configuration in which a heterojunction bipolar transistor is formed in a mesa shape on a semi-insulating substrate, wherein the substrate around the heterojunction bipolar transistor is oxidized.

  By adopting a structure in which a layer serving as an electric barrier against electric charges exists between the semi-insulating substrate and the heterojunction bipolar transistor by the above-described configurations 1) to 4), the heterojunction bipolar transistor to the substrate is adopted. The purpose of this is to suppress the injection.

  According to the present invention, it is possible to reduce inter-element leakage through a substrate between heterojunction bipolar transistors formed on a semi-insulating semiconductor substrate by performing the proposed methods alone or in combination. This contributes to higher circuit integration and higher performance.

  Embodiments of the present invention will be described below.

  As one embodiment of the present invention, in a structure in which a heterojunction bipolar transistor is formed on a semi-insulating substrate, a semiconductor having a large band gap with respect to a subcollector layer of the heterojunction bipolar transistor between the substrate and the heterojunction bipolar transistor A layer structure comprising layers is provided.

  In another embodiment of the present invention, in a structure in which a heterojunction bipolar transistor is formed on a semi-insulating substrate, an opposite conductivity to a subcollector layer of the heterojunction bipolar transistor is provided between the substrate and the heterojunction bipolar transistor. A layer structure comprising a semiconductor layer of the type is provided.

  In still another embodiment of the present invention, a structure in which a heterojunction bipolar transistor is formed on a semi-insulating substrate, wherein the substrate and the heterojunction bipolar transistor are surrounded by an oxide layer of the substrate. Provided.

  In yet another embodiment of the present invention, a heterojunction bipolar transistor is formed on a semi-insulating substrate, and the substrate and the heterojunction bipolar transistor are surrounded by an oxide layer of the substrate. A manufacturing method is provided.

  A feature of the present invention is that a substrate leakage current can be reduced in a bipolar transistor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the member corresponding to the member already demonstrated in the following description.

  A first embodiment of the semiconductor device according to the present invention, which solves the problem of large substrate leakage current in an attempt to form a heterojunction bipolar transistor on a semiconductor substrate by employing a novel carrier block layer, will be described with reference to FIG. To do.

  FIG. 1 is a cross-sectional view showing a schematic structure for explaining a heterojunction bipolar transistor which is Embodiment 1 of a semiconductor device of the present invention. In this embodiment, a semi-insulating semiconductor 1 and a subcollector layer 3 are shown. A transistor having a carrier block layer 2 therebetween is included.

Embodiment 1 shown in FIG. 1 shows an example of an InGaP / GaAs heterojunction bipolar transistor, where the carrier block layer 2 is in contact with the semi-insulating substrate 1 and the subcollector layer 3 is formed of the carrier block layer 2 and the collector layer. 4 is formed. The carrier block layer 2 is a wide gap semiconductor with respect to the subcollector layer, such as AlGaAs, and is uniformly doped with, for example, a thickness of 500 A and a doping amount of 1 × 10 ¹⁷ cm ⁻³ , for example. The subcollector layer 3 has a thickness of, for example, 6000 mm, and has a sufficiently high concentration and a sufficient thickness to reduce the collector resistance to 5 × 10 ¹⁸ cm ⁻³ .

  Since the carrier block layer 2 uses a wide gap semiconductor for the subcollector layer 3, it forms a barrier against electrons. Further, since the subcollector layer 3 has a sufficiently high concentration, the electric field is almost zero in the vicinity of the interface with the carrier block layer 2. FIG. 6A shows a band structure diagram of the heterojunction bipolar transistor formed by the above method.

  Of the electrons existing in the subcollector layer 3, only electrons having high energy exceeding the energy barrier of the carrier block layer can pass through. Due to the effect of the carrier blocking layer, inflow of electrons from the subcollector layer 3 to the GaAs substrate 1 is suppressed, and as a result, leakage current is reduced.

  FIG. 7 is a diagram comparing the substrate leakage current of the heterojunction bipolar transistor having the structure according to the first embodiment and the substrate leakage current of a heterojunction bipolar transistor manufactured by a conventional technique. It can be seen that can be reduced by about an order of magnitude.

  Here, an example of an InGaP / GaAs heterojunction bipolar transistor is shown as an example, but the present invention can also be applied to the manufacture of a heterojunction bipolar transistor using other material systems such as AlGaAs, InP, Any bipolar transistor structure can be implemented.

  In the present embodiment, an AlGaAs layer is used as the carrier block layer 2. However, the carrier diffusion prevention layer is not limited to this, and is not limited as long as it is a wide gap semiconductor for a subcollector layer such as InGaP.

  The same effect can be expected by inserting an AlGaAs / GaAs superlattice layer containing AlGaAs, which is a wide gap semiconductor, for example, as the carrier block layer in the first embodiment.

  FIG. 6B shows a band structure diagram of the heterojunction bipolar transistor according to the present embodiment using an AlGaAs / GaAs superlattice layer as a carrier block layer. By inserting an AlGaAs / GaAs superlattice layer under the subcollector layer 3, a carrier blocking effect is generated, so that the leakage current between elements can be reduced.

  In the present embodiment, the same effect can be expected by using a p-type GaAs low concentration layer as the carrier block layer 2. FIG. 6C is a band structure diagram when a p-type GaAs layer is inserted under the n + -type subcollector. Similar to the insertion of a wide gap semiconductor, it has the effect of forming a conduction band barrier, thus preventing the outflow of electrons.

  FIGS. 2A to 2E are cross-sectional views illustrating a sequence of steps for explaining an embodiment of the manufacturing method for manufacturing the heterojunction bipolar transistor of FIG. 1. In this embodiment, the heterojunction bipolar transistor will be described. However, the present invention can be implemented with any bipolar transistor structure.

In FIG. 2A, the substrate is a semi-insulating semiconductor substrate 1 made of GaAs having a (100) orientation. For example, an AlGaAs carrier block layer 2 is formed on the substrate 1 by a suitable process such as MBE or MOCVD. It is grown to a thickness of 1 μm and doped with Si at a concentration (5 × 10 ¹⁶ cm ⁻³ ). The subcollector layer 3 is epitaxially grown on the carrier block layer 2 to a thickness of 0.6 μm so that the concentration is sufficiently high, for example, 5 × 10 ¹⁸ cm ⁻³ . Next, the collector layer 4 is grown on the subcollector layer 3 to a thickness of 0.6 μm, and the concentration of the collector layer 4 is Si-doped or undoped to a low concentration (1 × 10 ¹⁶ cm ⁻³ ). For example, a GaAs base epitaxial layer 5 is epitaxially grown on the collector layer 4 to a thickness of 0.1 μm. For example, C (carbon) is doped to about 4 × 10 ¹⁹ cm ⁻³ or more.

Next, InGaP is formed as an emitter layer 6 on the base layer 5 by epitaxial growth to a thickness of 0.05 μm by n-type doping. Thereafter, 0.1 μm, 5 × 10 ¹⁸ cm ⁻³ GaAs as the emitter cap layer 7 and 1 × 10 ¹⁷ cm ⁻³ InGaAs as the emitter contact layer 8 are formed on the emitter layer 6 by epitaxial growth.

  In FIG. 2B, WSi13 is formed on the entire surface of the epitaxially grown layer structure, and a resist is spin-coated thereon to define an emitter boundary. Next, the emitter electrode 13 is formed by removing the WSi 13 not protected by the photoresist by reactive ion etching (RIE). Thereafter, the emitter contact layer 8 and the emitter cap layer 7 that are not protected by the WSi 13 are removed by etching with phosphoric acid: perwater: water = 4: 1: 45, and the emitter layer 6 is exposed. Etching selectively stops on the emitter InGaP. Next, the photoresist is peeled off.

  Next, in FIG. 2 (c), a photoresist is coated and patterned to delimit the base region. Thereafter, the portions of the emitter layer 6 and the base layer 5 that are not protected by the resist are removed by ion milling using Ar. Next, the photoresist is peeled off.

  Next, in FIG. 2 (d), a photoresist is coated and patterned to define the boundary for collector electrode formation. Next, the portion of the collector layer 4 that is not protected by the photoresist is removed with phosphoric acid: perwater: water = 4: 1: 45, and the subcollector layer 3 is exposed. In order to form the collector electrode 11, AuGe / Ni / Au metal is vapor-deposited on the entire surface to a thickness of 900/200/3600 mm. The photoresist is then stripped and all excess metal is released along with it.

  Further, a photoresist is coated and patterned to delimit the formation of the base electrode 12. Next, the portion of the emitter layer 6 not protected by the photoresist is removed with hydrochloric acid: phosphoric acid: water = 3: 2: 2 to form the base electrode 12, and Ti / Pt / Au = 500/500 / 1000５００ Vapor deposition to thickness. The photoresist is then stripped and all excess metal is released along with it.

  In FIG. 2E, a resist is spin-coated and patterned to define element isolation boundaries. Next, the non-protected portions of the collector layer 4, the subcollector layer 3, and the carrier block layer 2 are removed with phosphoric acid: perwater: water = 4: 1: 5, thereby completing the heterojunction bipolar transistor device.

  Through the above steps, a heterojunction bipolar transistor device having a structure as shown in FIG. 1 can be manufactured. In this embodiment, the electrodes are formed in the order of emitter, collector, and base, but the order of formation is not limited to this. Moreover, although the limited material was used in this embodiment, it is not limited to this.

  As a second embodiment of the present invention, a semiconductor device in which a subcollector layer between elements is oxidized in a structure in which a plurality of different heterojunction bipolar transistors exist on a semiconductor substrate, and a method for manufacturing the same will be described. .

  In Embodiment 2, the leak current through the interface state of the etching surface generated by the conventional mesa isolation method is reduced by oxidizing and insulating the subcollector layer between the elements without performing mesa isolation between elements. The purpose is to do. An example of an InGaP / GaAs heterojunction bipolar transistor is also shown here as an example. However, the present invention can be applied to the manufacture of a heterojunction bipolar transistor using other material systems such as AlGaAs, InP, and any bipolar transistor structure. Can be implemented.

3 (a) to 3 (e) are cross-sectional views illustrating the sequence of steps for explaining an embodiment of a manufacturing method for manufacturing a heterojunction bipolar transistor according to Embodiment 2 of the present invention. The substrate is a semi-insulating semiconductor substrate 1 such as (100) oriented GaAs. On the semi-insulating substrate 1, the subcollector layer 3 is epitaxially grown to a thickness of, for example, 0.6 μm, and the concentration is set to a sufficiently high concentration, for example, 5 × 10 ¹⁸ cm ⁻³ . Next, a collector layer 4 is grown on the subcollector layer 3 to a thickness of 0.6 μm, and the concentration of the collector layer 4 is Si-doped or undoped at a low concentration of 1 × 10 ¹⁶ m ⁻³ .

For example, a GaAs base epitaxial layer 5 is epitaxially grown on the collector layer 4 to a thickness of 0.1 μm, and, for example, C is doped to about 4 × 10 ¹⁹ cm ⁻³ or more. Next, InGaP is formed as an emitter layer 6 on the base layer 5 by epitaxial growth to a thickness of 0.05 μm by n-type doping. Further, 0.1 μm and 5 × 10 ¹⁸ cm ⁻³ of GaAs are formed as the emitter cap layer 7 on the emitter layer 6, and InGaAs is formed as the emitter contact layer 8 by 1 × 10 ¹⁷ cm ⁻³ epitaxial growth.

  In FIG. 3B, WSi13 is formed on the entire surface of the epitaxially grown layer structure, and a resist is spin coated thereon to define the boundary of the emitter. Next, an emitter electrode is formed by removing WSi 13 not protected by the photoresist by reactive ion etching (RIE). Next, the emitter contact layer 8 and the emitter cap layer 7 that are not protected by the WSi 13 are removed by etching with phosphoric acid: perwater: water = 4: 1: 45, and the emitter layer 6 is exposed. Etching is selectively stopped on the emitter layer (InGaP) 6. Next, the photoresist is peeled off.

  Next, in FIG. 3C, a photoresist is coated and patterned to define the base region boundaries. Next, the emitter layer 6 and the base layer 5 which are not protected by the resist are removed by ion milling using Ar. Next, the photoresist is peeled off.

  Next, in FIG. 3D, a photoresist is coated and patterned to define the boundary for forming the collector electrode 11. Next, the portion of the collector layer 4 that is not protected by the photoresist is removed with phosphoric acid: perwater: water = 4: 1: 45, and the subcollector layer 3 is exposed. In order to form the collector electrode 11, AuGe / Ni / Au metal is vapor-deposited on the entire surface to a thickness of 900/200/3600 mm. The photoresist is then stripped and all excess metal is released along with it.

  Photoresist is then coated and patterned to demarcate the formation of the base electrode 12. Next, the portion of the emitter layer 6 not protected by the photoresist is removed with hydrochloric acid: phosphoric acid: water = 3: 2: 2 to form the base electrode 12, and Ti / Pt / Au = 500/500 / 1000５００ Vapor deposition to thickness. The photoresist is then stripped and all excess metal is released along with it.

  In FIG. 3 (e), a resist is spin-coated and patterned to define element isolation boundaries. The element isolation region that is not protected by the resist is left in an oxidizing agent atmosphere. In this embodiment, for example, an oxidizing agent obtained by adding ammonia as a pH adjusting agent to 70% concentrated nitric acid and stabilizing at 60 ° C. with a constant temperature bath was used. This method has no orientation in oxidation, is fast and stable, and can oxidize GaAs with good reproducibility.

  Since the oxidized GaAs layer becomes an insulating layer, element isolation is possible without exposing the surface of the subcollector layer 3, so that leakage current through the interface state of the exposed subcollector layer 3 can be eliminated. it can.

  In this embodiment, the separation process by oxidation between elements is performed while leaving the subcollector layer 3. However, the present invention is not limited to this, and the separation process by oxidation may be performed after removing the subcollector layer 3. Is possible. In this case, the surface of the subcollector layer 3 is exposed but does not contribute to conduction because it is completely oxidized.

  Through the above steps, the heterojunction bipolar transistor device having the structure of the second embodiment as shown in FIG. 3E can be manufactured.

  In this embodiment, the electrodes are formed in the order of emitter, collector, and base, but the order of formation is not limited to this. Moreover, although the limited material was used in this embodiment, it is not limited to this.

  The present invention is applied to a semiconductor device using a III-V group compound semiconductor such as GaAs, InP, or InGaAs, and a method for manufacturing the same, and more particularly, a HEMT (High Electronct Mobility Transistor) or HBT. Application to high integration of high frequency semiconductor devices is expected.

Sectional drawing which shows the typical structure for demonstrating the heterojunction bipolar transistor which is Embodiment 1 of the semiconductor device of this invention (A)-(e) is sectional drawing which shows the process order for demonstrating embodiment of the manufacturing method which manufactures the heterojunction bipolar transistor of Embodiment 1. FIG. (A)-(e) is sectional drawing which shows the process order for demonstrating embodiment of the manufacturing method which manufactures the heterojunction bipolar transistor which is Embodiment 2 of this invention. Sectional drawing which shows the typical structure for demonstrating the conventional heterojunction bipolar transistor It is the figure (lot transition) showing the substrate leakage current in time series. (A) when a wide gap semiconductor for the subcollector is inserted as a carrier block layer, (b) when a superlattice layer including a wide gap semiconductor for the subcollector is inserted as a carrier block layer, (c) is a carrier block layer Band diagram of a heterojunction bipolar transistor fabricated according to an embodiment of the present invention when a semiconductor of opposite conductivity type to the subcollector is inserted as Explanatory drawing of reduction of substrate leakage current according to the present invention

Explanation of symbols

1 Semi-insulating GaAs substrate 2 Carrier block layer 3 Subcollector layer n + -GaAs
4 Collector layer n-GaAs
5 Base layer p-GaAs
6 Emitter layer n-InGaP
7 Emitter cap layer n-GaAs
8 Emitter contact layer n-InGaAs
11 Collector electrode 12 Base electrode 13 Emitter electrode

Claims (8)

A semiconductor device having a structure in which an npn heterojunction bipolar transistor is formed on a semi-insulating semiconductor substrate,
A semiconductor device, wherein a carrier block layer is present between the semiconductor substrate and a subcollector layer which is an electron collecting layer of the heterojunction bipolar transistor.   2. The semiconductor device according to claim 1, wherein a wide gap semiconductor for a subcollector layer of the heterojunction bipolar transistor is used as the carrier block layer.   2. The semiconductor device according to claim 1, wherein a superlattice layer including a wide gap semiconductor with respect to a subcollector layer of the heterojunction bipolar transistor is used as the carrier block layer. The semiconductor device according to claim 1, wherein a semiconductor layer having a conductivity type opposite to that of the subcollector layer and having a concentration of 5 × 10 ¹⁶ cm ⁻³ or less is used as the carrier block layer. A semiconductor device having a structure in which a heterojunction bipolar transistor is formed in a mesa shape on a semi-insulating semiconductor substrate,
A semiconductor device, wherein the heterojunction bipolar transistor is surrounded by an oxide layer of the semiconductor substrate.   The semiconductor substrate is a III-V compound semiconductor such as GaAs or InP or InGaAs, and the heterojunction bipolar transistor includes a III-V compound semiconductor material such as GaAs or InP or InGaAs, and further has a wide range for active devices. 6. The semiconductor device according to claim 1, wherein AlGaAs or InGaP is used as the gap semiconductor. In a method of manufacturing a semiconductor device having a heterojunction bipolar transistor structure in which subcollectors, collectors, bases, and emitter layers are sequentially stacked on a semi-insulating semiconductor substrate,
Etching each of the emitter, base, and collector regions into a mesa shape to form an electrode, and selectively oxidizing only the inert region of the subcollector region with a mixed solution containing nitric acid and ammonia. A method for manufacturing a semiconductor device, comprising: a step. A step of sequentially depositing each layer of an emitter, an emitter cap, and an emitter contact using a sub-collector, a collector, a base, and a semiconductor having a wider gap than the base on a semi-insulating semiconductor substrate by epitaxial growth, and exposing each of the layers by etching In the method of manufacturing a semiconductor device having a heterojunction bipolar transistor structure including a step of forming an electrode,
A method of manufacturing a semiconductor device comprising a step of selectively oxidizing only an inactive collector region directly below a region where a base electrode is formed with nitric acid (70%) at 40 ° C. to 70 ° C.

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