KR100257161B1 - Manufacturing method of heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a heterojunction bipolar transistor is to secure a under-cut portion having a predetermined length in the (011) direction as well as the (011) direction of an N-type InGaAs emitter junction region. CONSTITUTION: An N¬+-type InGaAs sub-collector layer(12), an N¬-type InGaAs collector layer(13), a P¬+-type InGaAs base layer(14), an N¬-type InP emitter layer(15) and an N¬+-type InGaAs emitter junction layer(16) are sequentially grown on an InP semiconductor substrate(11). An emitter metal(17) is formed on the N¬+-type InGaAs emitter junction layer. The N¬+-type InGaAs emitter junction layer is etched using a sulfuric acid containing etchant to expose the N-type InP emitter layer. An exposed N¬-type InP emitter layer is etched using a phosphoric acid containing etchant to expose the P¬+-type InGaAs base layer. The N-type InP emitter layer and the N¬+ type InGaAs emitter junction layer are grown to a thickness range of 1000 angstrom to 1500 angstrom. The emitter metal is formed to a thickness range of 2000 angstrom to 4000 angstrom.

Description

Manufacturing method of heterojunction bipolar transistor

The present invention relates to a method for manufacturing a heterojunction bipolar transistor, and more particularly, a heterojunction bipolar in which an emitter electrode and a base electrode are electrically separated by etching the emitter contact layer under-cut with an sulfuric acid-based etching solution. A method of manufacturing a transistor.

BACKGROUND ART In general, heterojunction bipolar transistors (HBTs) have been spotlighted as high-speed digital circuit devices, ultra-high frequency power devices, and linear devices due to their excellent electrical characteristics such as high speed, high power, high efficiency, and linearity. The characteristic of this HBT device is that the energy band gap discontinuity of the emitter-base junction suppresses the minority carriers injected into the emitter at the base, resulting in high emitter implantation efficiency despite high base impurity concentrations. It is possible to maintain the level, which has the advantage of narrowing the base width and lowering the internal base resistance. In addition, compared with the conventional bipolar transistor, the current gain and the cutoff frequency of the transistor can be improved.

The manufacturing method of the HBT as described above will be described with reference to FIGS. 1, 2a, and 2b.

Referring to FIG. 1, an N ⁺ type InGaAs sub-collector layer 2 and an N type InGaAs collector layer on a semi-insulated InP substrate 1 by a conventional molecular beam epitaxy method or a chemical vapor deposition method using an organometallic compound. (3), the P ⁺ type InGaAs base layer (4), the N type InP emitter layer (5) and the N ⁺ type InGaAs emitter contact layer (6) are grown sequentially, and the N ⁺ type InGaAs emitter The emitter electrode 7 is formed in the center on the contact layer 6 by a lift off method.

Then, although not shown, the emitter metal 7 is used as a mask, and as an etching solution, an etching process using a phosphoric acid-based etching solution composed of H ₃ PO ₄ , H ₂ O ₂ and H ₂ O is used. The N ⁺ type InGaAs emitter contact layer 6 is selectively etched to expose the InP emitter layer 5 of the type, and then the exposed InP emitter layer 5 is wet etched of HCl and H ₃ PO ₄ . The solution is etched to expose the P ⁺ InGaAs base layer 4.

Then, an ordinary HBT manufacturing process is performed to produce HBTs.

In the above, a self-aligning process of depositing a base metal using an emitter metal as a mask is essential for manufacturing a high-performance HBT. To perform the self-aligning process, the emitter metal 7 and then the must so that the base metal is electrically isolated from each other to be formed, to this emitter and the metal (7) as an etch mask when etching the InGaAs emitter contact layer 6 of the lower N ⁺ type, of N ⁺ type It is required to cause an under-cut of about 0.2 占 퐉 to occur in the InGaAs emitter contact layer 6.

Accordingly, in the case of AlGaAs / GaAs HBT devices, GaAs emitter layers are reactively ion-etched (hereinafter referred to as Reactive Ion Etching) to secure under-cuts of about 0.2 μm in the N ⁺ type InGaAs emitter contact layer 6. RIE) process generates a certain under-cut phenomenon, but the InP / InGaAs HBT device has a low etch selectivity due to the low etch selectivity of the N ⁺ type InGaAs emitter contact layer 6 even if a reactive ion etching process is performed. Difficult to secure Therefore, in order to solve this problem, under-cutting is generated in the N + type InGaAs emitter contact layer 6 through a wet etching process using a predetermined phosphate etching solution.

However, as described above, when the N ⁺ type InGaAs emitter contact layer is etched using a phosphate-based etching solution, the crystal direction of the N ⁺ type InGaAs emitter contact layer is shown in FIG. This cross section can secure the desired degree of under-cut by reverse etching, but as shown in FIG. 2B, the under-cut is generated by etching in the forward direction in the crystal direction. It is difficult to secure, and accordingly, there is a problem that the production of HBT is impossible because the emitter metal and the base metal are not electrically separated during subsequent base metal deposition.

결정방향에서도 언더-컷이 발생되도록 과도 식각을 실시할 경우, [011] 결정방향 단면이 지나치게 식각됨으로써 에미터 금속과 베이스 금속이 멀리 떨어지게 되어 베이스 저항이 증가함은 물론 이로 인하여 소자의 성능이 저하되는 문제점이 있었다.In addition, the N ⁺ type InGaAs emitter contact layer 6

When the excessive etching is performed so that the under-cut occurs in the crystal direction, too, the cross section of the crystal direction is excessively etched so that the emitter metal and the base metal are far apart, thereby increasing the base resistance and thereby degrading the performance of the device. There was a problem.

방향으로도 소정 길이의 언더-컷을 확보하여 상기와 같은 문제점을 해결할 수 있는 이종접합 바이폴라 트랜지스터 제조 방법을 제공하는 것을 목적으로 한다.Thus, the N ⁺ type by the present invention, etching the InP emitter layer of the N type to then use an etching solution of sulfuric acid series etching the InGaAs emitter contact layer of N ⁺ type, an etch consisting of HCl and H ₃ PO ₄ solution In addition to the crystallographic direction of the InGaAs emitter contact layer of

An object of the present invention is to provide a heterojunction bipolar transistor manufacturing method capable of solving the above problems by securing an under-cut of a predetermined length in the direction.

1 is a view for explaining a method for manufacturing a heterojunction bipolar transistor according to the prior art.

Figure 2a is a view showing a cross-sectional state in the crystal direction after etching the N ⁺ type InGaAs emitter contact layer.

Figure 2b is a view showing the cross-sectional state in the @ 2 crystal direction after etching the N ⁺ type InGaAs emitter contact layer.

3 to 5 are views for explaining a method for manufacturing a heterojunction bipolar transistor according to the present invention.

결정방향의 단면이다.6 and 7 are SEM photographs showing the state after the N ⁺ type InGaAs emitter contact layer was etched for about 60 seconds using the sulfuric acid-based etching solution according to the present invention, and FIG. Is a cross-section of Figure 7,

Cross section in the crystal direction.

8 is a view showing that an emitter electrode is formed in an [011] direction on an N ⁺ type InGaAs emitter contact layer.

* Explanation of symbols for main parts of the drawings

1: InP substrate 2: InGaAs sub collector layer of N ⁺ type

3: N-type InGaAs collector layer 4: P ⁺ InGaAs base layer

5: N-type InP emitter layer 6: N ⁺ -type InGaAs emitter contact layer

7: emitter metal 8: base metal

Purposes as described above, InP layer-substrate in the N ⁺ type InGaAs subcollector, an N-type InGaAs collector layer, a P ⁺ type InGaAs base layer, an N-type InP emitter layer and the N ⁺ type InGaAs emitter contact layer by the use of the etching solution of the step, a step, a sulfuric acid series such that InP emitter layer is exposed on the N-type to form an emitter metal on the contact InGaAs emitter of said N ⁺ type layer grown in sequence the N ⁺ Etching the InGaAs emitter contact layer of a type, and etching the exposed N-type InP emitter layer using a phosphate-based etching solution to expose the P ⁺ type InGaAs base layer. It is achieved by the heterojunction bipolar transistor manufacturing method according to the present invention.

According to the present invention, an N ⁺ type InGaAs emitter contact layer is etched using a sulfuric acid type etching solution, and then an N type InP emitter layer is etched with an phosphate type etching solution to form an N ⁺ type InGaAs emitter. An under-cut of a predetermined length can be secured regardless of the crystallization direction of the contact layer.

EXAMPLE

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, as shown in FIG. 3, the N ⁺ type InGaAs sub-collector layer 12, the N type InGaAs collector layer 13, and the P ⁺ type InGaAs base are mounted on the InP substrate 11 in a conventional manner. A layer 14, an N-type InP emitter layer 15 and an N ⁺ -type InGaAs emitter contact layer 16 are sequentially grown, and lift off method on the N ⁺ -type InGaAs emitter contact layer 16 The emitter metal 17 is formed. Here, the N-type InP emitter layer 15 and the N ⁺ -type InGaAs emitter contact layer 16 are grown to a thickness of 1,000 to 1,500 Å, respectively, to facilitate subsequent self-alignment processes, as shown in FIG. As shown, the emitter metal 17 is formed on the N ⁺ type InGaAs emitter contact layer 16 in the direction.

Then, as shown in FIGS. 4 and 5, the N ⁺ type InGaAs emitter contact layer 16 is etched using a predetermined etching solution.

결정방향으로는 순방향 식각이 일어나 약 0.1㎛ 정도의 언더-컷이 발생된다.First, the N ⁺ type InGaAs emitter contact layer 16 is etched using the emitter metal 17 as a mask so that the N type InP emitter layer 15 is exposed. In this case, as an etching solution, an sulfuric acid-based etching solution having H ₂ SO ₄ : H ₂ O ₂ : H ₂ O = 1: 8: 160 is used, and the etching time is about 1.3 to 1.5 times the normal etching time of InGaAs thickness. . As a result, as a result of performing an etching process using a sulfuric acid-based solution, the layer of N ⁺ type InGaAs emitter contact layer 16 has an under-cut of about 0.2 μm due to reverse etching in the crystal direction. Generated,

In the crystallization direction, forward etching occurs to produce an undercut of about 0.1 μm.

결정방향의 단면은 순방향 식각이 일어나 약 0.05㎛의 언더-컷을 확보할 수 있다.Subsequently, the N-type InP emitter layer 15 exposed by using a phosphoric acid-based etching solution of HCl: H ₃ PO ₄ = 1: 4 is etched to be 1.1 to 1.3 times larger than the etching time of a normal InP thickness. . As a result, the cross section in the crystallographic direction of the N-type InP emitter layer 15 is vertically etched to maintain an under-cut of about 0.2 μm,

The cross section of the crystal direction has a forward etching to secure an undercut of about 0.05 μm.

Subsequently, the base metal 18 is formed on the top of the emitter metal 17 and the exposed P ⁺ type InGaAs layer by a self-aligning process using photolithography, metal deposition and lift-off methods. At this time, the thickness of the base metal 18 is not only easy to perform a self-aligning process but also 1,500 to 2,000 mm thick in consideration of characteristics of the device.

FIG. 4 is a cross-sectional view of the crystal direction of the device in which the process is completed, and FIG. 5 is a cross-sectional view of the crystal direction.

방향의 단면은 약 0.1㎛ 정도의 언더-컷이 발생된다.6 and 7 are SEM images of the N ⁺ type InGaAs emitter contact layer according to the present invention after etching for about 60 seconds using an sulfuric acid-based etching solution. H ₂ SO ₄ : H ₂ When etching the N ⁺ type InGaAs emitter contact layer using a sulfuric acid etching solution of O ₂ : H ₂ O = 1: 8: 160, as shown in FIG. Undercut of about 0.2 μm occurs, and as shown in FIG.

The cross section in the direction produces an under-cut of about 0.1 mu m.

Therefore, when the InGaAs emitter contact layer 16 of the N ⁺ type to the etching using an etching solution of sulfuric acid sequence according to the present invention, regardless of the crystal orientation N ⁺ type InGaAs emitter contact layer 16 and Under-cuts of a predetermined length can be obtained in the N-type emitter layer, whereby a high performance HBT can be produced.

As described above, the present invention, by etching the N ⁺ type InGaAs emitter contact layer using a sulfuric acid-based etching solution, by etching the N-type InP emitter layer with a phosphoric acid-based etching solution, N A high performance heterojunction bipolar transistor can be manufactured by keeping the under-cut within 0.2 µm regardless of the crystal directions of the InP emitter layer of the type and the InGaAs emitter contact layer of the N ⁺ type. In addition, by using a low acid wet etching solution to minimize the stress to the emitter metal to reduce the fill-up phenomenon of the emitter metal can improve the process yield and device reliability.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (9)

An N ⁺ type InGaAs sub-collector layer, an N type InGaAs collector layer, a P ⁺ type InGaAs base layer, an N type InP emitter layer, and an N ⁺ type InGaAs emitter contact layer are sequentially grown on a semiconductor compound InP substrate. step of the N ⁺ type InGaAs emitter contact layer onto the emitter by using the etching solution of sulfuric acid series such that exposure step, InP emitter layer of the N type to form a metal wherein the N ⁺ type InGaAs emitter of And etching the exposed N-type InP emitter layer using a phosphate-based etching solution to expose the P ⁺ -type InGaAs base layer. Method for manufacturing bipolar transistors. The method of claim 1, wherein the N-type InP emitter layer and the N ⁺ -type InGaAs emitter contact layer are grown to a thickness of 1,000 to 1,500 Å, respectively. The method of claim 1, wherein the emitter metal is formed to have a thickness of 2,000 to 4,000 kV. According to claim 1, wherein the etching solution of the sulfuric acid series for etching the N ⁺ type InGaAs emitter contact layer is characterized in that H ₂ SO ₄ : H ₂ O ₂ : H ₂ O = 1: 8: 160. Method of manufacturing a heterojunction bipolar transistor. 5. The method of claim 1, wherein the etching time of the N ⁺ type InGaAs emitter contact layer is about 1.3 to 1.5 times the InGaAs thickness etching time. 6. The method of claim 1, wherein the phosphate-based etching solution for etching the N-type InP emitter layer is HCl: H ₃ OP ₄ = 1: 4. The method of manufacturing a heterojunction bipolar transistor according to claim 1 or 6, wherein the etching time of the N-type InP emitter layer is about 1.1 to 1.3 times the etching time of the InP thickness. The method of claim 1, further comprising forming a base metal on the emitter metal and the exposed P ⁺ type InGaAs base layer by a self-aligning process. . 9. The method of claim 8, wherein the base metal is formed to a thickness of 1,500 to 2,000 microns.

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