JP2001326229A - Heterojunction bipolar transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an HBT and its manufacturing method that can form stable undercut structure, in addition, can provide wider ledge structure to an emitter region that is formed on an unstable surface, and has excellent mass productivity and reliability. SOLUTION: By utilizing the selection etching characteristics of the GaAs and InGaAs of etching solution where hydrogen peroxide water is mixed with alkaline solution, and at the same time the pH of the mixed liquid is equal to 9.5 or more and 11.5 or less, an InGaAs layer is set to an overhang, and the undercut structure is formed in a shape where a GaAs layer is engraved. To this structure, a mask material is buried in the lower part of the overhang, and a region that is not covered with the mask material is etched by solution for etching the GaAs, thus forming the ledge structure. In addition, the undercut structure is utilized for forming emitter and base electrodes in self-alignment manner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor and a method for manufacturing the same, and more particularly, to a heterojunction bipolar transistor having a ledge structure which can be miniaturized and has high reliability and a method for manufacturing the same.

[0002]

2. Description of the Related Art A heterojunction bipolar transistor (hereinafter referred to as "HBT") is capable of operating with a single power supply, and has features such as low power consumption, high linearity, and high power density. Has been widely used as an element for use. Furthermore, due to the characteristic that HBT can operate at high speed, digital IC for high-speed optical communication
It is also used as an element for In these applications, the element required for the device has high reliability as well as performance.

As a technique for improving reliability in an HBT, there is a technique called a "ledge structure" or a "hetero guard ring structure".

FIG. 13 is a conceptual diagram showing a sectional structure of an HBT having a ledge structure. That is, FIG.
The HBTs shown in (c) are all semi-insulating GaAs.
On a substrate 1, a GaAs collector contact layer 2, Ga
As collector layer 3, GaAs base layer 4, InGaP emitter layer 7, GaAs emitter contact layer 8, InG
It has a structure in which an aAs emitter contact layer 9 is stacked, and an emitter electrode 25 and a base electrode 26 are formed.

[0005] Between the emitter layer 7 and the base layer 4, a ledge layer 28 or a ledge region 30 having an intermediate size between them is provided. These layers are formed between the intrinsic transistor region and the base electrode.
It is provided in order to prevent recombination current from being generated via a surface recombination level at a base junction end face or an external base region. It is known that recombination of electrons and holes supplies a large amount of energy to a semiconductor and contributes to introduction of a new defect serving as a recombination center, resulting in a decrease in reliability. The ledge structure has a shape that prevents the junction interface and the external base region from being exposed on the semiconductor surface. Specifically, the ledge structure has a structure in which a thin depleted semiconductor layer covers the corresponding region.

In particular, the emitter / base junction is a region in which a large amount of electrons, which are minority carriers for the base layer, are injected from the emitter region and recombination between electrons and holes is very likely to occur. Not exposing this portion to the surface is an important point for preventing an increase in recombination current. Reducing the recombination current also leads to improved reliability, in which the ledge structure is advantageous.

As a means for forming a structure for preventing such a recombination current and improving reliability, a structure shown in FIG. 13 has been proposed.

Here, FIG. 13A is called "buried base electrode structure" or the like, in which the base electrode is settled from the depleted semiconductor layer to secure the electrical connection between the base layer and the electrode. is there. FIG. 13B is called “regrowth external base structure” or the like, and shows MBE (Molecular Be
Am epitaxy (molecular beam epitaxy) is used to selectively grow the external base layer again to secure electrical connection and leave the base layer itself buried. FIG. 13C shows a method in which the semiconductor layer 30 is left between the emitter electrode and the base electrode by simply using a patterning technique.

However, in the buried base electrode structure illustrated in FIG. 13A, it is difficult to stably form a base electrode penetrating and settling through a depleted semiconductor layer, and at the same time, it is depleted. However, since the emitter layer and the base electrode are connected by the semiconductor layer, there is a problem that the leak current increases.

In the regrown external base structure illustrated in FIG. 13B, the regrowth process is very sensitive to changes in the surface state and the regrowth conditions before regrowth, so that the regrowth is performed with good reproducibility. It was difficult to form a layer. There is also a problem that it is not suitable for mass production because a special process of regrowth is required.

In contrast to these methods, from the viewpoint of mass production and stability, a method of forming a ledge structure using simple patterning as shown in FIG. 13C is most preferable.

However, in order to form a ledge structure by mask alignment, dimensional margins such as a mask misalignment margin and an etching amount margin are required to some extent. Will appear.

Furthermore, since the distance from the emitter region to the base electrode cannot be reduced to less than these dimensional margins, there is a characteristic limit that the presence of a lead-out resistor for this dimensional margin is inevitable. There's a problem.

In order to address this problem, a method of forming the emitter, ledge structure, and base electrode in a self-aligned manner has been considered. As this method, a method using an undercut structure or a method using a sidewall is used.

FIG. 14A is a conceptual diagram showing a structure obtained by using an undercut structure. That is, when performing the mesa etching for defining the emitter region 7, an undercut structure having an eave (eave) is formed using an etcher mask or the like. Thereafter, the portions under the eaves (both sides of the emitter mesa) are buried with a mask material (not shown) such as a resist, and the semiconductor layer 30 exposed outside thereof is etched to form a ledge structure.

On the other hand, FIG. 14B is a conceptual diagram showing a structure obtained by using a sidewall. That is,
After forming the emitter mesa structure, a mask material such as SiO ₂ is
It is uniformly formed on the entire surface of the wafer by a VD (chemical vapor deposition) method. Then, RIE (Reactive Ion Etching:
Etchback is performed by a reactive ion etching) method to form a sidewall 31. This sidewall 31
Is used as a mask to etch the semiconductor layer 30 exposed to the outside to form a ledge structure.

In each of the structures shown in FIGS. 14A and 14B, the ledge is formed in a self-aligned manner, and there is no need to provide a margin such as a mask alignment margin. For this reason, the distance between the emitter region and the base electrode can be significantly reduced as compared with the case where a ledge structure is formed using mask alignment, which is effective in reducing the base resistance and miniaturizing the transistor size. A way to say.

[0018]

However, in the self-aligned method illustrated in FIG. 14, how to form the undercut structure and the sidewall structure with good reproducibility becomes a problem.

In the undercut structure illustrated in FIG. 14A, a master pattern that defines an emitter region is formed, and the undercut structure is formed by utilizing side etching below the master pattern by using wet etching. Is formed. At this time, the amount of side etching is deeply related to the adhesion between the mask material (not shown) and the semiconductor layer, and it is difficult to control the amount of side etching unless the adhesion is stable. In a compound semiconductor, a typical example of such a mask material is SiO.
_{No. 2} is used, but the adhesion changes easily due to a slight difference in the physical properties of the semiconductor surface, and it is not easy to ensure reproducibility.

Although it has been considered to form the mask with a metal that can be used as an emitter electrode, a material that can satisfy all of the stability with the semiconductor layer, the occurrence of abnormal etching during wet etching, and the like has been found. Was a very difficult situation.

On the other hand, the sidewall structure illustrated in FIG. 14B eliminates the problem of mask failure as in the case of forming the undercut structure, but causes ion damage during etching using the RIE method. There is a problem that joins. Ion damage generates recombination centers and reduces reliability. In addition, strict control of the etching conditions is required for forming the sidewalls in the process, and there is a problem that it cannot be easily applied to mass production.

The present invention has been made based on the recognition of such a problem. That is, the purpose is InGaAs
By setting the s / GaAs selectivity sufficiently high, the controllability of side etching is high, a stable undercut structure can be formed, and a wider ledge is formed for the emitter region formed on the unstable surface. An object of the present invention is to provide an HBT which can provide a structure, is excellent in mass productivity and reliability, and a method for manufacturing the same.

[0023]

In order to achieve the above object, a method of manufacturing a heterojunction bipolar transistor according to the present invention is characterized in that a GaAs layer in a stacked structure of an InGaAs layer and a GaAs layer is prioritized by using an alkaline etching solution. A step of selectively etching.

Alternatively, a method of manufacturing a heterojunction bipolar transistor according to the present invention comprises a collector layer, a base layer provided on the collector layer, a ledge layer selectively provided on the base layer, Manufacturing of a heterojunction bipolar transistor having an emitter layer selectively provided on the ledge layer, a GaAs layer provided on the emitter layer, and an InGaAs layer provided on the GaAs layer Stacking each layer from the collector layer to the InGaAs layer;
etching the nGaAs layer according to a pattern; and removing the n-GaAs layer by using an alkaline etching solution.
forming an undercut structure in which the InGaAs layer protrudes like an eaves on the GaAs layer by etching the GaAs layer below the aGaAs layer preferentially over the InGaAs layer. Features.

A step of burying a mask material under the eaves of the InGaAs layer constituting the undercut structure, and a step of etching a portion not covered with the mask material to expose a base layer, thereby forming the ledge layer. And a step of forming

Further, by depositing an electrode material from above the undercut structure, the emitter electrode laminated on the InGaAs layer and the base electrode laminated on the base layer are self-aligned. The method may further include a forming step.

Here, it is desirable that the alkaline etching solution contains at least hydrogen peroxide and an alkaline solute.

If the pH of the alkaline etching solution is 9.5 or more and 11.5 or less, a sufficient selectivity can be obtained.

On the other hand, a heterojunction bipolar transistor according to the present invention comprises: a collector layer; a base layer provided on the collector layer; a ledge layer selectively provided on the base layer; And an emitter layer selectively provided on the emitter layer and a Ga layer provided on the emitter layer.
An As layer and InGaAs provided on the GaAs layer.
an InGaAs layer on the GaAs layer.
The s layer has an undercut structure protruding like an eave, and a side surface of the GaAs layer has at least a part of a higher-order crystal plane other than the {111} plane.

Crystal planes other than such {111} planes are as follows:
This is a crystal plane having a higher order index, and is unique due to selective etching of the GaAs layer using an alkaline etching solution.

Here, the InGaAs layer may have any one of octagonal, hexagonal, and rhombic planar patterns in which four rectangular corners are cut out. In this way, a sufficient ledge width is secured at the four corners,
Reliability can be improved.

Further, the undercut structure is formed by etching a GaAs layer below the InGaAs layer preferentially over the InGaAs layer using an alkaline etching solution.

The configuration of the present invention described above is realized based on an alkaline etching solution uniquely discovered by the present invention.

That is, the present inventor believes that an etching solution in which at least a hydrogen peroxide solution and an alkaline aqueous solution are mixed and the pH (pH) of the mixed solution is 9.5 or more and 11.5 or less is GaAs and InGaAs. To have a large selectivity. That is, the new etching solution is more GaAs than InGaAs.
Is preferentially etched. By utilizing this selectivity, the undercut structure of the HBT can be realized with sufficient controllability and reproducibility.

FIG. 1 is a cross-sectional view of a main part illustrating an undercut structure of an HBT. That is, on the substrate 1,
Collector contact layer 2, collector layer 3, base layer 4,
An InGaP ledge layer 5 and a GaAs ledge layer 6 are stacked in this order, and further thereon, an InGaP emitter layer 7 and a GaAs emitter contact layer 8 which are etched in a reverse mesa shape are formed, and an eaves-like shape is formed thereon. An overhanging InGaAs emitter contact layer 9 is formed. Then, an emitter electrode 25 and a base electrode 26 are formed.

In order to realize such an undercut structure, a selective etching solution that can side-etch the GaAs layer 8 without etching at least the InGaAs layer 9 is required. The alkaline etching solution of the present invention has such selectivity.

FIG. 2 is a graph showing the relationship between the etching selectivity and the etching rate with respect to the pH of the alkaline etching solution used in the present invention. In other words, the figure shows that the etching rate at room temperature obtained by adjusting the pH of the etching solution by changing the mixing ratio of aqueous ammonia (concentration: 25%) with the concentration of aqueous hydrogen peroxide at 0.3 vol%. Represents data.

In FIG. 2, the solid line represents the etching rate of GaAs, the wavy line represents the etching rate of InGaAs, and the dotted line represents the ratio of the etching rate of GaAs to the etching rate of InGaAs (etching selectivity).
Data relating to InGaAs is shown for the case where the In composition ratio is x = 0.3, x = 0.5 and x = 0.7.

FIG. 2 shows that GaAs (solid line) has a pH of about 1
It can be seen that the etching is performed at a substantially constant rate independent of pH in the range of 0 to about 12. In contrast, I
The etching rate of nGaAs (broken line) shows a dependence with a peak near pH 12, and the etching rate decreases as the In composition ratio x increases.

As a result, the etching selectivity (dotted line) shows a high value when the pH is in the range of about 9.5 to 11.5. In other words, it is understood that GaAs is preferentially etched over InGaAs in this range. I adopted in many devices such as HBT
The In composition ratio of nGaAs is often about x = 0.5. When the In composition ratio x = 0.5, the pH is 10.
In the range of 1 to 10.6, a selectivity of 100 or more is obtained, and it can be seen that GaAs can be sufficiently selectively etched with respect to InGaAs.

However, since the selectivity can be obtained even outside this range, the pH of the etching solution can be appropriately determined inside or outside this range according to the selectivity allowed in the target process. .

The alkaline aqueous solution used in the present invention includes, for example, aqueous solutions of potassium hydroxide (KOH), sodium hydroxide (NaOH) and other various alkalis in addition to aqueous ammonia.

According to the present invention, by selectively etching GaAs under the high selectivity condition shown in FIG. 2, the undercut structure as exemplified in FIG. 1 can be formed reliably and easily. .

In this case, the emitter layer of the HBT is made of GaAs.
It is necessary to have at least a structure in which a layer and an InGaAs layer are stacked. An eaves of the upper InGaAs layer is formed by selectively etching the lower GaAs layer. At this time, it is necessary to prepare a layer (for example, an InGaP layer) which is not etched by the above-mentioned etching solution as a layer further below the GaAs layer so that the etching does not proceed in the depth direction.

When an undercut structure is formed by the method according to the present invention, the etcher mask for the GaAs layer is an InGaAs layer. In this case, GaAs
Affects the side etching amount of GaAs / I
This is a state of an nGaAs interface, and although this interface varies depending on the crystal growth conditions, it is formed by crystal growth, and there is no problem in stability and reproducibility. Therefore, S
There is no change in the side etching amount due to poor adhesion caused when the iO ₂ film is used as a mask, and a highly reproducible side etching amount can be obtained by controlling the etching time.

By using the undercut structure obtained in this way, it is possible to reliably and easily form the ledge structure illustrated in FIG. 14A, and to provide an HBT having a small distance between the emitter region and the base electrode. It can be formed with good reproducibility.

In the GaAs etching using the alkaline etching solution used in the present invention, it can be seen in a phosphoric acid-based etching solution obtained by mixing phosphoric acid, hydrogen peroxide and pure water, which has been widely used as a conventional GaAs etching solution. It does not cause any electrochemical reaction. Due to this feature, there is an advantage that abnormal etching does not occur even in a situation where a metal such as an electrode is exposed. As a result, the restriction on the etching mask in the process is relaxed, and the metal or the electrode itself can be used as a mask.

Based on the above advantages, specific HB
As a method for producing T, the present invention relates to (1) Ti (titanium)
Etching the InGaAs layer with an etchant mixture of pure water, hydrogen peroxide solution, and phosphoric acid using as a mask, (2) only the GaAs layer with an alkaline etchant mixture of pure water, hydrogen peroxide solution, and an alkaline aqueous solution Selectively etching to form an undercut structure in a self-aligned manner; (3) embedding a mask material in the undercut structure and etching the exposed semiconductor layer outside thereof to form a ledge structure in a self-aligned manner And (4) forming an emitter electrode and a base electrode in a self-aligning manner using an undercut structure.
A method for producing T is provided.

Further, in order to obtain a desired HBT structure by the above-described steps, the layer structure needs to have a structure corresponding to the steps as described above. Specifically, semi-insulating Ga
On an As substrate, a high impurity concentration n-type GaAs layer serving as a collector contact layer, a low impurity concentration n-type GaAs layer serving as a collector layer, a p-type GaAs layer serving as a base layer, and an n-type InGaP layer serving as a ledge layer , A stacked structure of GaAs layers, an n-type InGaP layer serving as an emitter layer, an n-type GaAs layer serving as an emitter contact layer, and an n-type I
A structure in which nGaAs layers are sequentially stacked may be used.

Hereinafter, each step will be described in detail based on the above-mentioned laminated structure.

First, in the step (1), the uppermost InGaAs layer is removed using Ti as a mask. At this time, since the phosphoric acid-based etchant does not have the selectivity between InGaAs and GaAs, the lower GaAs layer is also etched, and the etching in the depth direction stops at the InGaP layer thereunder. Further, by using Ti as a mask, electrochemical reaction is positively used to prevent the side etching of the InGaAs and GaAs layers from progressing.

In the step (2), the GaAs layer is etched with an alkaline etching solution while leaving the InGaAs layer. At this time, since the electrochemical reaction does not occur, the etching of the GaAs layer proceeds without any problem even if Ti is used as a mask, and an undercut structure using the InGaAs layer as an eave is formed. Also,
In the depth direction, the etching in the depth direction is stopped in the InGaP layer because the alkaline etching solution cannot etch the InGaP layer as in the case of the phosphoric acid etching solution. Next, the InGaP layer serving as the etching stop layer is removed with hydrochloric acid using the GaAs layer as a mask to expose the ledge layer.

The ledge structure is formed by the step (3). In this example, since the ledge layer has a laminated structure of a GaAs layer and an InGaP layer, it is necessary to sequentially remove each layer in a portion that is not covered with the mask material embedded under the eaves. Thus, a ledge structure can be formed.

Next, the Ti remaining as a mask is removed, and a base electrode and an emitter electrode are formed in a self-aligned manner in the step (4). By forming the electrode by using the vacuum evaporation method, the undercut structure formed in the step (2) causes disconnection of the step, and the base electrode and the emitter electrode are not short-circuited.

After this step, several steps such as a collector electrode forming step are required until the transistor is completed. These steps may be performed by a method similar to the conventional method, and can be easily implemented. . In this way, the emitter electrode and the base electrode can be formed in a self-aligned manner, and an HBT having a ledge structure with good reproducibility can be formed.

Next, the pattern shape when forming the HBT according to the present invention will be described.

FIG. 3 is an enlarged view of an essential part showing an example of an undercut structure formed by the alkaline aqueous solution used in the present invention. That is, FIG.
GaAs emitter contact layer 8 and InGa on it
FIG. 3 is an enlarged view of a corner of a plane pattern of the As emitter contact layer 9, and FIGS.
It is an A line, BB line, and CC sectional drawing.

As described above with respect to the first embodiment, the ledge structure of the HBT of the present invention is formed corresponding to the region where the undercut structure is formed. At the four corners of the rectangular emitter region as in a conventional transistor, electric field concentration occurs, and microscopically, higher-order plane orientations other than the (111) plane appear on the surface. It is stable and easily forms recombination centers. Therefore,
Having a particularly large ledge structure in such a portion plays a significant role in improving reliability. The alkali-based etching solution works very effectively for such a requirement of the element structure.

That is, when GaAs is etched using an alkali-based etching solution, the “normal mesa” (FIG. 2B) is obtained in the same manner as the conventional phosphoric acid-based etching solution.
An end face composed of (111) planes called “inverted mesas” (FIG. 2 (d)) appears on each side of the rectangle. Apart from these (111) planes, FIG. As shown, it has been found that another surface appears as the etching of GaAs proceeds from the four corners of the rectangular pattern. This plane is a crystal plane such as (311) having an orientation index higher than that of the (111) plane. Since this plane is a higher-order plane, it is unstable as a crystal plane, and the side etching proceeds at a higher speed than the side etching speed in the forward mesa direction and the reverse mesa direction. As a result, the side etching of GaAs is deep and the ledge width at these four corners is increased. That is, if this phenomenon is used, a wide ledge region can be automatically provided for an unstable surface or region, and the reliability is improved.

[0060]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail below, with reference to specific examples in which the present invention is applied to a GaAs-based HBT.

(First Embodiment) FIG. 4 to FIG.
It is a process sectional view showing the manufacturing method of HBT by light. Ma
First, as shown in FIG.
Grow a stacked structure. Specifically, for example, MOCVD
(Metal-Orgaic Chemical Vapor Deposition: Organometallic
The thickness of the semi-insulating substrate 1 is reduced to 50
0 nm, 5 × 10 Si¹⁸cm^-3N-type Ga introduced
As layer 2, 500 nm thick, 1 × 10 Si^{1 6}cm
^-3Introduced n-type GaAs layer 3, thickness 60 nm, carbon
4 × 10¹⁹cm ^-3Introduced p-type GaAs layer 4, thickness
Is 25 nm and Si is 3 × 10¹⁷cm^-3N-type introduced
InGaP layer 5, 7 nm thick, non-doping GaAs
s layer 6, thickness 100 nm, Si is 5 × 10¹⁷cm^-3
Introduced n-type InGaP layer 7, 100 nm thick, Si
5 × 10¹⁸cm^-3N-type GaAs layer 8 introduced, thickness
100 nm, Si 3 × 10¹⁹cm^-3N-type introduced
A structure in which the InGaAs layers 9 are stacked is formed.

Next, as shown in FIG. 4B, the uppermost layer 9 is mesa-etched. Specifically, a resist pattern (not shown) having a reverse tapered cross section is formed by an image reverse method, and Ti is formed by a lift-off method.
Is formed on the wafer. next,
An etching solution in which phosphoric acid, hydrogen peroxide solution and pure water are mixed at a ratio of 3: 1: 50 (hereinafter referred to as “phosphoric acid-based etching solution”)
) To etch the uppermost InGaAs layer 9 and the GaAs layer 8 thereunder. At this time, since the phosphoric acid-based etching solution has low selectivity between InGaAs and GaAs, the etching is performed to such an extent that a part of the lower GaAs layer 8 is etched, and the InGaAs layer 9 is completely removed by etching.

Next, as shown in FIG.
The s layer 8 is mesa-etched. The present inventor has found a unique etchant in which the InGaAs layer 9 and the GaAs layer 8 have a sufficient selectivity in this etching step.

Specifically, for example, an etching solution (hereinafter, referred to as an “alkali-based etching solution”) in which 25% aqueous ammonia, hydrogen peroxide, and pure water are mixed at a ratio of 3: 1: 300 is used. Ga, leaving the InGaAs layer 9
Only the As layer 8 is selectively etched. The pH of this etching solution is about 10.3, and GaAs and InGa
As a selection ratio with As, a value of 100 or more is obtained. Due to this selectivity, only the GaAs layer 8 can be etched without substantially etching the InGaAs layer 9.

However, the selectivity of the alkaline etching solution gradually decreases as the pH increases, and the selectivity of the alkaline etching solution decreases as the pH increases.
When the ratio is 2 or more, the selection ratio is lost. Further, since the InGaP layer 7 below the GaAs layer 8 is not etched by the alkaline etching solution, the etching in the depth direction stops at the InGaP layer 7. As a result, only the GaAs layer 8 undergoes side etching to form an undercut structure as shown. The width of the undercut, that is, the amount of side etching, is 0.3 μm, which is the width that functions as the width of the ledge structure.
It is desirable to dig up to about m.

Next, as shown in FIG. 4D, the ledge layer 6 is exposed. Specifically, Ga remaining in an inverted mesa shape
Using the As layer 8 as a mask, the underlying InGaP layer 7 is removed with hydrochloric acid to form an emitter mesa, exposing the ledge layer 6.

Next, as shown in FIG. 5A, the ledge layer is etched. Specifically, a resist pattern 13 embedded in the undercut structure is formed by applying a positive photoresist on the entire surface of the wafer, exposing the entire surface to light, and developing. By using the resist pattern 13 as a mask, etching is sequentially performed with a phosphoric acid-based etching solution and hydrochloric acid to remove an unnecessary ledge layer and form a ledge structure.

Next, as shown in FIG. 5B, the resist 13 and the Ti layer 10 remaining as masks are respectively removed, and a SiO ₂ film 14 is deposited to a thickness of 200 nm on the entire wafer by the CVD method. I do.

Next, as shown in FIG.
The base electrode and the emitter electrode are
A mask pattern 15 to be formed sometimes is formed, and the exposed S
iO ₂NH film₄Remove with F solution. And vacuum
Pt (platinum), Mo (molybdenum), P
t (platinum) and Au (gold) are sequentially laminated, and the emitter electrode 2
5 and the base electrode 26 are formed in a self-aligned manner. On this occasion,
The gap between the electrodes is cut off by an undercut structure.
Ensure that the electrode 26 and the emitter 25 are short-circuited.
Can be prevented.

Thereafter, as shown in FIG. 6A, a resist pattern 16 is formed so as to cover the base electrode 26, and the exposed SiO ₂ film 14 and the base layer 4 are respectively coated with an NH ₄ F solution and a phosphoric acid-based or Etching is removed with an alkaline etching solution. As a result, isolation between elements in the base region is achieved.

Next, after removing the resist pattern 16 and depositing an SiO ₂ film 17 again on the entire surface of the wafer to a thickness of 100 nm, the device region is separated as shown in FIG. A covering resist pattern 18 is formed. Then, using this as a mask, boron (B) is ion-implanted to form the high-resistance region 20. Thus, the resistance of the collector contact layer other than the element region is increased, and the element isolation is completed. After the ion implantation, the resist pattern is removed by ashing (ashing).

Next, a resist pattern (not shown) having an opening in the collector electrode forming region is formed, and the exposed S
The iO ₂ film 17 and the collector layer 3 are respectively removed by an NH ₄ F solution and a phosphoric acid or alkali etching solution,
The collector contact layer 2 is exposed. Then, a laminated structure of AuGe (gold germanium), Ni (nickel), and Au (gold) is formed by a vacuum deposition method, and the collector electrode 2 is formed.
7 is formed. At this time, after the lift-off, a heat treatment at 370 ° C. for 2 minutes in nitrogen, for example, can secure ohmic characteristics with the semiconductor.

Next, the SiO ₂ film 17 is treated with an NH ₄ F solution.
Is removed once, and the thickness 20 is again entirely formed by the thermal CVD method.
A 0 nm SiO ₂ film 20 is deposited. Thereafter, a resist pattern (not shown) is formed, and contact holes are formed in the SiO ₂ film at the emitter, base and collector electrode portions. Then, as the wiring layer 28, Ti (titanium), Pt
A stacked structure of (platinum) and Au (gold) is formed by using a vacuum deposition method and a lift-off method. Thus, an HBT having a ledge structure as shown in FIG. 7 is completed.

(Second Embodiment) FIG. 8 to FIG. 12 are conceptual diagrams illustrating a principal part plane pattern of an HBT according to a second embodiment of the present invention. That is, these drawings show that the GaAs emitter contact layer 8 and the InG
FIG. 2 is a plan view conceptually showing a plane pattern of an aAs emitter contact layer 9, a base electrode 26, and a collector electrode 27.

First, FIG. 8 shows an example of a pattern in which the outer circumference of the emitter region is entirely formed in an oblique direction and the overall undercut width is made large to improve the reliability. That is, as described above with reference to FIG. 2C, the GaAs crystal plane in an oblique direction different from both the forward mesa direction FM and the reverse mesa direction RM can be etched at a high speed by the alkaline etching solution of the present invention. A wider cut width can be formed. As a result, the ledge width is increased, and the reliability of the HBT can be further improved.

On the other hand, FIG. 9 shows that the etched surface in the reverse mesa direction, which is a stable surface, is left to some extent. Represents a pattern example in which is enlarged. That is, in the figure, the reverse mesa surface of GaAs is formed in parallel to the direction of reference numeral RM, and the forward mesa surface is formed in parallel to the direction of reference numeral FM. By providing an etching surface 32 in an oblique direction that is not parallel to any of these, a pattern is formed so that a normal mesa surface of GaAs does not appear. Even in this case, the reliability of the HBT can be improved by securing a wide undercut width.

FIG. 10 shows an example in which oblique surfaces 32 different from the normal mesa direction and the reverse mesa direction are formed at the four corner portions of the emitter electrode, which are particularly problematic, and the ledge width of this portion is increased. It is. If the ledge width at the four corners of the emitter electrode is increased in this way, the reliability of the HBT can be ensured even when the electric field is concentrated.

FIG. 11 shows an example in which the characteristics of an alkaline etching solution are used as they are. That is, according to the alkaline etching solution used in the present invention,
By performing GaAs side etching on the normal rectangular emitter electrode pattern, portions 33 having large ledge widths are formed at the four corners, thereby improving reliability.

On the other hand, FIG. 12 shows that the reliability is improved by increasing the width of the ledges at the four corners and forming the relatively stable forward mesa surface and reverse mesa surface long. That is, in this specific example, projecting patterns 34 are intentionally provided at the four corners of the emitter electrode. Due to the etching characteristics of the alkaline etching solution, the GaAs layer under the protruding pattern 34 undergoes side etching at an early stage and is removed. As a result, as shown in FIG. 12, the ledge widths at the four corners where the ledge width is desired to be maximized can be sufficiently increased.

The embodiment of the invention has been described with reference to the examples. However, the present invention is not limited to these specific examples. For example, the specifics and structure of the HBT, or the material of each part, other than those shown as specific examples, those skilled in the art can use those appropriately changed based on known techniques.

Also, the composition of the alkaline etching solution used in the present invention can obtain the same effect by using those appropriately selected based on known techniques by those skilled in the art other than those described above as specific examples. .

Further, the alkaline etching solution used in the present invention is not limited to HBT, but can be similarly applied to all devices and steps which need to selectively etch GaAs and InGaAs to obtain the same effect. be able to.

[0083]

As described in detail above, according to the present invention,
When forming an HBT having a ledge structure using a self-aligned method using an undercut structure, InGaAs is used.
By setting the s / GaAs selectivity sufficiently high, the controllability of side etching is high, and a stable undercut structure can be formed.

Further, according to the present invention, it is possible to provide a wider ledge structure for the emitter region formed on the unstable surface, and it is possible to manufacture an HBT excellent in mass productivity and reliability. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part showing an undercut structure of an HBT.

FIG. 2 is a graph showing the relationship between the etching selectivity and the etching rate with respect to the pH of an alkaline etching solution used in the present invention.

FIG. 3 is an enlarged view of a main part showing an example of an undercut structure formed by an alkaline aqueous solution used in the present invention.

FIG. 4 is a process sectional view illustrating a method of manufacturing an HBT according to the present invention.

FIG. 5 is a process sectional view illustrating a method of manufacturing an HBT according to the present invention.

FIG. 6 is a process sectional view illustrating a method of manufacturing an HBT according to the present invention.

FIG. 7 is a process sectional view illustrating a method of manufacturing an HBT according to the present invention.

FIG. 8 is a conceptual diagram illustrating a main part plane pattern of an HBT according to a second embodiment of the present invention.

FIG. 9 is a conceptual diagram exemplifying a main part plane pattern of an HBT according to a second embodiment of the present invention.

FIG. 10 is a conceptual diagram illustrating a principal-part plane pattern of an HBT according to a second embodiment of the present invention.

FIG. 11 is a conceptual diagram illustrating a main part plane pattern of an HBT according to a second embodiment of the present invention.

FIG. 12 is a conceptual diagram illustrating a principal-part planar pattern of an HBT according to a second embodiment of the present invention.

13 (a) is a “buried base electrode structure”, FIG. 13 (b) is a “regrown external base structure”, and FIG. 13 (c) is a simple patterning technique using an emitter electrode. It is a conceptual diagram showing the structure which leaves the semiconductor layer 30 between a base electrode, respectively.

FIG. 14 (a) is a conceptual diagram showing a structure obtained by using an undercut structure, and FIG. 14 (b)
FIG. 3 is a conceptual diagram illustrating a structure obtained by using a sidewall.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semi-insulating GaAs substrate 2 GaAs collector contact layer 3 GaAs collector layer 4 GaAs base layer 5 InGaP ledge layer 6 GaAs ledge layer 7 InGaP emitter layer 8 GaAs emitter contact layer 9 InGaAs emitter contact layer 10 Ti mask 13 Embedded resist 14, 17 , 20 SiO2 film 15, 16, 18 Resist mask 18 High resistance region 25 Emitter electrode 26 Base electrode 27 Collector electrode 28 Wiring layer 29 Regrown external base layer 31 Side wall 40 Ledge layer 42 Ledge region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/417 F term (Reference) 4M104 AA05 BB06 BB11 BB14 CC01 DD02 DD09 DD16 DD34 DD68 DD78 DD94 FF22 GG06 5F003 AP04 AZ01 BA11 BA25 BA91 BA92 BA93 BB00 BB02 BB04 BB08 BB90 BC01 BC08 BE02 BE04 BE90 BF06 BH01 BH08 BH18 BH99 BM02 BM03 BP11 BP32 BP94 BP96 BS04 BS08 5F043 AA14 BB07 FF02 GG10

Claims (9)

[Claims] 1. A method for manufacturing a hetero-junction bipolar transistor, comprising a step of preferentially etching a GaAs layer in a laminated structure of an InGaAs layer and a GaAs layer using an alkaline etching solution. 2. A collector layer, a base layer provided on the collector layer, a ledge layer selectively provided on the base layer, and a selectively provided layer on the ledge layer. An emitter layer, and a Ga layer provided on the emitter layer.
An As layer and InGaAs provided on the GaAs layer.
a step of laminating each layer from the collector layer to the InGaAs layer, a step of etching and removing the InGaAs layer according to a pattern, and an alkaline etching solution. Using InGaAs
Forming an undercut structure in which the InGaAs layer protrudes like an eaves on the GaAs layer by etching the GaAs layer below the layer preferentially over the InGaAs layer. Of manufacturing a heterojunction bipolar transistor. 3. The I-shaped structure constituting the undercut structure
a step of embedding a portion under the eaves of the nGaAs layer with a mask material; and a step of forming a ledge structure by exposing a portion not covered by the mask material to expose a base layer. The method for manufacturing a heterojunction bipolar transistor according to claim 2. 4. An emitter material deposited on said InGaAs layer and a base electrode deposited on said base layer are self-aligned by depositing an electrode material from above said undercut structure. 4. The method according to claim 3, further comprising the step of forming. 5. The method of manufacturing a heterojunction bipolar transistor according to claim 1, wherein said alkaline etching solution contains at least hydrogen peroxide and an alkaline solute. 6. The method for manufacturing a heterojunction bipolar transistor according to claim 1, wherein the pH of the alkaline etching solution is 9.5 or more and 11.5 or less. 7. A collector layer, a base layer provided on the collector layer, a ledge layer selectively provided on the base layer, and a selectively provided layer on the ledge layer. An emitter layer, and a Ga layer provided on the emitter layer.
An As layer and InGaAs provided on the GaAs layer.
and an undercut structure in which the InGaAs layer overhangs the GaAs layer in an eaves-like manner. The side surface of the GaAs layer has at least one crystal plane higher than the {111} plane. A heterojunction bipolar transistor, characterized in that the transistor has a heterojunction bipolar transistor. 8. The heterojunction bipolar transistor according to claim 7, wherein said InGaAs layer has a planar pattern of any one of an octagon, a hexagon, and a rhombus in which four rectangular corners are cut out. 9. The method according to claim 1, wherein the undercut structure is formed by using an alkaline etching solution to remove the Ga under the InGaAs layer.
9. The heterojunction bipolar transistor according to claim 7, wherein the heterojunction bipolar transistor is formed by etching the As layer preferentially over the InGaAs layer.