JPS63124465A - Manufacture of bipolar transistor - Google Patents

Manufacture of bipolar transistor

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Publication number
JPS63124465A
JPS63124465A JP27132086A JP27132086A JPS63124465A JP S63124465 A JPS63124465 A JP S63124465A JP 27132086 A JP27132086 A JP 27132086A JP 27132086 A JP27132086 A JP 27132086A JP S63124465 A JPS63124465 A JP S63124465A
Authority
JP
Japan
Prior art keywords
layer
electrode
base electrode
semiconductor layer
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27132086A
Other languages
Japanese (ja)
Other versions
JPH0588541B2 (en
Inventor
Kazuhiko Honjo
和彦 本城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27132086A priority Critical patent/JPS63124465A/en
Publication of JPS63124465A publication Critical patent/JPS63124465A/en
Publication of JPH0588541B2 publication Critical patent/JPH0588541B2/ja
Granted legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain a bipolar transistor having excellent high-speed and high-frequency characteristics and consisting of a compound semiconductor by forming a collector electrode self-aligning with a fine base electrode by shaping an insulating film having superior adhesion onto the base electrode. CONSTITUTION:An N GaAs layer 2, a P-GaAs layer 3 and an N-AlGaAs layer 4 are superposed onto semi-insulating GaAs 1 through an MBE method, H ions are implanted and dielectric isolation 5 is conducted, and ohmic AuGeNi 6a and SiO2 7 are stacked. A photo-resist mask 8 is executed, an emitter electrode 6 is shaped through ion milling, and the N layer 4 is etched in an isotropic manner by HPO4+H2O2+H2O to expose the P layer 3. The mask 8 is removed, a photo-resist 9 is formed, and AuZnNi 10a is superposed on the emitter electrode 6 through self-alignment. The resist 9 is gotten rid of and AuZnNi 10a is coated with SiO2 11, a resist 13 is executed, SiO2 11 and the P layer 3 are taken off through etching to expose the P layer 3, AuGeNi 12a is evaporated, and a collector electrode 12 self-aligning with a base electrode 10 is shaped onto the layer 2. The layer 12a is lifted off, thus completing a bipolar transistor.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はバイポーラトランジスタの製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a bipolar transistor.

〔従来の技術〕[Conventional technology]

バイポーラトランジスタは電界効果トランジスタに比べ
て、電流駆動能力が大きいという優れた特徴を有してい
る。このため、近年、SjのみならずGaAsなとの化
合物半導体を用いたバイポーラトランジスタの研究開発
が盛んに行なわれている。特に、化合物半導体を用いた
バイポーラトランジスタは、分子線エピタキシー(以降
MBEと称す)技術などを用いることによりエミッタ・
ベース接合をヘテロ接合に構成でき、ベースを高濃度と
しても、エミッタ注入効率を大きく保てるなど利点は大
きい。
Bipolar transistors have an excellent feature of higher current driving capability than field effect transistors. Therefore, in recent years, research and development of bipolar transistors using not only Sj but also compound semiconductors such as GaAs have been actively conducted. In particular, bipolar transistors using compound semiconductors are developed by using molecular beam epitaxy (hereinafter referred to as MBE) technology.
It has many advantages, such as the base junction can be configured as a heterojunction, and the emitter injection efficiency can be maintained high even if the base is highly doped.

このような化合物半導体のパイポーラトランジスタをよ
り高周波化するためには、エミッタ電極及びベース電極
を微細化することと同時に、自己整合的に配置すること
は勿論、ベース電極とコレクタ電極との間も自己整合的
に配置する必要がある。
In order to increase the frequency of such compound semiconductor bipolar transistors, it is necessary to miniaturize the emitter and base electrodes, and at the same time arrange them in a self-aligned manner. Must be placed in a self-consistent manner.

第3図(a)・〜(c)は従来のバイポーラトランジス
タの製造方法を説明するための工程順に示した半導体チ
ップの断面図である。
FIGS. 3(a) to 3(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a bipolar transistor.

この従来例は、先ず、第3図<a)に示すように、Ga
As半絶縁性基板1′上にn−GaAsからなる半導体
層2’、P−GaAsからなる半導体層3′及びn −
A e G a A sからなる半導体層4′を順次M
BE法により形成し、更に、所定のパターンのA IJ
 G e N i層からなるエミッタ電極6′及びその
上のS i 02膜7を形成した後これをマスクとして
半導体層3′上にAuZnNi層10a′全10a′的
に形成する。ここでは、AuGeNi層からなるエミッ
タ電極6′の上には、5i02膜7′とA u Z n
 N i層1oa′が残る。
In this conventional example, first, as shown in FIG.
A semiconductor layer 2' made of n-GaAs, a semiconductor layer 3' made of P-GaAs, and an n-
Sequentially M
It is formed by the BE method, and furthermore, A IJ of a predetermined pattern is formed.
After forming an emitter electrode 6' made of a GeNi layer and an Si02 film 7 thereon, an AuZnNi layer 10a' is formed on the entire semiconductor layer 3' using this as a mask. Here, on the emitter electrode 6' made of an AuGeNi layer, a 5i02 film 7' and an A u Z n
1 oa' of the Ni layer remains.

続いて、エミッタ電極6′を覆う所定のパターンのホト
レジスト膜13′を形成し、ベース電極の幅WBが所定
の値になるようにする。
Subsequently, a photoresist film 13' having a predetermined pattern is formed to cover the emitter electrode 6' so that the width WB of the base electrode becomes a predetermined value.

次に、第3図(b)に示すように、ホトレジスト膜13
′をマスクとしてAuZnNi層10a′全10a′グ
してベース電極10’を形成すると共に等方性エツチン
グによって半導体層3′と半導体層2′の表面とを除去
し、更にホトレジスト膜15をマスクとして半導体層2
′の表面にオーミック金属のA u G e N i層
12a′を上方から蒸着する。
Next, as shown in FIG. 3(b), the photoresist film 13
Using the photoresist film 15 as a mask, the entire AuZnNi layer 10a' is etched to form the base electrode 10', and the surfaces of the semiconductor layer 3' and the semiconductor layer 2' are removed by isotropic etching. semiconductor layer 2
An ohmic metal AuGeNi layer 12a' is deposited on the surface of the substrate 12a' from above.

次に、第3図(c)に示すように、有機溶剤中でホトレ
ジスト膜13′を溶がしりストオフを行って、コレクタ
電極12′を形成する。
Next, as shown in FIG. 3(c), the photoresist film 13' is dissolved and removed in an organic solvent to form the collector electrode 12'.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のバイポーラトランジスタの製造方法では
、ベース電極をその上に形成したホトレジストでパター
ニングするが、そのときホトレジス1へとベース電極の
A u Z n N i層との密着性が悪く、通常用い
られるリン酸系あるいは硫酸系エツチング液がしみ込み
A u Z n N i層の部分もエツチングされてし
まうという欠点があった。
In the conventional bipolar transistor manufacturing method described above, the base electrode is patterned using a photoresist formed thereon, but at this time, the adhesion between the photoresist 1 and the A u Z n N i layer of the base electrode is poor, so that it is not normally used. There is a drawback that the phosphoric acid or sulfuric acid-based etching solution used in the etching soaks in and etches the AuZnNi layer as well.

このためこの方法では、ベース電極の幅Waは2μm程
度が下限で、それ以上の微細化は極めて困難であった。
Therefore, in this method, the lower limit of the width Wa of the base electrode is about 2 μm, and it is extremely difficult to make the base electrode smaller than that.

従って、従来方法による構造では、ベース電極の下部の
寄生のベース・コレクタ接合容量が大きく、バイポーラ
トランジスタの高速・高周波特性向上の妨げになってい
た。
Therefore, in the structure according to the conventional method, the parasitic base-collector junction capacitance under the base electrode is large, which hinders the improvement of the high-speed and high-frequency characteristics of the bipolar transistor.

本発明の目的は、ベース電極を微細化しがっコレクタ電
極をベース電極に自己整合的に形成して高速・高周波性
能の極めて優れたバイポーラトランジスタの製造方法を
提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a bipolar transistor having extremely excellent high-speed and high-frequency performance by miniaturizing the base electrode and forming a collector electrode in self-alignment with the base electrode.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のバイポーラトランジスタの製造方法は、半絶縁
性基板上に順次堆積した一導電型の第1及び反対導電型
の第2の半導体層の上に所定のパターンで一導電型のエ
ミッタ層及びエミッタ電極を形成する工程、前記第2の
半導体層上のに選択的に第1の導体層を形成する工程、
前記エミッタ電極及び前記第1の導体層上に絶縁膜及び
所定のパターンのホトレジスト膜を形成する工程、該ホ
トレジスト膜をマスクとして前記絶縁膜及び前記第1の
導体層並びに前記第2の半導体層を異方性並びに等方性
エツチングで順次除去して前記第1の導体層からなるベ
ース電極を形成する工程及び前記ホトレジスト膜及び前
記ベース電極をマスクとして前記第1の導体層上にコレ
クタ電極を形成する工程を含み前記コレクタ電極を前記
ベース電極に自己整合的に形成して成る。
The method for manufacturing a bipolar transistor of the present invention includes forming an emitter layer of one conductivity type and an emitter layer in a predetermined pattern on a first semiconductor layer of one conductivity type and a second semiconductor layer of the opposite conductivity type, which are sequentially deposited on a semi-insulating substrate. a step of forming an electrode; a step of selectively forming a first conductor layer on the second semiconductor layer;
forming an insulating film and a photoresist film with a predetermined pattern on the emitter electrode and the first conductor layer; using the photoresist film as a mask, the insulating film, the first conductor layer, and the second semiconductor layer are formed; Forming a base electrode made of the first conductor layer by sequentially removing it by anisotropic and isotropic etching, and forming a collector electrode on the first conductor layer using the photoresist film and the base electrode as a mask. The collector electrode is formed in self-alignment with the base electrode.

〔作用〕[Effect]

本発明では、ベース電極の上に密着性のよい酸化膜又は
窒化膜等からなる絶縁膜を形成して保護するため、ベー
ス電極の幅WBを0.5μm程度に狭くしても、ホトレ
ジスト膜の下のA u Z nNj層がエツチングされ
ることがなく、微細化したベース電極とそれに自己整合
的なコレクタ電極が形成出来、高速・高周波性能の極め
て優れた化合物のバイポーラトランジスタが実現できる
In the present invention, since an insulating film made of an oxide film or a nitride film with good adhesion is formed on the base electrode to protect it, even if the width WB of the base electrode is narrowed to about 0.5 μm, the photoresist film is The underlying A u Z nNj layer is not etched, a fine base electrode and a collector electrode self-aligned thereto can be formed, and a compound bipolar transistor with extremely excellent high speed and high frequency performance can be realized.

〔実施例〕〔Example〕

以下に本発明の一実施例について図面を参照して説明す
る。
An embodiment of the present invention will be described below with reference to the drawings.

第1図(a)〜(f>は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。この
実施例では、先ず、 第1図(a)に示すようにGaAsの半絶縁性基板1表
面に順次にn−GaAsからなる半導体層2.p−Ga
A、sからなる半導体層3及びn−Δ(! G a A
 sからなる半導体層4をMBE法により形成し、続い
てバイポーラトランジスタを形成する部分を除いて他の
部分に水素イオンH゛をイオン注入し絶縁領域5を形成
する。
1(a) to (f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.In this embodiment, first, as shown in FIG. 1(a), A semiconductor layer 2 made of n-GaAs is sequentially formed on the surface of the GaAs semi-insulating substrate 1.
The semiconductor layer 3 consisting of A, s and n-Δ(! G a A
A semiconductor layer 4 made of S is formed by the MBE method, and then hydrogen ions H are ion-implanted into other parts except for the part where the bipolar transistor is to be formed to form the insulating region 5.

次に、第1−図(b)に示すように、半導体層4のオー
ミック金属のA u G c N i層6aと5j02
膜7とを順次形成する。
Next, as shown in FIG. 1(b), the ohmic metal AuGcNi layers 6a and 5j02 of the semiconductor layer 4 are
The films 7 and 7 are sequentially formed.

次に、第1図(c)に示すように、所定のパターンのホ
トレジスト膜8を形成し、これをマスクとして5i02
膜7及びAuGeN i層6aをAr4によるイオンミ
リング法による異方性エツチングで除去してエミッタ電
極6を形成し、さらにリン酸、過酸化水素及び水の混合
液により、半導体層4を等方性エツチングして半導体層
3表面を露出する。ここでエミッタ電極6は密着性のよ
いS i 02膜7に保護されている。
Next, as shown in FIG. 1(c), a photoresist film 8 of a predetermined pattern is formed, and using this as a mask, 5i02
The film 7 and the AuGeN i layer 6a are removed by anisotropic etching using Ar4 ion milling to form the emitter electrode 6, and the semiconductor layer 4 is isotropically etched using a mixture of phosphoric acid, hydrogen peroxide, and water. The surface of the semiconductor layer 3 is exposed by etching. Here, the emitter electrode 6 is protected by a Si 02 film 7 with good adhesion.

次に、第1図(d)に示ずように、ホトレジス1〜膜8
を除去した後、絶縁領域5の上にホトレジスト膜9を形
成し、更に、上方より半導体層2のオーミック金属のA
uZnNi層10aを層着0aってエミッタ電極6に自
己整合的に形成する。
Next, as shown in FIG. 1(d), the photoresist 1 to film 8
After removing the ohmic metal A of the semiconductor layer 2, a photoresist film 9 is formed on the insulating region 5.
A uZnNi layer 10a is deposited on the emitter electrode 6 in a self-aligned manner.

以上の工程が示すようにエミッタ電極6が2μm以下に
微細化されても、S i 02膜7からなる保護膜があ
るため、エミッタ電極6がオーバーエツチングされるこ
とがなく設計通りに自己整合的にAuZnNi層10a
を層着0aる。
As shown in the above process, even if the emitter electrode 6 is miniaturized to 2 μm or less, since there is a protective film made of the SiO2 film 7, the emitter electrode 6 will not be over-etched and will remain self-aligned as designed. AuZnNi layer 10a
Layer 0a.

次に、第1図(e)に示ずように、有機溶剤による洗浄
を行いホトレジス1〜膜9を溶かした後、CVD法によ
り全面にSi○2膜11全11し、続いて、コレクタ電
極形成用のホトレジスト膜13を形成した後、バッフア
ートフッ酸にてSiO2膜11全11チングし、更に、
リン酸、過酸化水素及び水の混合液により半導体層3を
エツチングして、半導体層2を露出する。続いて、上方
よりn −G a A sからなる半導体層4のオーミ
ック金属のAuGeNi層1.2 a蒸着する。このと
き、半導体層2の表面にはベース電極10に自己整合的
にコレクタ電極12が形成される。
Next, as shown in FIG. 1(e), after cleaning with an organic solvent to dissolve the photoresists 1 to 9, a Si○2 film 11 is deposited on the entire surface by CVD, and then the collector electrode After forming the photoresist film 13 for formation, the entire SiO2 film 11 is etched with buffered hydrofluoric acid, and further,
The semiconductor layer 3 is etched using a mixture of phosphoric acid, hydrogen peroxide, and water to expose the semiconductor layer 2. Subsequently, an ohmic metal AuGeNi layer 1.2a of the semiconductor layer 4 made of n-GaAs is deposited from above. At this time, a collector electrode 12 is formed on the surface of the semiconductor layer 2 in a self-aligned manner with the base electrode 10.

最後に、第1図(f>に示すように、有機溶剤によるリ
フトオフによってAuGeNi層12aを層表2a化合
物半導体のバイポーラ1ヘランジスタができる。
Finally, as shown in FIG. 1(f>), the AuGeNi layer 12a is lifted off using an organic solvent to form a bipolar 1-helangister of the compound semiconductor layer 2a.

従って、ここに示した工程によって、ベース電極10の
幅が2μm以下となってもSjO□膜11からなる保護
膜があるためベース電極10がオーバーエツチングされ
ることがなくコレクタ電極12の自己整合配置が行なえ
る。
Therefore, by the process shown here, even if the width of the base electrode 10 becomes 2 μm or less, the base electrode 10 is not over-etched because of the protective film made of the SjO□ film 11, and the self-aligned arrangement of the collector electrode 12 is maintained. can be done.

第2図は本発明の一実施例を説明するための半導体チッ
プの平面図である。
FIG. 2 is a plan view of a semiconductor chip for explaining one embodiment of the present invention.

この実施例では、上述した製造方法によって、= 9− 第2図に示すように、半絶縁性基板1上の絶縁領域5に
よって囲まれた素子形成領域内に、エミッタ電極6とそ
れに自己整合的に配置したベース電極10とベース電極
10に自己整合的に配置されたコレクタ電極12とを備
えた化合物半導体のバイポーラトランジスタが出来る。
In this embodiment, by the manufacturing method described above, an emitter electrode 6 and a self-aligned emitter electrode 6 are formed in an element formation region surrounded by an insulating region 5 on a semi-insulating substrate 1, as shown in FIG. A bipolar transistor made of a compound semiconductor is produced, which includes a base electrode 10 disposed at the base electrode 10 and a collector electrode 12 disposed in self-alignment with the base electrode 10.

なお本発明の実施例においては、絶縁膜として5i02
膜を用いたが、これに限らすSiNx等の窒化膜を用い
ても効果は同じである。
In the embodiment of the present invention, 5i02 is used as the insulating film.
Although a film is used, the effect is the same even if a nitride film such as SiNx is used.

又、半導体としてはGaAsを用いたものについて述べ
たが、GaAsに限らすJnP等の他の化合物半導体で
もよい。
Furthermore, although GaAs has been described as a semiconductor, other compound semiconductors such as JnP may be used instead of GaAs.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ベース電極上に絶縁膜を
設けてベース電極の幅を0.5〜0.2μInという極
めて微細なパターンに形成し、更にコレクタ電極をベー
ス電極に自己整合的に配置することによって、高速・高
周波性の非常に優れた化合物半導体のバイポーラトラン
ジスタを実現出来るという効果がある。
As explained above, the present invention provides an insulating film on the base electrode, forms the base electrode into an extremely fine pattern with a width of 0.5 to 0.2 μIn, and furthermore, the collector electrode is formed in a self-aligned manner to the base electrode. This arrangement has the effect of realizing a compound semiconductor bipolar transistor with excellent high speed and high frequency performance.

このことにより、遮断周波数が300H以上のバイポー
ラトランジスタの量産化を可能にして価格を低減すると
共に動作周波数20 G H2以上の分周器の集積化が
可能となる。
This makes it possible to mass-produce bipolar transistors with cut-off frequencies of 300H or more, thereby reducing costs, and to integrate frequency dividers with operating frequencies of 20 GH2 or more.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図は本
発明の一実施例を説明するための半導体チップの平面図
、第3図(a)〜(c)は従来のバイポーラトランジス
タの製造方法を説明するための工程順に示した半導体チ
ップの断面図である。 1.1′・・・半絶縁性基板、2.2’ 、3.3’ 
。 4.4′・・・半導体層、5・・・絶縁領域、6.6′
・・・エミッタ電極、6a−・・AuGeNi層、7.
7′・・・5i02膜、8,9・・・ホトレジスト膜、
10゜10 ’−・・ベース電極、10a、10a’−
AuZnNi層、1l−3i02膜、12.12′・・
・コレクタ電極、12a、12a”−AuGeNi層、
13・・・ホトレジスト膜。 箔2 図
1(a) to (f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor chip for explaining an embodiment of the present invention. The plan view and FIGS. 3(a) to 3(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a bipolar transistor. 1.1'...semi-insulating substrate, 2.2', 3.3'
. 4.4'...Semiconductor layer, 5...Insulating region, 6.6'
...Emitter electrode, 6a-...AuGeNi layer, 7.
7′...5i02 film, 8,9...photoresist film,
10°10'--Base electrode, 10a, 10a'-
AuZnNi layer, 1l-3i02 film, 12.12'...
・Collector electrode, 12a, 12a''-AuGeNi layer,
13... Photoresist film. Foil 2 figure

Claims (1)

【特許請求の範囲】[Claims]  半絶縁性基板上に順次堆積した一導電型の第1及び反
対導電型の第2の半導体層の上に所定のパターンで一導
電型のエミッタ層及びエミッタ電極を形成する工程、前
記第2の半導体層上に選択的に第1の導体層を形成する
工程、前記エミッタ電極及び前記第1の導体層上に絶縁
膜及び所定のパターンのホトレジスト膜を形成する工程
、該ホトレジスト膜をマスクとして前記絶縁膜及び前記
第1の導体層並びに前記第2の半導体層を異方性並びに
等方性エッチングで順次除去して前記第1の導体層から
なるベース電極を形成する工程及び前記ホトレジスト膜
及び前記ベース電極をマスクとして前記第1の導体層上
にコレクタ電極を形成する工程を含み前記コレクタ電極
を前記ベース電極に自己整合的に形成することを特徴と
するバイポーラトランジスタの製造方法。
forming an emitter layer and an emitter electrode of one conductivity type in a predetermined pattern on a first semiconductor layer of one conductivity type and a second semiconductor layer of an opposite conductivity type sequentially deposited on a semi-insulating substrate; a step of selectively forming a first conductor layer on the semiconductor layer; a step of forming an insulating film and a photoresist film in a predetermined pattern on the emitter electrode and the first conductor layer; using the photoresist film as a mask, a step of sequentially removing the insulating film, the first conductor layer, and the second semiconductor layer by anisotropic and isotropic etching to form a base electrode made of the first conductor layer, and the photoresist film and the second semiconductor layer. A method for manufacturing a bipolar transistor, comprising the step of forming a collector electrode on the first conductor layer using the base electrode as a mask, and forming the collector electrode in a self-aligned manner with the base electrode.
JP27132086A 1986-11-13 1986-11-13 Manufacture of bipolar transistor Granted JPS63124465A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27132086A JPS63124465A (en) 1986-11-13 1986-11-13 Manufacture of bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27132086A JPS63124465A (en) 1986-11-13 1986-11-13 Manufacture of bipolar transistor

Publications (2)

Publication Number Publication Date
JPS63124465A true JPS63124465A (en) 1988-05-27
JPH0588541B2 JPH0588541B2 (en) 1993-12-22

Family

ID=17498409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27132086A Granted JPS63124465A (en) 1986-11-13 1986-11-13 Manufacture of bipolar transistor

Country Status (1)

Country Link
JP (1) JPS63124465A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5344786A (en) * 1990-08-31 1994-09-06 Texas Instruments Incorporated Method of fabricating self-aligned heterojunction bipolar transistors
US5665614A (en) * 1995-06-06 1997-09-09 Hughes Electronics Method for making fully self-aligned submicron heterojunction bipolar transistor
US5702958A (en) * 1994-08-09 1997-12-30 Texas Instruments Incorporated Method for the fabrication of bipolar transistors
JP2002170829A (en) * 2000-12-04 2002-06-14 Nec Corp Heterojunction bipolar transistor and its manufacturing method
JP2011176171A (en) * 2010-02-25 2011-09-08 Nippon Telegr & Teleph Corp <Ntt> Bipolar transistor, and method of manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5344786A (en) * 1990-08-31 1994-09-06 Texas Instruments Incorporated Method of fabricating self-aligned heterojunction bipolar transistors
US5702958A (en) * 1994-08-09 1997-12-30 Texas Instruments Incorporated Method for the fabrication of bipolar transistors
US5665614A (en) * 1995-06-06 1997-09-09 Hughes Electronics Method for making fully self-aligned submicron heterojunction bipolar transistor
US5729033A (en) * 1995-06-06 1998-03-17 Hughes Electronics Fully self-aligned submicron heterojunction bipolar transistor
JP2002170829A (en) * 2000-12-04 2002-06-14 Nec Corp Heterojunction bipolar transistor and its manufacturing method
JP2011176171A (en) * 2010-02-25 2011-09-08 Nippon Telegr & Teleph Corp <Ntt> Bipolar transistor, and method of manufacturing the same

Also Published As

Publication number Publication date
JPH0588541B2 (en) 1993-12-22

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