JP3057679B2 - Heterojunction bipolar transistor and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a heterojunction bipolar transistor.

[Summary of the Invention]

According to the present invention, a heterojunction bipolar transistor has a compound semiconductor layer having an etching characteristic different from that of a base region in a portion close to or in contact with a base region of an emitter region. By being formed narrower than the upper layer, the thickness of the base region can be reduced and the device size can be reduced.

The present invention also includes a step of selectively masking a laminated structure in which a part of the emitter region has a large etching selectivity with respect to the base region and the selective etching solution, and etching a part of the emitter region with the selective etching solution. And a step of side-etching a part of the emitter region below the mask to manufacture a heterojunction bipolar transistor in which the base region is made thinner and the device size is reduced.

[Conventional technology]

FIG. 3 is an example of a conventional heterojunction bipolar transistor. The heterojunction bipolar transistor (1) is formed on a semi-insulating GaAs substrate (2) by, for example, MOCVD.
N-GaAs to be a collector region (3), p ⁺ -GaAs to be a base region (4), n-GaAs layer (6) to be an emitter region (5), and n ⁺ - A GaAs layer (7) is sequentially grown by epitaxy, and a mesa etching is performed on the emitter region (5) and the base region (4) to form a base electrode extraction region (8) and a collector electrode extraction region (9). , A collector electrode (10), a base electrode (11) and an emitter electrode (12).

[Problems to be solved by the invention]

In a heterojunction bipolar transistor, higher performance can be expected, for example, as the thickness of the base region is reduced, the base transit time is reduced. However, in the conventional structure shown in FIG. 3, the multilayer structure formed by epitaxial growth is mesa-etched to form a base electrode extraction region (8).
In forming the and the base region (3) does not have a certain degree or more thicknesses t _1, the formation of practically the base electrode extraction region in relation to the etching accuracy (8) becomes difficult, or the external base The resistance increases (ie, the sheet resistance increases due to the thinner external base region). For this reason, the base region (3) usually requires a thickness of 1000 mm or more.

Furthermore, techniques to reduce the device's size or emitter size d ₁ is wide reported. However, approximately 1μm wide as the emitter size d ₁ was limited in patterning using conventional photoresist.

The present invention has been made in view of the above circumstances, and provides a high-performance heterojunction bipolar transistor having a thin base and a reduced device size, and a method of manufacturing the same.

[Means for solving the problem]

The present invention provides a collector region (36) made of a first conductivity type compound semiconductor, a base region (35) made of a second conductivity type compound semiconductor, and an emitter region (34) made of a first conductivity type compound semiconductor. And the base region (35) has a thickness of 500Å
The emitter region (34) has a compound semiconductor layer (25) in a portion close to or in contact with the base region (35), and the compound semiconductor layer (25) and the base region (35) are exposed to a selective etching solution. To have a large etching selectivity.

In addition, the compound semiconductor layer (25) has an emitter region (34).
It is configured to be narrower than the inner upper layers (26) and (27).

The collector region (36) is GaAs or A1GaAs, respectively.
The base region (35) includes a GaAs or A1GaAs layer, the intrinsic emitter region (25) includes a GaInP layer, and the emitter region (34) includes GaAs or A1GaAs.

The present invention also provides a collector region (36) made of a first conductivity type compound semiconductor, a base region (35) made of a second conductivity type compound semiconductor, and an emitter region (34) made of a first conductivity type compound semiconductor. ) And the emitter region (34)
Has an intrinsic emitter region (25) in a portion close to or in contact with the base region (35), and the intrinsic emitter region (25) is an upper emitter region (26) above the base region (35) and the intrinsic emitter region (25). (27) and (27), when manufacturing a heterojunction bipolar transistor having a laminated structure having a large etching selectivity with respect to the first and second selective etching solutions, selectively masking the laminated structure; Etching the upper emitter regions (26) and (27) with a first selective etchant; etching the intrinsic emitter region (25) with a second selective etchant and removing the intrinsic emitter region (25) below the mask (30); twenty five)
And performing a side etching step.

The intrinsic emitter region (25) has a layer containing phosphorus.

The second selective etching solution is a hydrochloric acid-based etching solution.

The first selective etching solution is a phosphoric acid-based etching solution.

The collector region (36) includes a GaAs or A1GaAs layer, the base region (35) includes a GaAs or A1GaAs layer, the intrinsic emitter region (25) includes a GaInP layer, and the upper emitter regions (26) and (27). Include a GaAs or A1GaAs layer.

The present invention also provides a collector region (36) made of a first conductivity type compound semiconductor, a base region (35) made of a second conductivity type compound semiconductor, and an emitter region (34) made of a first conductivity type compound semiconductor. When a heterojunction bipolar transistor having a multilayer structure having a large etching selectivity with respect to a base region (35) and a selective etching solution is formed in a part (25) of the emitter region,
A step of selectively masking the laminated structure; and a step of etching a part (25) of the emitter region with a selective etching solution and side-etching a part (25) of the emitter region below the mask (30).

[Action]

The emitter region (34) is provided with a compound semiconductor layer (2) having a large band gap and a different etching characteristic with respect to the base region in a portion close to or in contact with the base region (35).
5), the base region (35) is not etched in the selective etching step in the base electrode extraction region type. Thus, a sufficiently thin (less than 500 °) base region (35) is possible. Since the base region (35) becomes thinner, the base traveling time decreases.

Further, since the thickness of the base region (35) is maintained at the thickness at the time of growth, the parasitic resistance (external base resistance) does not increase much.

Further, since the compound semiconductor layer (25) is formed narrower than the upper layers (25) and (26) in the emitter region (34),
Separates the emitter region (35) from the base electrode (33)
In addition, the size of the emitter region (34) can be reduced.

Further, the emitter region can be etched by the compound semiconductor layer (25) without affecting the base region.
Compound semiconductor layer can be reduced substantially emitter size d ₂ in the control of the etching time (25).

A step of selectively masking the laminated structure; a step of etching the upper emitter regions (26) and (27) with a first selective etching solution; and a step of etching the intrinsic emitter region (25) with a second selective etching solution. And a step of side-etching the intrinsic emitter region (25) below the mask (30), so that the intrinsic emitter region (25) is removed from the mask (30) and the upper emitter regions (26) and (27) by side etching. Can also be formed narrow.

In addition, since the intrinsic emitter region (25) has a layer containing phosphorus, a large etching selectivity between the intrinsic emitter region (25) and the base region (35) and the upper emitter regions (26) and (27). Can be taken. Then, by using a hydrochloric acid-based etchant as the second selective etchant, a selectivity particularly with respect to the base region (35) can be obtained. In addition, by using a phosphoric acid-based etching solution as the first selective etching solution, a selection ratio between the upper emitter regions (26) and (27) can be obtained.

The collector region (36) includes a GaAs or AlGaAs layer, the base region (35) includes a GaAs or AlGaAs layer, the intrinsic emitter region (25) includes a GaInP layer, and the upper emitter regions (26) and (27). Includes a GaAs or AlGaAs layer, so that the above-described etching selectivity can be increased to perform selective etching using the first and second selective etching solutions.

Selectively masking a laminated structure in which a part (25) of the emitter region has a large etching selectivity with respect to the base region (35) and the selective etching solution; ) And a part (2) of the emitter region below the mask (30)
5), a step of side-etching a part of the emitter region (2
5) can be formed narrower than the mask (30).

Embodiments Hereinafter, embodiments of a heterojunction bipolar transistor and a method for manufacturing the same according to the present invention will be described with reference to the drawings.

As shown in FIG. 1A, on a semi-insulating GaAs substrate (21), an n-GaAs layer (22) serving as a collector region, and a P ⁺ -Al layer having a thickness of 500 mm or less, which is about 300 mm in this example, serving as a base region. _X Ga _1-X
As graded composition layer (layer in which Al composition ratio _X is sequentially changed from 0 to 0.3) (23), for example, n-Al _0.1 Ga _0.9 As having a thickness of about 100 °
Layer (24), for example, an n-GaInP layer (2
5), an n-Al _X Ga _{1 -X} As graded composition layer (a layer in which the Al composition ratio _X is sequentially changed from 0.3 to 0) (26) and an n ⁺ -GaAs layer (27) are sequentially grown by, for example, MOCVD. .

n-Al _0.1 Ga _0.9 As layer (24), n-GaInP layer (25), n-Al _X Ga _1-X As graded composition layer (26) and n ⁺ -GaAs layer (27)
Is an emitter region.

Next, as shown in FIG. 1B, after an emitter electrode (for example, AuGe / Ni) (28) is formed in a required position on the n ⁺ -GaAs layer (27), the emitter electrode corresponds to an emitter region to be formed later. leaving width d ₂ to portion, and is selectively formed photoresist layer having an opening (29) in a portion corresponding to the base electrode extraction region (30).

Next, as shown in FIG. 1C, using a photoresist layer as a mask, for example, a phosphoric acid-based etching solution (H ₃ PO ₄ + H ₂ O + H ₂ O ₂ )
Thereby, the n ⁺ -GaAs layer (27) and the n-Al _X Ga _{1 -X} As gradient composition layer (26) are selectively etched. In this etching step, the n-GaInP layer (25) is not etched because of different etching characteristics from GaAs and AlGaAs, and the etching stops at the n-GaInP layer (25).

Next, selectively etching the etchant, for example hydrochloric acid, as shown in FIG. 1 D (HCl + H ₂ O) by n-GaInP layer (25). In this etching step, n-Al _0.1 Ga
_{The 0.9} As layer (24) and the P ⁺ -Al _X Ga _{1 -X} As gradient composition layer (23) are not etched, and the etching stops at the thin n-Al _0.1 Ga _0.9 As layer (24). N-GaInP layer than the emitter width d ₂ (2
If the thickness l _{1 of} 5) is sufficiently thin, n
The width d ₃ of the GaInP layer (25) can be controlled, ie the substantial emitter size (width) d ₃ can be controlled by the photoresist layer (30);
It can be made smaller than the width d ₂ which is determined by the pattern.

At this time, the n-GaInP layer (25) is etched, but the upper n ⁺ -GaAs layer (27) and the n-Al _X Ga _{1 -X} As graded composition layer (26) are not etched.

Next, as shown in FIG. 1E, a thin n-Al _0.1 Ga _0.9 As layer (see FIG. 1E) facing the opening (29) by light etching using a phosphoric acid-based etching solution (H ₃ PO ₄ + H ₂ O + H ₂ O ₂ ). After removing 24) to form a base electrode extraction region (31), a base metal (TiPtAu) (32) is deposited to form a base electrode (33) in the base electrode extraction region (31). At this time, the base electrode (33) is formed close to the intrinsic emitter region while the photoresist layer (30) serves as a deposition mask.

Next, after the photoresist layer (30) and the base metal (32) thereon are lifted off, a photoresist layer (not shown) is selectively formed in a region including the base electrode (33) and the emitter region (34). Then, using the photoresist layer as a mask, the P ⁺ -Al _X Ga _{1 -X} As gradient composition layer (23) is selectively etched away to form a collector electrode extraction region (38).
Next, a collector electrode (37) is formed in this region (38). Thus, the collector region (3
6), a base region composed of a P ⁺ -Al _X Ga _1-X As graded composition layer (3
5), comprising an n-Al _0.1 Ga _0.9 As layer (24), an n-GaInP layer (25), an n-Al _X Ga _1-X As graded composition layer (26), and an n ⁺ -GaAs layer (27). A target heterojunction bipolar transistor (40) having an emitter region (34) is obtained.

Here, in the present embodiment, the phosphoric acid-based and hydrochloric acid-based etchants are GaAs (including AlGaAs, GaInAs, etc.) and GaInP (AlGaIn
(Including P, etc.). However, the above GaAs (AlGaAs, G
aInAs) and GaInP (AlGaInP) depend on the mixed crystal ratio. The following table shows an example of the etching rate of the etchant. The liquid temperature is 20 ° C.

In the table, the concentrations of the phosphoric acid-based etching solution and the hydrochloric acid-based etching solution are examples. Although not shown, a sulfuric acid-based etchant tends to be similar to a phosphoric acid-based etchant, so that sulfuric acid-based etching can be used instead of phosphoric acid-based etching solution.

According to the above-described configuration, the n-GaInP layer (25) having an etching characteristic different from that of the GaAs-based material is provided in a part of the emitter region (34) in the vicinity of the base region (35). ), The P ⁺ -Al _X Ga _{1 -X} As gradient composition layer (23) serving as the base region (35) is hardly etched. Therefore, the base electrode extraction region (31) can be easily formed,
A heterojunction bipolar transistor (40) having a thin base region (35) with a thickness t ₂ of 500 ° or less can be constructed. The base electrode extraction region (31) in the base region (35) is etched, an increase in parasitic resistance is small because of the growth thickness t ₂ is maintained. Further, since the base metal (32) is deposited using the photoresist layer (30) at the time of forming the emitter region (34) as a mask and the base electrode (33) is formed by a so-called self-alignment method,
The base electrode (33) is formed close to the intrinsic emitter region, and can reduce parasitic resistance, that is, external base resistance.

Furthermore, without using a special process, by controlling the etching time of the n-GaInP layer (25), a photoresist layer size d ₃ of substantial intrinsic emitter region (30)
Can be made smaller than the possible full width d _2, it is possible to reduce the so-called Debye's size.

Therefore, a high-performance heterojunction bipolar transistor can be obtained. In the embodiment of FIG. 1, a thin n-AlGaAs
Since a heterojunction is formed between the layer (24) and the P ⁺ -Al _X Ga _{1 -X} As graded composition layer (23), the n-GaInP layer (25) has an appropriate impurity concentration and thickness l ₁ . Does not directly affect the device operation.

Even if the n-GaInP layer (25) is etched and narrowed, the width of the n ⁺ -GaAs layer (27) above the emitter region (34) is maintained, so that the contact with the emitter electrode (28) is maintained. Resistance is small.

In the above example, the emitter electrode (28), the base electrode (33), and the collector electrode (37) are all formed on one main surface side. However, as shown in FIG. It can also be formed on the side. In this case, an n ⁺ -GaAs substrate (41) is used as the substrate.

In the above example, the n-GaInP layer (25) is used, but AlGaInP may be used instead.

In the above example, the p ⁺ -AlGaAs base region (3
5) An n-GaInP layer (2
Although 5) was formed, an n-GaInP layer (25) can be formed in contact with the base region (35) of p ⁺ -AlGaAs. or,
GaInAs can be used instead of AlGaAs as the base region (35).

〔The invention's effect〕

According to the present invention described above, in a heterojunction bipolar transistor, a high-speed transistor can be formed by reducing the base transit time by setting the thickness of the base region to 500 ° or less. Further, a compound semiconductor layer is provided in a portion of the emitter region close to or in contact with the base region, the compound semiconductor layer and the base region have a large etching selectivity with respect to a selective etching solution, and the compound semiconductor layer is formed in the emitter region. By forming the base electrode narrower than the inner upper layer, the base electrode extraction region can be easily formed by selective etching, and the thickness of the base region can be sufficiently reduced. Further, the emitter size can be reduced. Therefore, higher performance of the heterojunction bipolar transistor can be achieved.

According to the method of the present invention described above, a step of selectively masking a laminated structure in which a part of the emitter region has a large etching selectivity with respect to the base region and the selective etching solution, and Etching the intrinsic emitter region with a second selective etchant and side-etching the intrinsic emitter region below the mask by side-etching the intrinsic emitter region with the mask and the upper emitter. It can be formed narrower than the region.

At this time, even if the intrinsic emitter region is side-etched, the width of the upper emitter region is maintained, so that the contact resistance between the upper emitter region and the emitter electrode is reduced.

According to the above another method of the present invention, a step of selectively masking a laminated structure in which a part of the emitter region has a large etching selectivity with respect to the base region and the selective etching solution; And a step of side-etching a part of the emitter region below the mask, and
Part of the emitter region can be formed narrower than the mask by side etching.

Thus, the base electrode extraction region can be easily formed, and a transistor with a reduced emitter size can be manufactured. Therefore, a high-performance heterojunction bipolar transistor can be manufactured.

[Brief description of the drawings]

1A to 1F are cross-sectional views showing an example of a heterojunction bipolar transistor according to the present invention in the order of steps, FIG. 2 is a cross-sectional view showing another example of the present invention, and FIG. It is sectional drawing. (25) is an n-GaInP layer, (34) is an emitter region, (35)
Is a base region, and (36) is a collector region.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 29/205 H01L 29/73

Claims (9)

(57) [Claims] 1. A hetero-junction bipolar transistor having a collector region made of a first conductivity type compound semiconductor, a base region made of a second conductivity type compound semiconductor, and an emitter region made of a first conductivity type compound semiconductor. The emitter region has a compound semiconductor layer in a portion close to or in contact with the base region; the compound semiconductor layer and the base region have a large etching selectivity to a selective etching solution; A heterojunction bipolar transistor having a thickness of less than 500 mm. 2. The heterojunction bipolar transistor according to claim 1, wherein said compound semiconductor layer is formed narrower than an upper layer of said compound semiconductor layer in said emitter region. 3. A GaAs of the first conductivity type sequentially laminated on a substrate.
Or a collector region including an A1 GaAs layer and GaAs of the second conductivity type.
Alternatively, a base region including an A1GaAs layer and a first conductivity type GaInP
An intrinsic emitter region including a layer and GaAs or A1 of the first conductivity type.
A heterojunction bipolar transistor having an emitter region including a GaAs layer, wherein the intrinsic emitter region is formed narrower than the emitter region. 4. A semiconductor device comprising: a collector region made of a first conductivity type compound semiconductor; a base region made of a second conductivity type compound semiconductor; and an emitter region made of a first conductivity type compound semiconductor. Having an intrinsic emitter region near or in contact with the base region, wherein the intrinsic emitter region comprises a first selective etching solution, a second selective etching solution, and an upper emitter region above the base region and the intrinsic emitter region. In a method for manufacturing a heterojunction bipolar transistor having a stacked structure having a large etching selectivity with respect to a liquid, a step of selectively masking the stacked structure, and etching the upper emitter region with the first selective etching solution And etching the intrinsic emitter region with the second selective etching solution. Method of manufacturing a heterojunction bipolar transistor having a step of side-etching in the intrinsic emitter region of the mask downward while. 5. The method for manufacturing a heterojunction bipolar transistor according to claim 4, wherein said intrinsic emitter region has a layer containing phosphorus. 6. The method according to claim 5, wherein the second selective etching solution is a hydrochloric acid-based etching solution. 7. The method for manufacturing a heterojunction bipolar transistor according to claim 6, wherein said first selective etching solution is a phosphoric acid-based etching solution. 8. The collector region includes a GaAs or A1 GaAs layer, the base region includes a GaAs or A1 GaAs layer, the intrinsic emitter region includes a GaInP layer, and the upper emitter region includes a GaAs or A1 GaAs layer.
The method for manufacturing a heterojunction bipolar transistor according to claim 4, comprising an aAs or A1GaAs layer. 9. An emitter region comprising a collector region made of a first conductivity type compound semiconductor, a base region made of a second conductivity type compound semiconductor, and an emitter region made of a first conductivity type compound semiconductor. A method of manufacturing a heterojunction bipolar transistor having a laminated structure having a large etching selectivity with respect to the base region and the selective etching solution; selectively masking the laminated structure; Etching part of the emitter region with a liquid and side-etching a part of the emitter region below the mask.