JPH098055A - Hetero-bi-polar semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To improve through-put and protect a base layer stably by adopting such a method as providing a base protection layer composed of first and second emitter layers and an emitter protection layer extended on a base layer in a region between a base electrode and an emitter cap layer. CONSTITUTION: The device has a collector layer 23, a base layer 24, a first emitter layer 25, an emitter protection layer 26, a second emitter layer 27 and an emitter cap layer 28 composed of first to sixth III-V composed semicondcutors, respectively formed on a compound semiconductor board 21. It also has a cap layer 29 formed on the emitter cap layer 28, an emitter electrode 30 formed on the cap layer 29, a base electrode 31A and a collector electrode 34A. Furthermore, it also has a base protection layer which is composed of the first and second emitter layers 25, 27 and the emitter protection layer 26 extended on the base layer 24 in a region between the base electrode 31A and the emitter cap layer 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hetero bipolar semiconductor device, and more particularly to a semiconductor device having a heterojunction bipolar transistor (HBT) and a method of manufacturing the same.

[0002]

2. Description of the Related Art HBTs are expected to be applied to microwave devices, optical communication drivers, and the like because they can operate at high speed and have high current driving capability. The HBT has an emitter region formed of a semiconductor material having a bandgap wider than that of the base region. When the base-emitter junction is forward biased, majority carriers in the emitter region are injected into the base region, but due to the difference in band gap, majority carriers in the base region are difficult to be injected into the emitter region. Therefore, a high current gain can be expected.

FIG. 5 shows a conventional AlGaAs / GaAs HBT. On the GaAs substrate 1, a collector contact layer 2 made of n ⁺ type GaAs, a collector layer 3 made of n type GaAs, and pGa
A base layer 4 made of As, an emitter layer 5 made of n-type AlGaAs, an emitter cap layer 6, and a cap layer 7 are sequentially formed. Emitter layer 5, base layer 4 and collector layer 3
Are sequentially stepwise mesa-etched, and an emitter electrode 8, a base electrode 9 and a collector electrode 10 are formed on each of the emitter layer 5, the base layer 4 and the collector layer 3.

The surface layer 9 of p-type GaAs has a high surface recombination rate, and when the base layer 9 is exposed, electrons are trapped on the exposed surface, so that the current gain is reduced. Therefore, it is preferable not to expose the base layer 4 in order to prevent a decrease in current gain. As a countermeasure, it is effective to thinly extend the emitter layer 5 in a region between the emitter layer 5 and the base electrode 9 to cover the region. The thin emitter layer 5 is called a guard ring 5a or a base protective layer.

When the guard ring 5a has a thickness of about 10 to 100 nm, the guard ring 5a is depleted and almost no carriers are present, so that no current flows between the emitter layer 5 and the base electrode 9. However, the thickness of the GaAs emitter layer 5 forming the guard ring 5a is set to 1 by etching.
It is difficult to control it to be 0-100 nm,
There is a problem of reduction in yield and shortening of device life.

Therefore, the present applicant has proposed an HBT having a structure as shown in FIG. 6 in an application dated July 25, 1994. The manufacturing process of the HBT is as follows.
That is, after forming a thin emitter layer 11 made of n-type InGaP on the base layer 4, an emitter protection layer 12 made of n-type GaAs, an etching stop / emitter layer 13 made of n-type InGaP, and an n-type Emitter cap layer 14 made of GaAs, cap layer 1 made of n ⁺ type InGaAs
5 is laminated in order. Then, the cap layer 15 and the emitter cap layer 14 are etched by changing the etchant using the emitter electrode 8 as a mask to form these layers into a mesa shape. As those etchants, those which do not etch the etching layer / emitter layer 13 are used.

Subsequently, the mesa-shaped emitter cap layer 1
Etching stop and emitter layer 1 using 4 etc. as a mask
Etch 3 to make it a mesa shape. in this case,
An etchant that does not etch the emitter protection layer 12 is used. Here, the emitter protection layer 12 is the emitter layer 1
It is formed in order to prevent the oxidation of 1. As a result, the emitter layer 11 and the emitter protection layer 12 in the regions on both sides of the mesa-shaped emitter cap layer 14 remain unchanged in thickness, and those layers function as a guard ring in that region. Therefore, HB of such a structure
T improves the yield and extends the device life.

[0008]

However, according to such a process, the etchant must be changed in order to individually etch the emitter cap layer 14 and the etching stop layer 13, and the throughput is lowered. I have a hate. When the emitter protection layer 12 exposed in the region between the emitter cap layer 14 and the base electrode 9 is damaged, the emitter layer 11 deteriorates and the base protection becomes unstable.

The present invention has been made in view of the above problems, and an object thereof is to provide a hetero-bipolar semiconductor device capable of improving the throughput and stably protecting the base layer, and a method for manufacturing the same. .

[0010]

[Means for Solving the Problems]
As illustrated in (b), the compound semiconductor substrate 21, the collector layers 22 and 23 made of the first III-V group compound semiconductor formed on the compound semiconductor substrate 21, and the collector layers 22 and 23 are formed. A base layer 24 made of a second III-V group compound semiconductor formed on the base layer 24, a collector electrode 34 formed on the side of the base layer 24 at a distance, and formed on the base layer 24. A first emitter layer 25 having a wider bandgap than the second III-V compound semiconductor forming the layer 24 and formed of a third III-V compound semiconductor containing phosphorus as a V-group element. An emitter protection layer 26 made of a fourth III-V group compound semiconductor formed on the first emitter layer 25, and the first protection layer 26 formed on the emitter protection layer 26 and constituting the base layer 24. Second III-V compound Fifth III- which has a bandgap wider than that of semiconductors and contains phosphorus as a Group V element
Second emitter layer 27 formed from group V compound semiconductor
And a sixth II formed on the second emitter layer 27.
Emitter cap layer 28 made of IV compound semiconductor
A cap layer 29 formed on the emitter cap layer 28, an emitter electrode 30 formed on the cap layer 29, and the base layer 24 in a region laterally separated from the emitter cap layer 28. Formed on the base electrode 31A, the first and second emitter layers 25 and 27 extending on the base layer 24 in the region between the base electrode 31A and the emitter cap layer 28, and the emitter. A heterobipolar semiconductor device having a base protective layer formed of the protective layer 26 is provided.

The base layer is made of GaAs, the first and second emitter layers are made of InGaP, and the emitter protection layer is made of GaAs or AlGaAs. Alternatively, as illustrated in FIGS. 1 to 3, the compound semiconductor substrate 2
Forming a collector layer 22 made of a first III-V group compound semiconductor on the first layer, and forming a second collector layer 22 on the collector layer 23.
A step of forming a base layer 24 made of a III-V group compound semiconductor, and the second III-V forming the base layer 24.
Has a wider bandgap than Group I compound semiconductors and
Forming a first emitter layer 25 formed from a third III-V group compound semiconductor containing phosphorus as a group element on the base layer 24; and forming a fourth emitter layer 25 on the first emitter layer 25. Emitter protection layer 26 made of III-V group compound semiconductor
A fifth step of forming phosphorus on the emitter protection layer 26 having a bandgap wider than that of the second III-V group compound semiconductor forming the base layer 24 and containing phosphorus as a V group element. Forming a second emitter layer 27 made of a III-V compound semiconductor, and forming an emitter cap layer 28 made of a sixth III-V compound semiconductor on the second emitter layer 27. And a step of forming a cap layer 29 on the emitter cap layer 28,
Forming an emitter electrode 30 on the cap layer 29; etching the emitter cap layer 28 using the emitter electrode 30 as a mask and the second emitter layer 27 as an etch stop layer; The step of leaving the insulating film 40 under the electrode 30, and the insulating film 40 on the upper surface and the side surface of the emitter electrode 30, the side surface of the emitter cap layer 28 and the upper surface of the second emitter layer 27.
And a step of anisotropically etching the insulating film 40 to leave the insulating film 40 on the side surface of the emitter electrode 30 and below the emitter electrode 30, and on the emitter electrode 30 and the insulating film. 40, a step of depositing a metal material on the side of the insulating film 40 to form a base electrode 31A electrically connected to the base layer 24 on the side of the insulating film 40. This is solved by a method of manufacturing a device.

Alternatively, the base electrode 30 uses the insulating film 40 as a mask to form the second emitter layer 27.
Alternatively, the metal material 31 to be the base electrode 31A is deposited after the step of etching the emitter protective film 26 or the first emitter layer 25 and selectively leaving the emitter protective film 26 or the first emitter layer 25 only under the emitter electrode 30 and the insulating film 40. It is characterized by being done.

[0013]

[Operation] According to the present invention, in the region between the emitter region and the base electrode, the first emitter layer on the base layer is also used as the base protective layer, and the emitter protective film covering the first emitter layer is formed. Since the second emitter layer, which functions as an etch stop layer above, is left unpatterned, surface recombination on the surface of the base layer is suppressed and the step of patterning the etching stop layer can be omitted, improving throughput. To do.

In the area for protecting the base layer,
Since the emitter protection layer formed between the first and second emitter layers is not exposed, the emitter protection film is not damaged or overetched.
Further, in the region between the emitter region and the base electrode, the emitter protection layer is sandwiched in the emitter layer serving as the base protection layer, so that the base protection is stable and a stable current gain can be obtained for a long period of time.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 3 show an HBT according to a first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the manufacturing process of. First, as shown in FIG. 1A, on a semi-insulating substrate 21 made of GaAs, an n ⁺ type collector contact layer 22 made of GaAs, an undoped collector layer 23 made of GaAs, and a p ⁺ type base made of GaAs. Layer 24, first n-type emitter layer 25 made of InGaP, Ga
An n-type emitter protection layer 26 made of As, a second n-type emitter layer 27 made of InGaP, an emitter cap layer 28 made of GaAs, and an n ⁺ type cap layer 29 made of InGaAs are sequentially grown by MOCVD.

The collector contact layer 22 is 3 × 10.¹⁸cm
^-3Impurity concentration of 500 nm, collector layer 23 is
Undoped and 450 nm thick, the base layer 24 is 4 ×
¹⁹cm ^-3Impurity concentration, 70 nm thickness, first n-type emission
Data layer 25 is 3 × 10¹⁷cm^-3Impurity concentration, thickness of 30nm
Now, the emitter protection layer 26 is 3 × 10^{1 7}cm^-3Impurities
Concentration: 5 nm, second n-type emitter layer 27 is 3 × 1
0¹⁷cm^-3Each has an impurity concentration of 10 nm and a thickness of 10 nm
I have. The emitter cap layer 28 has a thickness of 300 nm.
And the impurity concentration of the lower half layer is 3 × 10¹⁷
cm^-3, The impurity concentration of the upper half layer is 3 × 10¹⁸cm^-3Into shape
And the cap layer 29 has an impurity concentration of 3 × 1.
0¹⁸cm^-3The film thickness is 100 nm.

In this state, a WSi layer having a film thickness of 400 nm is deposited on the surface of the cap layer 29 by sputtering, and then the emitter region of the WSi layer (not shown) is covered with a resist pattern (not shown) to remove CF ₄ and O _2. Using mixed gas of
The WSi layer was anisotropically etched, leaving W remaining in the emitter region.
The Si layer is used as the emitter electrode 30. After this, the resist pattern is removed.

Next, as shown in FIG. 1B, the cap layer 29 is wet-etched using the emitter electrode 30 as a mask. H ₃ PO ₄ and H as etchants
Use a mixture of ₂ O. Then, the emitter cap layer 28 is isotropically dry-etched. In this case, the etching gas is the second n-type emitter layer 27 made of InGaP.
A mixed gas of CF ₄ and SiCl ₄ is used to prevent the removal of C.

As a result, the cap layer 29 and the emitter cap layer 28 remain in a mesa shape in the emitter region. After that, a silicon nitride (SiN) film having a thickness of 100 nm is formed along the surfaces of the emitter electrode 30, the cap layer 29, the emitter cap layer 28, and the second n-type emitter layer 27 by the CVD method.
Formed to a thickness of

Next, as shown in FIG. 1 (c), CF ₄ and C
The SiN film 40 is vertically etched by reactive ion etching using a mixed gas of HF ₃ , so that the SiN film 40 is selectively formed only under the emitter electrode 30, the periphery of the emitter electrode 30, and the region immediately below the emitter electrode 30. leave. This makes In
Since a part of the second n-type emitter layer 27 made of GaP is exposed, as shown in FIG. 2A, the second n-type emitter layer 2 in a region not covered by the SiN film 40 and the emitter electrode 30 is exposed.
7 is etched with HCl to expose the emitter protection film 26 thereunder. At this time, the second n-type emitter layer 2
7 is side-etched and recedes inward from the edge of the SiN film 40.

Next, as shown in FIG. 2 (b), by vapor deposition
20 nm, 20 nm, 40 nm and 8 for Pd, Zn, Pt and Au respectively
The first multilayer metal film 31 is formed by sequentially depositing each 0 nm. In this case, the edge of the SiN film 40 causes the second n-type miter layer 2
The contact between 7 and the first multilayer metal film 31 is prevented. next,
As shown in FIG. 2C, after covering the region from the emitter electrode 30 to the base region with the resist pattern 32, the first multilayer metal film 31 not covered with the resist pattern 32.
Are removed by ion milling using argon, and the remaining first multilayer metal film 31 is used as the base electrode 31A.

Subsequently, the emitter protection film 26 made of GaAs in a region not covered with the resist pattern 32 is formed with H ₃ P.
It is removed with a mixed solution of O ₄ , H ₂ O ₂ and H ₂ O, and the first n-type emitter layer 24 made of InGaP underneath is removed by HC.
1 and H ₃ PO ₄ are removed with a mixed solution of H ₃ PO ₄ , and the base layer 24 made of GaAs up to about 100 nm of the collector layer 23 is removed with a mixed solution of H ₃ PO ₄ , H ₂ O ₂ and H ₂ O. After that, the resist pattern 32 is removed.

Next, as shown in FIG. 3 (a), a resist 33 is applied again to the entire surface, and the resist 33 is exposed and developed to form a window 33a on the collector layer 23 at a distance from the base layer 24. . Then, the collector layer 23 exposed from the window 33a
Is completely removed with a mixture of H ₃ PO ₄ , H ₂ O ₂ and H ₂ O. As a result, the collector contact layer 22 is exposed from the window 33a.

Next, a 30 nm thick AuGe film and a 10 nm thick film are formed.
A second multilayer metal film 34 made of Ni and Au having a film thickness of 300 nm is vapor-deposited on the entire surface, and subsequently, as shown in FIG. 3B, the resist 33 is removed and lift-off is performed on the collector contact layer 22. Only the second multilayer metal film 34 is left, and this is used as the collector electrode 34A. Next, in a nitrogen atmosphere,
Heat treatment is performed at a temperature of 0 ° C. for 15 minutes. As a result, the vicinity of the boundary between the collector electrode 34A and the collector contact layer 22 therebelow is alloyed, and the collector electrode 34A and the collector contact layer 22 make ohmic contact, and at the same time, the metal reaction reaching the base layer 24 from the base electrode 31A. The region 35 is formed, and the base layer and the base electrode are in ohmic contact with each other.

In this case, since the surface of the first n-type emitter layer 26 is prevented from being oxidized by the emitter protection film 26, conductive indium oxide is formed by the oxidation of the first n-type emitter layer 25. There is no. Also, the second n
The second n-type emitter layer 2 may be formed by exposing the type emitter layer 26 and forming indium oxide on its surface.
Since 7 is separated from the base electrode 31A, the base electrode 31A
The emitter cap layer 28 is not electrically connected to the emitter cap layer 28.

In this case, the second n-type emitter layer 27, the emitter protection layer 26 and the first n-type emitter layer 2 existing in the region between the emitter cap layer 28 and the base electrode 31A.
The InGaP layer / GaAs layer / InGaP layer that constitutes No. 5 is shown in Fig. 2 (c).
A base protective layer GR for protecting the base layer 24 as shown in FIG.
Becomes This completes the formation of the basic structure of the HBT.

In the above steps, since the second n-type emitter layer 27 forming the uppermost part of the base protective layer is used as the etching stop layer, the thickness of the base protective layer can be easily controlled and the yield is improved. Moreover, since the second n-type emitter layer 27 that functions as an etching stop layer is left between the emitter region and the base electrode 31A, the step of removing the second n-type emitter layer 27 before forming the SiN film 40. Can be eliminated and throughput can be improved.

When the second n-type emitter layer 27 between the emitter region and the base electrode 31A is to be etched, the etchant may also etch the first n-type emitter layer 25 through the emitter protection layer 26. is there. Further, since the first n-type emitter layer 25 and the emitter protection film 26 are extremely thin, 30 nm and 5 nm, respectively, they are depleted between the emitter region and the base electrode 31A, and the base electrode 31A and the emitter cap layer 28 are electrically connected. Not done.

Further, when the reliability of the HBT formed by the above process was investigated, the following results were obtained. The emitter current density of the above HBT is set to 6 at 250 ° C.
When the time-dependent change of the current gain was examined with the constant value of × 10 ⁴ cm ^-3 , the life was 500 hours or more. Here, the bonding temperature exceeds 300 ° C. when the ambient temperature is 250 ° C., but it is shown that a stable HBT under such severe conditions has sufficient reliability. (Second Embodiment) The base electrode 31A of the first embodiment is formed on the emitter protection layer 25 in the region where the second n-type emitter layer 27 is removed. As shown in (c), it may be brought into direct contact with the second n-type emitter layer 27, or may be brought into contact with the first n-type emitter layer 25 and the base layer 24.

When the base electrode 31A is formed on the second n-type emitter layer 27, the total thickness of the first emitter 25, the protective layer 26, and the second emitter layer 27 is extremely thin at 45 nm, so the whole structure is small. Since it is depleted, the first emitter layer 2
No current flows from the base electrode 31A to the emitter cap layer 28 through the emitter protection layer 26, the emitter protection layer 26, and the second emitter layer 27. (Other Embodiments) In the above embodiments, Pd / Zn / Pt / Au
However, other non-gold materials such as Pt / Ti / Pt / Au or Ti / Pt / Au may be used.

The base electrode reaction layer 35 below the base electrode 31A is formed to the base layer 24 through the first and second InGaP n-type emitter layers 25 and 27. Even if the reaction with the metal is stopped in the middle of the first n-type emitter layer 25 made of InGaP, a thin InGaP layer that allows holes to tunnel can be left between the base electrode reaction layer 35 and the base layer 24. Good.

Further, although the above HBT is of npn junction type, it may be of pnp junction type. Although the above-mentioned sidewalls are formed from the SiN film, other insulating materials such as SiO ₂ may be used, or the sidewalls may not particularly be formed. The collector layer is not i-type but n-type or p-type
The conductivity type of the mold may be used. The collector structure is not limited to the embodiment.

In the above embodiment, the base layer is made of GaAs, but in this case, the emitter protection layer 26 may be made of AlGaAs and the emitter layers 25 and 27 may be made of AlInGaP. When the base layer is made of InGaAs, the emitter protection layer 26 may be made of a material not containing In such as GaAs, and the emitter layers 25 and 27 may be made of InP. The materials of the first emitter layer and the emitter protection layer are preferably selected so as to have lattice matching.

[0034]

As described above, according to the present invention, in the region between the emitter region and the base electrode, the first emitter layer on the base layer is also used as the base protective layer and the first emitter layer is used. Since the second emitter layer that functions as an etch stop layer is left unpatterned on the emitter protection film, the surface recombination on the surface of the base layer is suppressed and the etching stop layer is patterned. It can be omitted and throughput can be improved.

In the area for protecting the base layer,
Since the emitter protection layer formed between the first and second emitter layers is not exposed, damage to the emitter protection film and overetching can be prevented. Furthermore, in the region between the emitter region and the base electrode, the emitter protection layer is sandwiched between the emitter layers serving as the base protection layer, so that the base protection is stable and a stable current gain can be obtained for a long time.

[Brief description of drawings]

FIG. 1 is a sectional view (1) showing a manufacturing process of an HBT according to a first embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) showing a manufacturing process of the HBT according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view (3) showing the process of manufacturing the HBT according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing the structure of an HBT according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing an example of a conventional HBT.

FIG. 6 is a sectional view showing an example of an HBT according to the prior application.

[Explanation of symbols]

 21 substrate (compound semiconductor substrate) 22 collector contact layer 23 collector layer 24 base layer 25 first emitter layer 26 emitter protective layer 27 second emitter layer 28 emitter cap layer 29 cap layer 30 emitter electrode 31A base electrode 34A collector electrode GR Base protection layer (guard ring)

Claims (4)

[Claims] 1. A compound semiconductor substrate, a collector layer made of a first III-V group compound semiconductor formed on the compound semiconductor substrate, and a second III-V group compound formed on the collector layer. A base layer made of a semiconductor, a collector electrode formed at a distance to the side of the base layer, and a second III-V group compound semiconductor formed on the base layer and constituting the base layer. A first emitter layer formed of a third III-V group compound semiconductor having a wide band gap and containing phosphorus as a V group element, and a fourth III-layer formed on the first emitter layer. An emitter protection layer made of a group V compound semiconductor, having a bandgap wider than that of the second III-V group compound semiconductor formed on the emitter protection layer and constituting the base layer, and phosphorus as a group V element. Fifth III-including
A second emitter layer formed of a group V compound semiconductor, an emitter cap layer formed of a sixth III-V group compound semiconductor formed on the second emitter layer, and formed on the emitter cap layer An emitter electrode, a base electrode formed on the base layer in a region laterally separated from the emitter cap layer, and a base electrode formed on the base layer in a region between the base electrode and the emitter cap layer. A hetero-bipolar semiconductor device having the first and second emitter layers present and a base protective layer composed of the emitter protective layer. 2. The hetero-bipolar type according to claim 1, wherein the base layer is made of GaAs, the first and second emitter layers are made of InGaP, and the emitter protection layer is made of GaAs or AlGaAs. Semiconductor device. 3. A step of forming a collector layer made of a first III-V group compound semiconductor on a compound semiconductor substrate, and a base layer made of a second III-V group compound semiconductor on the collector layer. And a first III-V compound semiconductor having a bandgap wider than that of the second III-V compound semiconductor constituting the base layer and containing phosphorus as a V-group element. Forming an emitter layer on the base layer, forming an emitter protective layer made of a fourth III-V group compound semiconductor on the first emitter layer, and forming an emitter protective layer on the emitter protective layer. A second emitter layer formed of a fifth III-V group compound semiconductor having a bandgap wider than that of the second III-V group compound semiconductor forming the base layer and containing phosphorus as a V group element. And a step of forming Forming a sixth III-V compound semiconductor emitter cap layer on the second emitter layer; forming an emitter electrode on the emitter cap layer; and using the emitter electrode as a mask And using the second emitter layer 27 as an etching stop layer to etch the emitter cap layer so that it remains below the emitter electrode, and the upper surface and the side surface of the emitter electrode, the side surface of the emitter cap layer, and the side surface of the emitter cap layer. Forming an insulating film on the upper surface of the second emitter layer; anisotropically etching the insulating film to leave the insulating film on the side surface of the emitter electrode and below the emitter electrode; A metal material is deposited on the upper side of the insulating film to form a base electrode electrically connected to the base layer on the side of the insulating film. Method for producing a hetero bipolar semiconductor device characterized by having a that step. 4. The base electrode is formed under the emitter electrode and the insulating film by etching up to the second emitter layer, the emitter protective film, or the first emitter layer using the insulating film as a mask. 4. The method for manufacturing a hetero-bipolar semiconductor device according to claim 3, wherein the metal material to be the base electrode is deposited after the step of selectively leaving only the above.