JP3349267B2 - Hetero bipolar semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor, and more particularly to a heterojunction bipolar transistor (H).
BT). Since the HBT can operate at high speed and has a high current driving capability, it is expected to be applied to a microwave device, a driver for optical communication, and the like.

[0002]

2. Description of the Related Art An HBT has an emitter region formed of a semiconductor material having a band gap wider than that of a base region. When the base-emitter junction is forward-biased, majority carriers in the emitter region are injected into the base region, but it is difficult for majority carriers in the base region to be injected into the emitter region due to a difference in band gap. Therefore, a high current gain can be expected.

FIG. 10A shows a conventional AlGaAs / GaAs.
1 shows an HBT of the s system. N-type GaAs on a GaAs substrate 50
s collector layer 51, p-type GaAs base layer 52, n
An AlGaAs emitter layer 53 is formed in this order. Mesa etching is performed stepwise in the order of emitter, base, and collector to form an emitter electrode 57, a base electrode 56, and a collector electrode 55 on the emitter, base, and collector, respectively.

Since p-type GaAs as a base layer has a high surface recombination speed, when the base layer 52 is exposed, electrons are trapped on the exposed surface, and the current gain is reduced. Therefore, it is preferable that the base layer 52 is not exposed in order to prevent a decrease in current gain. As a countermeasure, a thin layer 5 of an emitter layer called a guard ring (base protection layer) is provided between the emitter layer 53 and the base electrode 56.
It is effective to leave the base layer 8 and cover the base layer 52.

At this time, the emitter layer 53 and the base electrode 5
6 are in contact with each other via the guard ring 58, but the carrier does not flow directly from the base electrode 56 to the emitter layer 53 by depleting the guard ring 58.

In order to form the guard ring 58 of this structure, it is necessary to dry-etch or wet-etch AlGaAs of the emitter layer 53 and control the etching time to leave the guard ring 58 of 30 to 100 nm. . However, it is difficult to leave such a thin guard ring 58 by controlling the etching time.

FIG. 10B shows an HBT having a structure for solving the above problem. This is disclosed in JP-A-4-286.
No. 126. The HBT shown in FIG. 10A is different from the HBT in that the emitter layer 53 is separated into two layers of the emitter layers 53a and 53b by the etching stop layer 59 containing In, and that the base layer 52 and the emitter layer 53 are separated.
The difference is that an etching stop layer 30 containing In is inserted at the interface with b.

When the emitter layer 53 a is etched to form the guard ring 58, the etching stops at the etching stop layer 59. Therefore, the emitter layer 53b
Is formed to a desired film thickness, it is not necessary to precisely control the etching time, and the guard ring 58 can be easily formed. Further, the emitter layers 53a, 53
Even when the surface of the base layer is exposed by mesa etching of b, the etching can be stopped by the etching stop layer 30 on the surface of the base layer 52.

FIG. 10C shows an HBT having another structure for solving the problem of the HBT of the structure of FIG. 10A.
This is disclosed in JP-A-3-053563. The GaAs base layer 52 is covered with an extremely thin AlGaAs emitter layer 53c of about 25 nm, on which an n-GaAs emitter cap layer 61 is formed.

[0010] The emitter cap layer 61 is selectively dry-etched to form a mesa. At this time, if a gas that does not etch AlGaAs is used as the GaAs etching gas, the emitter layer 53c can be left on the base layer 52.

The emitter cap layer 61 left in a mesa shape
Is formed around the base electrode 56 made of AuBe or the like. This is subjected to a heat treatment so that the base electrode 56 and the base layer 5 are formed.
Ohmic contact with 2 can be made.

In this structure, the entire surface of the base layer 52 is covered with the emitter layer 53c. Thus, the guard ring 58 made of AlGaAs can be formed on the base layer 52. In addition, the same structure as above, except that the emitter layer 53c is made of InGaP, is an extended abstract of SSDM92.
Page 316 of c) or Electronics Letters Vo
l.28 p2308 (1992).

[0013]

In order to improve the high frequency characteristics of the HBT, it is necessary to increase the impurity concentration of the base region in order to reduce the base resistance. However, when the impurity concentration in the base region is increased, holes in the base region flow into the emitter region, and the current gain is reduced.

When the base region is made of GaAs, the energy difference of the valence band at the interface between the emitter region and the base region is smaller in the case where InGaP is used in the emitter region than in the case where InGaP is used.
It is larger than when GaAs is used. Therefore, if InGaP is used for the emitter region, injection of holes, which are majority carriers in the base region, into the emitter region is suppressed in principle. Therefore, by using InGaP for the emitter region, the current gain can be improved as compared with the case where AlGaAs is used.

Similarly, when the base region is made of InGaAs, the use of InAlAs for the emitter region is less than the case where InAlAs is used for the emitter region.
The current gain can be improved in principle by using nP. As described above, by using a III-V group compound semiconductor using phosphorus as a group V element as a material of the emitter, a decrease in current gain when the base region is made highly concentrated can be suppressed in principle. Therefore, an HBT using InP or InGaP as an emitter is promising as a microwave device.

However, InP and InGaP have poor controllability of etching, and it is difficult to etch such that a guard ring shown in FIG. 10A is left. In addition, phosphorus-based semiconductors,
In particular, those containing In as a group III element are very unstable with respect to the surface protective film.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-frequency HBT having a high-frequency characteristic in which the base region is highly concentrated without reducing the current gain and the leakage current between the base and the emitter is prevented from increasing.
It is to provide.

[0018] A heterobipolar semiconductor device according to the present invention comprises a supporting substrate and a III-V substrate formed on the supporting substrate.
A collector layer made of a group V compound semiconductor; and a III- layer formed on the collector layer and containing arsenic as a group V element.
A base layer made of a group V compound semiconductor; a first emitter layer formed on the base layer, made of a III-V compound semiconductor containing phosphorus as a group V element, and having a wider band gap than the base layer; An emitter protection layer formed on the first emitter layer and made of a semiconductor having a function of passivating a surface of the first emitter layer;
Formed at least on the emitter protection layer;
An electrical connection with the first emitter layer through a mitter protection layer.
III-V compound containing phosphorus as group V element
A hetero-bipolar semiconductor device having a second emitter layer made of a semiconductor and a base electrode in ohmic contact with the base layer, wherein an upper surface of the first emitter layer is
Substantially the entire surface is covered by the emitter protective layer or the emitter protective layer and the base electrode, and the first emitter layer is in contact with the base electrode, and In the region near the end of the base electrode, the entire thickness is depleted.

[0019]

By using a phosphorus-based III-V compound semiconductor such as InP or InGaP for the emitter, the energy difference of the valence band at the interface between the emitter and the base can be increased. For this reason, even if the base has a high concentration, the current gain does not easily decrease, and the high-frequency characteristics can be improved. In addition, by covering the surface of the base layer with the first emitter layer, surface recombination and the like can be suppressed, and reliability can be improved.

On the emitter protective layer, a phosphorus-based second
When an emitter layer is formed, an arsenic-based etching stop layer formed by an emitter protective layer is inserted into a phosphorus-based emitter. Therefore, the etching can be stopped while leaving the thin film of the first emitter layer. For this reason,
A guard ring between the emitter region and the base electrode can be easily formed. Thereby, recombination of electrons at the interface of the base layer can be suppressed, and the current gain can be improved.

By covering the surface of the guard ring, which is a III-V compound semiconductor containing In and phosphorus, with an etching stop layer, which is an arsenic III-V compound semiconductor, insulation protection between the phosphorus and the phosphorus III-V compound semiconductor is achieved. A structure in which the film does not directly contact can be provided. Therefore, instability due to contact between the III- V compound semiconductor containing In and phosphorus and the insulating protective film can be avoided.

Further, by arranging the arsenic-based III-V compound semiconductor layer in the emitter region of the III-V compound semiconductor containing In and phosphorus, electrons can be transported regardless of the use of the etching stop layer. On the other hand, a potential barrier can be prevented from being formed.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An HBT according to a first embodiment of the present invention will be described below with reference to FIGS. 1, 2A to 2D.

On a semi-insulating GaAs substrate 1, an n ⁺ type G
aAs collector contact layer 2, n-type GaAs collector layer 3, p ⁺ -type GaAs base layer 4, n-type InGaP emitter layer 5, n-type GaAs emitter protection layer 6, n-type InG
aP emitter layer 7, n ⁺ -type GaAs layer and n ⁺ -type InGa
An emitter cap layer 8 having a two-layer structure of an As layer is formed in this order by gas source MBE or MOCVD.

The GaAs collector contact layer 2 has an impurity concentration of about 3 × 10 ¹⁸ cm ⁻³ and a thickness of about 500 nm. The impurity concentration of the GaAs collector layer 3 is about 3 × 10 ¹⁶
cm ^-3 and a film thickness of about 400 nm. The GaAs base layer 4 has an impurity concentration of about 4 × 10 ¹⁹ cm ⁻³ and a thickness of about 70 n.
m. The impurity concentration of the InGaP emitter layer 5 is about 5
× 10 ¹⁷ cm ^-3 and a film thickness of about 50 nm.

The impurity concentration of the GaAs emitter protective layer 6 is
About 5 × 10¹⁷cm^-3And the film thickness is about 5 nm. InGa
The impurity concentration of the P emitter layer 7 is about 5 × 10¹⁷cm^-3,film
The thickness is about 100 nm. Ga of the emitter cap layer 8
The impurity concentration of the As layer is about 3 × 10¹⁸cm^-3, Film thickness is about 1
00 nm, the impurity concentration of the InGaAs layer is about 5 × 10 ¹⁹
cm^-3, And the film thickness is about 100 nm.

Hereinafter, a method of manufacturing the HBT according to the first embodiment will be described with reference to FIGS. 2A to 2D. FIG.
A shows a step of forming an emitter mesa. The emitter electrode 1 is formed on the substrate having the multilayer structure prepared as described above.
About 50 tungsten silicide (WSi) films
The WSi film is formed to a thickness of 0 nm, and the WSi film other than the portion serving as the emitter is removed by photolithography.

Next, GaAs is formed using the WSi film as a mask.
The surface of the InGaP emitter layer 7 is exposed by etching the / InGaAs emitter cap layer 8. afterwards,
The emitter layer 7 is etched with a mixed solution of hydrochloric acid and pure water.
Since the mixed solution of hydrochloric acid and pure water does not etch GaAs, the etching stops at the surface of the GaAs emitter protective layer 6. Thus, the InGaP emitter layer 7, G
aAs / InGaAs emitter cap layer 8 and WSi
An emitter mesa 30 composed of three layers of the emitter electrode 11 is formed.

FIG. 2B shows a step of etching the emitter protection layer 6. The substrate prepared in the step of FIG.
A SiO ₂ film is deposited by a method or the like, and a sidewall 13 made of SiO ₂ is formed on the side surface of the emitter mesa 30 by using anisotropic reactive ion etching or the like.

Using the sidewalls as a mask, the GaAs emitter protective layer 6 is etched with a mixture of phosphoric acid (H ₃ PO ₄ ), hydrogen peroxide (H ₂ O ₂ ), and pure water.
Since this etching solution does not etch InGaP, the etching stops at the surface of the InGaP emitter layer 5.

FIG. 2C shows a step of exposing the base region. After the process of FIG. 2B, I
The nGaP emitter layer 5 is etched to expose the surface of the GaAs base layer 4.

FIG. 2D shows a step of depositing a base electrode. Ti, Pt, and Au are respectively 10 nm, 50 nm,
Vacuum deposition is performed on the substrate in this order by 200 nm. Thereby, the surface from the emitter electrode 11 to the base layer 4 is covered with the Ti / Pt / Au film. Since film deposition by vapor deposition has directivity, only a small amount of Ti / Pt / Au film is deposited on the sidewalls 13.

Next, argon ion milling is performed from an oblique direction, and the side surface of the sidewall is etched to remove an excess Ti / Pt / Au film, thereby separating the emitter electrode 11 and the base electrode 10. in this way,
The base electrode can be formed in a self-aligned manner with respect to the emitter.

Next, the base region is protected by a photoresist film, and an extra Ti / Pt / Au film is removed by ion milling. The emitter region and the base region are masked, and mesa etching is performed with a mixed solution of phosphoric acid, hydrogen peroxide and pure water to expose the GaAs collector contact layer 2 (FIG. 1). A resist mask is formed by lithography to expose the collector contact region. AuGe and Au are deposited in a thickness of 20 nm and 300 nm, respectively, and a collector electrode 9 is formed by lift-off. Then 350-450 ° C
To obtain ohmic contact with the collector.

FIG. 1 shows the HBT thus manufactured. As shown in FIG.
Between the InGaP emitter layer 5 and the surface of the base layer 4.
Is completely covered by a guard ring 12 consisting of a part of The GaAs emitter protective layer 6 is left on the surface. Therefore, since the InGaP emitter layer 5 and the protective film do not directly contact each other, an increase in leak current can be prevented.

In the above embodiment, an HBT having an InGaP / GaAs structure has been described. However, an HBT having an InP / InGaAs structure can be manufactured in the same steps. Further, a GaAs emitter protective layer was used as an etching stop layer in the case of an InGaP emitter.
Other arsenic-based III-V compound semiconductors such as s may be used. It is easy to selectively etch a phosphorus-based III-V compound semiconductor and an arsenic-based compound semiconductor having different group V elements from each other. Although the etching stop and the protection of the side wall insulating film of the emitter layer are performed by the same GaAs layer, they can be formed by separate layers.

In the case of an InP emitter, InGaAs is used as an etching stop layer, which is one element in the emitter structure, but may be InAlAs or InAlGaAs. In addition, although the example in which the lattice constant is matched with the emitter layer is illustrated as the etching stop layer, if the etching stop layer is sufficiently thin, the lattice constant need not be particularly matched.

Although FIGS. 2A to 2D show the side wall type self-aligned structure, a T-shaped self-aligned structure having an eave-shaped portion may be used. Although the case where SiO ₂ is used as the sidewall has been described, other insulators such as SiN and SiON may be used. The base electrode was Ti / Pt / Au,
Other electrodes may be used.

Next, an HBT according to a second embodiment of the present invention will be described with reference to FIGS. 3, 4A to 4D. FIG.
Shows a sectional view of the HBT according to the second embodiment. The main difference from the HBT according to the first embodiment shown in FIG. 1 is that the emitter electrode 11 projects from the end of the emitter mesa 30 like an eave, and the base electrode 10 is self-aligned by this eave-like portion. And the base electrode 1
0 is formed on the surface of the InGaP emitter layer 5,
The ohmic contact between the base electrode 10 and the base layer 4 is established by the electrode reaction region 20 extending from the base electrode 10 to the GaAs base layer 4 through the InGaP emitter layer 5.

In FIG. 1, the upper emitter layer 7 is
3 is different from the HBT of FIG. 3 in that the upper emitter layer 7 is made of GaAs. Hereinafter, FIG. 4A
The method of manufacturing the HBT shown in FIG. 3 will be described with reference to FIGS.

As shown in FIG. 4A, semi-insulating GaAs
On a substrate 1, an n ⁺ -type GaAs collector contact layer 2,
i-type GaAs collector layer 3, p ⁺ -type GaAs base layer 4, n-type InGaP emitter layer 5, n-type AlGaAs emitter protective layer 6, n-type GaAs emitter layer 7, n ⁺ -type I
The nGaAs emitter cap layer 8 is formed in this order by gas source MBE or MOCVD.

The GaAs collector contact layer 2 has an impurity concentration of about 3 × 10 ¹⁸ cm ⁻³ and a thickness of about 500 nm. The GaAs collector layer 3 is non-doped and has a thickness of about 45 nm.
0 nm. The impurity concentration of the GaAs base layer 4 is about 4
× 10 ¹⁹ cm ^-3 and a film thickness of about 70 nm. InGaP
The emitter layer 5 has an impurity concentration of about 3 × 10 ¹⁷ cm ⁻³ and a thickness of about 30 nm.

The AlGaAs emitter protective layer 6 is made of Al _x G
a _1-x As is a composition gradient layer having a composition of As, where x is 0.3 on the lower surface and x is 0 on the upper surface. The emitter protection layer 6 also serves to stop the etching and passivate the surface of the emitter layer and to smoothly connect the conduction band of the InGaP emitter layer 5 to the GaAs band structure. Also,
The impurity concentration is about 3 × 10 ¹⁷ cm ⁻³ and the film thickness is about 30 nm. The impurity concentration of the GaAs emitter layer 7 has a gradient, about 3 × 10 ¹⁷ cm ^{−3 on} the lower surface, about 3 × 10 ¹⁸ cm ⁻³ on the upper surface, and a film thickness of about 300 nm.

The emitter cap layer 8 is composed of a 50-nm _- thick composition gradient layer having a composition of In _y Ga _1-y As and a thickness of 6 nm.
It is composed of two layers of 0 nm In _0.6 Ga _0.4 As layers. Note that y is 0 on the lower surface of the composition gradient layer and 0.6 on the upper surface. A gradient is provided in the impurity concentration of the InGaAs composition gradient layer, and about 3 × 10 ¹⁸ cm
^-3 , about 3 × 10 ¹⁹ cm ^-3 on the upper surface. In _0.6 Ga
The impurity concentration of the _0.4 As layer is about 3 × 10 ¹⁹ cm ⁻³ .
The band structure is smoothly connected from the In _0.6 Ga _0.4 As layer to the InGaP emitter layer without causing a large discontinuity.

The impurity concentration of the lower surface of the emitter layer 7 is equal to the impurity concentration of the emitter layer 5. The impurity concentration on the upper surface is equal to the impurity concentration of the emitter cap layer 8. Accordingly, the emitter layer 7 functions as an emitter, and at the same time, the upper part thereof also functions as an emitter cap layer.

It is preferable that carbon is used for the p-type impurity of the GaAs base layer 4 and silicon is used for the n-type impurity of the other layers. C as a p-type impurity
When is used, it is preferable to form by MOCVD.

FIG. 4B shows a step of forming an emitter mesa. A 400 nm-thick WSi layer is deposited on the surface of the GaAs emitter cap layer 8 by sputtering. WS
Covering the emitter region on the i-layer surface with a resist pattern,
The WSi layer is anisotropically etched using a mixed gas of F ₄ and O ₂ to form the emitter electrode 11.

After removing the resist pattern, the emitter
Using the electrode 11 as a mask, the GaAs emitter cap layer 8 is
Perform wet etching. H as an etchant_Three
PO _Four, H_TwoO_TwoAnd H_TwoA mixture of O is used.

Next, the GaAs emitter layer 7 is isotropically dry-etched using a mixed gas of CCl ₂ F ₂ and He. Since this etching gas does not etch AlGaAs, the etching automatically stops at the surface of the AlGaAs emitter protective layer 6. Further, the emitter layer 7 is side-etched by performing over-etching to form an eave-shaped portion by the emitter electrode 11. Thus, the emitter mesa 30 is formed.

FIG. 4C shows a step of forming a side wall on the emitter mesa and etching the emitter protective layer 6. After side-etching the emitter layer 7, a SiN film is deposited on the entire surface of the substrate by plasma CVD. continue,
The deposited SiN film is anisotropically dry-etched with a mixed gas of CHF ₃ and CF ₄ to form a sidewall 13.

Since the anisotropic etching mainly proceeds from above the substrate to below, the side surface of the emitter mesa 30 and the region behind the eaves of the emitter electrode 11 are hardly etched. Therefore, as shown in FIG. 4C, the side wall 1 is located near the emitter mesa 30 on the surface of the emitter protection layer 6.
3 is formed.

Next, the emitter protection layer 6 is removed using the side walls 13 as a mask. H as an etchant
A mixture of ₃ PO ₄ , H ₂ O ₂ and H ₂ O is used. Since this mixed solution hardly etches InGaP, the etching automatically stops when the surface of the emitter layer 5 is exposed. Since the wet etching proceeds isotropically, the emitter protection layer 6 is slightly undercut from the end of the sidewall 13.

FIG. 4D shows a step of forming a base electrode. After removing the emitter protection layer 6, Pd, Zn, P
t and Au are 20 nm, 20 nm, 4
Evaporate to a thickness of 0 nm and 80 nm. Since the emitter protection layer 6 is undercut, Pd / Zn / Pt / A
The u layer does not contact the emitter protection layer 6. Pd / Zn / P
Regarding the deposition of the t / Au layer, the inventors of the present application have disclosed in
-259435 can be used.

Next, the emitter mesa and the base electrode region are covered with a resist pattern, and an excess region of the Pd / Zn / Pt / Au layer is removed by argon ion milling.
Subsequently, using the same resist pattern as a mask, the emitter layer 5 is etched using a mixed solution of HCl and H ₃ PO ₄ to expose the surface of the base layer 4. In addition, H ₃ PO
₄ , a base layer 4 using a mixture of H ₂ O ₂ and H ₂ O.
And the collector layer 3 is etched. When the collector layer 3 is etched from the interface with the base layer 4 to a depth of about 150 nm, the etching is stopped. In this way,
A base electrode 10 in ohmic contact with the base layer 4 is formed around the emitter mesa 30. The resist pattern is once removed.

As shown in FIG. 3, an HBT can be manufactured by forming a collector electrode 9. First, a resist pattern having an opening in a region where a collector electrode is to be formed is formed, and the collector layer 3 and the collector contact layer 2 are etched with a mixed solution of H ₃ PO ₄ , H ₂ O ₂ and H ₂ O. Etching is stopped when a hole having a predetermined depth is formed from the surface of the collector contact layer 2 to expose the collector contact layer 2. Then, AuGe, Ni, A
u is deposited to a thickness of 30 nm, 10 nm, and 300 nm, respectively, and a collector electrode 9 is formed by lift-off.

Next, at 350 ° C. for 15 minutes in a nitrogen atmosphere,
Heat treatment is performed. By the heat treatment, the vicinity of the interface between the collector contact layer 2 and the collector electrode 9 is alloyed, and an ohmic contact between the collector electrode 9 and the collector contact layer 2 can be obtained. At the same time, an electrode reaction region 20 extending from the base electrode 10 to the base layer 4 is formed, and an ohmic contact between the base electrode 10 and the base layer 4 can be obtained.

In order to make ohmic contact between the base electrode 10 and the base layer 4, AuZn, AuB
e, AuMn, AuMg, etc.
At about 350 ° C., the reaction between Au and GaAs progresses rapidly, and passes through the base layer 4 having a thickness of about 100 nm. When the electrode reaction region 20 reaches the collector layer 3, it causes a decrease in the collector breakdown voltage. This problem can be solved by using Pd for the lower layer of the base layer 4. Note that it is preferable to use a material such as Pd or Pt that is thick enough that Au in the uppermost layer does not react with the semiconductor even after the heat treatment. Even if AuBe, AuZn, or AuMn is used, the thickness may be sufficiently small so that the reaction does not pass through the base layer even when the heat treatment is performed.

Also in the HBT according to the second embodiment shown in FIG. 3, the surface of the base layer 4 between the base electrode 10 and the emitter mesa 30 is covered by the guard ring 12 composed of the emitter layer 5. The surface of the emitter layer 5 is covered with an AlGaAs emitter protection layer 6,
The nGaP emitter layer 5 does not directly contact the SiN film. Further, the emitter protective layer and the emitter layer are completely depleted below the sidewall insulating film. Therefore, the same effect as that of the first embodiment shown in FIG. 1 can be obtained.

When an HBT having the structure shown in FIG. 3 was actually manufactured, the withstand voltage of the base collector was 15 V or more, and a sufficient withstand voltage was obtained. Also, no leakage current through the guard ring between the emitter and the base was observed. It can be seen that the guard ring portion is completely depleted even when the bias voltage is applied.

Next, with reference to FIG. 5, a result of a life test of the HBT manufactured according to the embodiment shown in FIG. 3 will be described. FIG. 5 shows the change over time in the current gain of the HBT. The horizontal axis represents the elapsed time from the start of energization, and the vertical axis represents
Indicates current gain. The solid lines p1 and p2 are 150
HB having the structure shown in FIG.
5 shows a change with time of the current gain of T. For comparison, I
The dotted lines q1 and q2 show the temporal changes of the current gain of the HBT having the structure in which the nGaP emitter layer 5 is replaced with AlGaAs at 150 ° C. and 200 ° C., respectively. The emitter current density was measured at 6 × 10 ⁴ A / cm ² .

HB using AlGaAs for the emitter layer
At T, as shown by the dotted lines q1 and q2, the current gain continues to decrease after the start of energization, and further decreases by 100 to 200.
At the time point when the time had elapsed, the current gain dropped sharply, and the device became inoperable. If the life at normal temperature operation is estimated from these conditions, the life will be less than about 2 years even if there is no sharp decrease in current gain.

On the other hand, in the case of an HBT using InGaP for the emitter layer, at 200.degree.
At 00 hours and 150 ° C., the current gain hardly decreased even after about 1200 hours. Estimating the life at normal temperature operation from this test result will be at least several years, and longer than several tens of years. As described above, the InGaP
When the surface is passivated by using Al, the life of the device can be significantly improved as compared with the case where AlGaAs is used.

Although the case where the emitter protective layer is used as the etching stop layer has been described, the etching may be controlled by time or the like. The emitter protective layer is made of GaAs if it covers the exposed surface of the emitter layer and can be inactivated.
It is not limited to AlGaAs or AlGaAs. Semiconductors having such properties include III-V group and IV group semiconductors. However, it is preferable that In be not contained in the composition. For example, GaP, GaAsP, Si and the like can be considered. Even if they are not lattice-matched with the upper and lower semiconductors, they can be manufactured if they are sufficiently thin.

In the current path, the emitter protection layer is
This causes band discontinuity such as a potential barrier. For this reason, the thickness is set within a range in which the carrier can be transported by a tunnel or the like. Preferably, the thickness is 50 nm or less. However, this does not apply when the band discontinuity ΔEc is sufficiently small and does not hinder the current, or when the bands are smoothly connected.

Next, a modification of the second embodiment will be described with reference to FIG. FIG. 6 shows a cross-sectional view of an HBT according to a modification of the second embodiment. The HBT according to this modification is
The difference from the HBT according to the second embodiment shown in FIG. 3 is that the emitter protection layer 6 in the region where the base electrode 10 is formed is not removed and is left. Other configurations are the same as those of the second embodiment shown in FIG.

As shown in FIG. 6, the base electrode 10 is formed on the emitter protection layer 6. An electrode reaction region 20 extends from the base electrode 10 through the emitter protection layer 6 and the emitter layer 5 to the surface of the base layer 4. Is formed. Such a structure is obtained by forming the side wall 13 in the step shown in FIG.
Before etching the s emitter protection layer 6, Pd / Zn /
It can be formed by depositing a Pt / Au layer.

Also in this modification, since the surface of the InGaP emitter layer 5 is covered with the AlGaAs emitter protective layer 6, the problem of the leakage current flowing on the surface of the InGaP emitter layer 5 does not occur.

In the structure shown in FIG. 6, the base electrode 1
0 is connected to the emitter layer 7 through the AlGaAs emitter protection layer 6,
Since the GaAs emitter protective layer 6 is extremely thin, about 30 nm, the entire thickness is depleted. 3, the entire thickness of the InGaP emitter layer 5 in the guard ring 12 is also depleted. Therefore, the AlGaAs emitter protective layer 6 or the InGaAs
No current flows through the GaP emitter layer 5 directly to the emitter.

3 to 6, one HBT formed on the substrate has been described. However, when a plurality of semiconductor elements are formed on the same substrate to form an IC, for example, proton (H ⁺ The device isolation can be performed by ion-implanting ()).

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 7 shows an HB according to the third embodiment.
1 shows a sectional view of T. In the modification of the second embodiment shown in FIG. 6, the AlGaAs emitter protection layer 6 is
Also functioned as an etching stop layer for forming a layer and a protective layer for the InGaP emitter layer 5. The present embodiment is different from the first embodiment in that an AlGaAs etching stop layer 6a for stopping the etching and a GaAs emitter protection layer 6b for protecting the InGaP emitter layer 5 are separated to form a two-layer structure.

The first embodiment shown in FIG. 1 and the second embodiment shown in FIG.
In this embodiment, the base electrode is formed in a self-aligned manner by utilizing the eaves of the side wall and the emitter electrode. In the present embodiment, the base electrode is positioned by ordinary mask alignment.

The emitter mesa is formed by stacking the AlGaAs etching stop layer 6a, the GaAs emitter layer 7, the emitter cap layer 8 composed of two layers of GaAs and InGaAs, and the emitter electrode 11 in this order from the bottom. . Other configurations are the same as those of the modification of the second embodiment shown in FIG. FIG. 7 also shows an interlayer insulating film 21 formed so as to cover the HBT, a wiring 22 formed on the interlayer insulating film 21, and an element isolation region 23.

Next, a method of manufacturing the HBT according to the third embodiment will be described with reference to FIGS. 8A to 8D. FIG. 8A
As shown in FIG. 1, an n ⁺ type G is formed on a semi-insulating GaAs substrate 1.
aAs collector contact layer 2, n-type GaAs collector layer 3, p ⁺ -type GaAs base layer 4, n-type InGaP emitter layer 5, n-type GaAs emitter protective layer 6b, n-type Al
The GaAs etching stop layer 6a, the n-type GaAs emitter layer 7, and the n ⁺ -type GaAs / InGaAs emitter cap layer 8 are sequentially placed in the gas source MBE or MOCVD.
Epitaxial growth.

Impurities in GaAs collector contact layer 2
The concentration is 5 × 10¹⁸cm^-3, And the film thickness is 500 nm. G
The impurity concentration of the aAs collector layer 3 is 3 × 10¹⁶cm^-3,
The thickness is 500 nm. Impurity of GaAs base layer 4
The concentration is 4 × 10¹⁹cm^-3, And the film thickness is 100 nm. I
The impurity concentration of the nGaP emitter layer 5 is 4 × 10¹⁷c
m ^-3, And the film thickness is 40 nm.

The GaAs emitter protective layer 6b has an impurity concentration of 4 × 10 ¹⁷ cm ^-3 and a thickness of 4 nm. AlGaAs
The impurity concentration of the s etching stop layer 6a is 4 × 10 ¹⁷ cm
^-3 , the film thickness is 4 nm. The impurity concentration of the GaAs emitter layer 7 is 4 × 10 ¹⁷ cm ⁻³ , and the thickness is 100 nm.

The GaAs / InGaAs emitter cap layer 8 is composed of a lower GaAs layer and an upper InGaAs layer.
It is composed of layers. The lower GaAs layer has an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 100 nm. The upper InGaAs layer has a composition of In _0.6 Ga _0.4 As,
The impurity concentration is 3 × 10 ¹⁹ cm ⁻³ and the film thickness is 50 nm.

FIG. 8B shows a step of forming the emitter mesa 30. First, an emitter electrode 11 made of WSi is formed in the emitter region on the surface of the emitter cap layer 8 by photolithography. Using the emitter electrode 11 as a mask, the InGaAs emitter cap layer 8 is etched by wet etching in the same manner as the step shown in FIG. 2A, and then the GaAs emitter layer 7 is dry-etched. Etching is performed using an AlGaAs etching stop layer 6a.
Stops automatically when the surface is exposed.

Subsequently, the AlGaAs etching stop layer 6
Etch a to expose the GaAs emitter surface. Thus, the emitter mesa 30 is formed. FIG.
As shown in C, a surface protection film 13a such as SiO ₂ is deposited on the entire surface of the substrate so as to cover the emitter mesa 30.

As shown in FIG. 8D, an opening is formed in the base electrode region of the surface protection film 13a by using a resist pattern having an opening in the base electrode region as a mask to expose the surface of the GaAs emitter protection layer 6b. Then, P
A d / Zn / Pt / Au layer is deposited, and a base electrode 10 is formed by lift-off.

After the formation of the base electrode 10, the collector electrode 9 is formed by the same steps as the steps after the formation of the base electrode shown in FIG. 4D. Thereafter, an interlayer insulating film 21 is deposited on the entire surface of the substrate, and contact holes are formed in the emitter electrode, base electrode, and collector electrode portions. Next, the wiring 22 is formed on the interlayer insulating film 21 by plating or vapor deposition.

The element isolation region 23 is formed, for example, by ion-implanting protons into a predetermined region. 7 and 8A to 8D, in order to obtain ohmic contact between the base electrode and the base layer, Pd / Zn / Pt /
Although the case where the Au alloy electrode is used has been described,
Ohmic contact may be made by diffusing Zn or the like or implanting Be or the like into the electrode reaction region 20. FIG.
As shown in (1), the GaAs emitter protective layer 6b and the InGaP emitter layer 5 in the base electrode formation region may be removed, and the base electrode 10 may be formed directly on the base layer 4.

Next, a modification of the third embodiment will be described with reference to FIG. FIG. 9 is a sectional view of an emitter mesa portion of an HBT according to a modification of the third embodiment. In the HBT according to the present modification, the emitter mesa 30 is made of InGaP second
Emitter layer 7, AlGaAs etching stop layer 6c, G
The third embodiment is different from the third embodiment shown in FIG. 7 in that the emitter cap layer 8 and the emitter electrode 11 are formed by laminating two layers of aAs and InGaAs.

The InGaP second emitter layer 7 has an impurity concentration of 4 × 10 ¹⁷ cm ⁻³ and a thickness of 40 nm. AlGa
The As etching stop layer 6c is a composition gradient layer having a composition of Al _x Ga _1-x As, where x is 0.3 at the lowermost surface and x is 0 at the uppermost surface. The impurity concentration is 4 × 10 ¹⁷ c
m ^-3 and the film thickness is 30 nm.

The lower GaAs layer of the emitter cap layer 8 has an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 100 nm. The upper InGaAs layer has a composition of In _0.6 Ga _0.4 As. 3 × 10 ¹⁹ cm ^-3 , thickness 5
0 nm.

Next, a method of manufacturing the HBT according to the present modification will be described. The process of forming the emitter mesa shown in FIG. 8B is different from that of the third embodiment, and the other processes are the same. Hereinafter, only the step of forming the emitter mesa will be described.

First, the InGaAs layer on the emitter cap layer 8 is wet-etched using the emitter electrode 11 formed on the emitter cap layer 8 as a mask.
Next, the GaAs layer below the emitter cap layer 8 is selectively dry-etched. Subsequently, the AlGaAs etching stop layer 6c is selectively wet-etched to form InGaP.
The surface of the emitter layer 7 is exposed. Further, the InGaP emitter layer 7 is selectively wet-etched to expose the surface of the GaAs emitter protection layer 6b.

In these selective etchings, since the layer below the layer to be etched is not etched, the etching automatically stops when the surface of the lower layer is exposed. GaAs
After exposing the surface of the emitter protection layer 6b, an HBT is manufactured by the same steps as those in FIG. 8C and thereafter of the third embodiment.

According to this modification, the emitter cap layer 8 can be formed by dry etching while suppressing damage in the guard ring due to dry etching. Since dry etching has higher anisotropy than ordinary wet etching, the cross-sectional shape of the emitter mesa can be formed with good controllability. As a result, it is possible to reduce variations in element characteristics.

The AlGaAs etching stop layer 6c
Is a composition gradient layer, the effect of spikes in the conduction band can be reduced. In the second and third embodiments, the case where the Pd / Zn / Pt / Au layer is used as the base electrode has been described, but other non-gold-based electrodes containing no gold in the lowermost layer may be used. For example, Pt / Ti /
An electrode having a laminated structure such as Pt / Au, Ti / Pt, or Ti / Pt / Au may be used. AuZn, AuB
e, AuMn, etc., or AuZn /
It may be Pt / Au, AuMn / Mn / Au, or the like.

In the second and third embodiments, the case where the electrode reaction region extends from the base electrode to the base layer through the emitter layer below the base electrode has been described. It does not need to be in contact. For example, even when the reaction stops in the middle of the InGaP emitter layer and the electrode reaction region and the base layer surface are not directly connected, the distance between the lower surface of the electrode reaction region and the upper surface of the base layer is determined by holes. It is sufficient that the interval is such that a tunnel current flows.

In the first to third embodiments, the case where InGaP is used as the emitter layer has been described.
Other mixed crystal semiconductors containing In, Ga, and P may be used. For example, InP / InGaAs is used as an emitter / base, InAlAs is used as a protective layer, and InGaAs is used as a second emitter.
As may be used.

Also, InGaAs lattice-matched to the base layer
sP or InGaAlP may be used. In any case, the thickness and concentration of each of the emitter protective layer and the emitter are selected so that the emitter is completely depleted even when biased by the depletion layer extending from the base and the depletion layer extending from the insulating film. .

In the above embodiment, the emitter-up type HBT has been described.
A similar structure can be adopted for T. Furthermore, not only npn type transistors but also pnp type transistors are used.
It can also be applied to transistors of the type.

The total thickness of the single layer or the plurality of layers which serve both as the etching stop and the emitter protection is about 50 n.
m or less is preferable from the electrical characteristics. In the case of a layer having a uniform composition without using the composition gradient layer, the total thickness is about 10 n.
m or less.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0096]

As described above, according to the present invention,
Without causing a decrease in current gain, H
BT can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of an HBT according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a main part of the HBT for illustrating a manufacturing process of the HBT according to the first embodiment of the present invention.

FIG. 3 is a sectional view of an HBT according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a main part of an HBT for illustrating a manufacturing process of the HBT according to a second embodiment of the present invention.

FIG. 5 is a graph showing a change over time in a current gain of an HBT according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of an HBT according to a modification of the second embodiment of the present invention.

FIG. 7 is a sectional view of an HBT according to a third embodiment of the present invention.

FIG. 8 is a sectional view of a main part of an HBT for illustrating a manufacturing process of the HBT according to a third embodiment of the present invention.

FIG. 9 is a sectional view of an HBT according to a modification of the third embodiment of the present invention.

FIG. 10 is a sectional view of a conventional HBT.

[Explanation of symbols]

Reference Signs List 1, 20 GaAs substrate 2 GaAs collector contact layer 3, 21 GaAs collector layer 4 GaAs base layer 5 Emitter layer 6a, 6c GaAs etching stop layer 6, 6b Emitter protection layer 7 Emitter layer 8 Emitter cap layer 9 Collector electrode 10 Base electrode 11 Emitter electrode 12 Guard ring 13 Side wall 13a Surface protective film 20 Electrode reaction region 21 Interlayer insulating film 22 Wiring 23 Element isolation region 30 Emitter mesa 52 p-type GaAs base layer 53, 53a, 53b, 53cn n-type AlGaAs emitter layer 54 SiO ₂ side Wall 55 Collector electrode 56 Base electrode 57 Emitter electrode 58 Guard ring 59, 60 Etch stop layer 61 n-type GaAs emitter cap layer 62 Base to ohmic reaction layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-52483 (JP, A) JP-A-62-162358 (JP, A) JP-A-61-162257 (JP, A) JP-A-61-162257 99375 (JP, A) JP-A-5-243256 (JP, A) JP-A-5-36713 (JP, A) JP-A-4-288838 (JP, A) JP-A-4-286126 (JP, A) JP-A-3-53563 (JP, A) JP-A-3-44938 (JP, A) JP-A-2-194652 (JP, A) JP-A-2-188964 (JP, A) JP-A-1-1611862 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/331 H01L 29/205 H01L 29/737

Claims (29)

(57) [Claims] 1. A support substrate, a collector layer made of a group III-V compound semiconductor formed on the support substrate, and a group III-V compound formed on the collector layer and containing arsenic as a group V element A base layer made of a semiconductor, a first emitter layer formed on the base layer, made of a III-V compound semiconductor containing phosphorus as a group V element, and having a wider band gap than the base layer; An emitter protection layer formed on the first emitter layer and made of a semiconductor having a function of passivating the surface of the first emitter layer ; and
An electrical connection with the first emitter layer through a mitter protection layer.
III-V compound containing phosphorus as group V element
A hetero-bipolar semiconductor device having a second emitter layer made of a semiconductor and a base electrode in ohmic contact with the base layer, wherein an upper surface of the first emitter layer is formed by the emitter protection layer or the emitter protection layer And the base electrode is substantially entirely covered with the first emitter layer, and the first emitter layer is in contact with the base electrode, and a region of the first emitter layer near an end of the base electrode is A hetero-bipolar semiconductor device whose total thickness is depleted. 2. The hetero-bipolar semiconductor device according to claim 1, wherein said emitter protection layer is formed of a III-V compound semiconductor containing arsenic as a V element. 3. The semiconductor device according to claim 1, further comprising an emitter cap layer formed on the second emitter layer and made of a III-V compound semiconductor having an impurity concentration higher than that of the second emitter layer. Heterobipolar semiconductor device. 4. The hetero-bipolar semiconductor device according to claim 3, wherein said base electrode is formed directly on a surface of said base layer. 5. The semiconductor device according to claim 1, further comprising: a sidewall formed on a side surface of the second emitter layer and the emitter cap layer, the sidewall being made of an insulating material and having a position of an outer peripheral surface coinciding with an end of the emitter protection layer. 5. The heterobipolar semiconductor device according to item 4. 6. The hetero-bipolar semiconductor device according to claim 3, wherein said base electrode is formed on said first emitter layer, and is in ohmic contact with said base layer via said first emitter layer. 7. An alloyed region containing palladium or platinum for electrically connecting the base electrode and the base layer is formed in a region of the first emitter layer where the base electrode is formed. 7. The hetero-bipolar semiconductor device according to claim 6, wherein the semiconductor device is formed. 8. A region of the first emitter layer where the base electrode is formed, in order to electrically connect the base electrode and the base layer, zinc, beryllium, carbon, magnesium, and manganese are used. 7. The hetero-bipolar semiconductor device according to claim 6, wherein a region doped with at least one kind is formed. 9. The hetero-bipolar type according to claim 3, wherein the base electrode is formed on the emitter protection layer, and is in ohmic contact with the base layer via the emitter protection layer and the first emitter layer. Semiconductor device. 10. An alloy containing palladium or platinum for electrically connecting the base electrode to the base layer in a region of the first emitter layer and the emitter protection layer where the base electrode is formed. The hetero-bipolar semiconductor device according to claim 9, wherein an oxidized region is formed. 11. A region in which the base electrode of the first emitter layer and the emitter protection layer is formed, wherein zinc, beryllium, carbon, and the like are used to electrically connect the base electrode and the base layer. 10. The hetero-bipolar semiconductor device according to claim 9, wherein a region doped with at least one of magnesium, manganese and manganese is formed. 12. An emitter electrode formed on the emitter cap layer, protruding slightly outward from an end of the second emitter layer, and having an etching resistance different from that of the second emitter layer and the emitter cap layer. 7. An end of the base electrode on the side of the second emitter layer has an in-plane position coincident with an end of the emitter electrode.
12. The hetero-bipolar semiconductor device according to any one of items 1 to 11. 13. An end portion of the second emitter layer and an end portion of the base electrode on a side surface of the emitter electrode, the emitter cap layer and the second emitter layer, and a surface of the emitter protection layer. 13. The semiconductor device according to claim 12, further comprising: a side wall formed of an insulating material formed in the interposed region.
The heterobipolar semiconductor device according to claim 1. 14. The hetero-bipolar semiconductor device according to claim 3, wherein said emitter protection layer and said second emitter layer have different etching resistances. 15. The semiconductor device according to claim 15, wherein the first emitter layer further comprises
15. The hetero-bipolar semiconductor device according to claim 14, comprising at least In and Ga as a group element. 16. The hetero-bipolar semiconductor device according to claim 15, wherein said first emitter layer is made of InGaP. 17. The method according to claim 17, wherein the first emitter layer is made of InGaAs.
16. The hetero-bipolar semiconductor device according to claim 15, which is P or InGaAlP. 18. The second emitter layer contains In and Ga as Group III elements, and the emitter protection layer
The heterobipolar semiconductor device according to claim 14, wherein the device is aAs or AlGaAs. 19. The heterostructure according to claim 14, further comprising an etching stop layer formed between the second emitter layer and the emitter cap layer and having an etching resistance different from that of the second emitter layer and the emitter cap layer. Bipolar semiconductor device. 20. The emitter cap layer includes at least GaAs, and the etching stop layer includes AlGaAs.
20. The heterobipolar semiconductor device according to claim 19, wherein s. 21. A support substrate, a collector layer made of a group III-V compound semiconductor formed on the support substrate, and a group III-V compound formed on the collector layer and containing arsenic as a group V element A base layer made of a semiconductor, a first emitter layer formed on the base layer, made of a III-V compound semiconductor containing phosphorus as a group V element, and having a wider band gap than the base layer; An emitter protection layer formed on the first emitter layer and made of a semiconductor having a function of passivating the surface of the first emitter layer; formed on the emitter protection layer via at least the emitter protection layer A second emitter layer electrically coupled to the first emitter layer and made of a III-V compound semiconductor containing phosphorus as a group V element; A hetero-bipolar semiconductor device, comprising: an emitter cap layer formed of a III-V compound semiconductor having a higher impurity concentration than the second emitter layer; and a base electrode in ohmic contact with the base layer. An upper surface of the first emitter layer is substantially entirely covered by the emitter protection layer or the emitter protection layer and the base electrode, and the first emitter layer is in contact with the base electrode. In the first emitter layer, the region near the end of the base electrode is depleted in its entire thickness, and the emitter protective layer and the second emitter layer have the same etching resistance. An edge having an etching resistance different from that of the emitter protective layer and the second emitter layer is provided between the emitter protective layer and the second emitter layer. A hetero-bipolar semiconductor device having a stopping layer. 22. The hetero-bipolar semiconductor device according to claim 21, wherein said first emitter layer further contains In and Ga as at least a group III element. 23. The first emitter layer is made of InGaP,
3. InGaAsP or InGaAlP.
3. The heterobipolar semiconductor device according to item 2. 24. The second emitter layer and the emitter protection layer are made of GaAs, and the etching stop layer is made of A
24. The hetero-bipolar semiconductor device according to claim 21, which is made of lGaAs. 25. III-V containing arsenic as a group V element
A base layer made of a group III compound semiconductor, a first emitter layer made of a group III-V compound semiconductor containing phosphorus as a group V element, an emitter protective layer made of a group III-V compound semiconductor containing arsenic as a group V element, a group V element Preparing a semiconductor substrate having a multilayer structure including a second emitter layer made of a group III-V compound semiconductor containing phosphorus in this order, and partially etching the second emitter layer to form an emitter protection layer. Stopping etching at the surface to form a mesa; forming an insulator sidewall on the side surface of the mesa of the second emitter layer; and etching the emitter protection layer using the sidewall as a mask. A step of partially etching the first emitter layer using the sidewalls and the emitter protection layer as a mask; A step of exposing a surface of the base layer; a step of forming a conductive film over the entire surface of the substrate; and a step of removing the conductive film formed on a side surface of the sidewall. Device manufacturing method. 26. III-V containing arsenic as a group V element
A base layer made of a group III compound semiconductor, a first emitter layer made of a group III-V compound semiconductor containing phosphorus as a group V element, an emitter protection layer made of a group III-V compound semiconductor containing arsenic as a group V element, and said emitter protection III , which differs from the layer in etching resistance and contains phosphorus as a group V element
Preparing a semiconductor substrate having a multilayer structure including, in this order, a second emitter layer made of a -V group compound semiconductor, an emitter protective layer and an emitter electrode layer having etching resistance different from that of the second emitter layer; Forming an emitter electrode by partially etching the emitter electrode layer; using the emitter electrode as a mask, etching the second emitter layer to expose the surface of the emitter protection layer; Side-etch
Forming an eaves-like portion in which an end of the emitter electrode projects from an end of the second emitter layer; and isotropically forming an exposed surface of the emitter electrode, the second emitter layer, and the emitter protection layer. Forming an insulating film; and performing anisotropic etching on the insulating film to form a side surface and a partial lower surface of the emitter electrode, a side surface of the second emitter layer, and a surface of the emitter protection layer. Leaving a sidewall in a shadowed region; etching the emitter protective layer using the sidewall as a mask to expose a surface of the first emitter layer; Forming a conductive film; and performing heat treatment to alloy the first emitter layer in a region where the conductive film is formed, thereby forming an ohmic contact between the conductive film and the base layer. Method for producing a hetero bipolar semiconductor device including a step of contacting. 27. III-V containing arsenic as a group V element
A base layer made of a group III compound semiconductor, a first emitter layer made of a group III-V compound semiconductor containing phosphorus as a group V element, an emitter protection layer made of a group III-V compound semiconductor containing arsenic as a group V element, and said emitter protection III , which differs from the layer in etching resistance and contains phosphorus as a group V element
Preparing a semiconductor substrate having a multilayer structure including, in this order, a second emitter layer made of a -V group compound semiconductor, an emitter protective layer and an emitter electrode layer having etching resistance different from that of the second emitter layer; Forming an emitter electrode by partially etching the emitter electrode layer; using the emitter electrode as a mask, etching the second emitter layer to expose the surface of the emitter protection layer; Side-etch
Forming an eaves-like portion in which an end of the emitter electrode projects from an end of the second emitter layer; and isotropically forming an exposed surface of the emitter electrode, the second emitter layer, and the emitter protection layer. Forming an insulating film; and performing anisotropic etching on the insulating film to form a side surface and a partial lower surface of the emitter electrode, a side surface of the second emitter layer, and a surface of the emitter protection layer. Leaving a sidewall in a shadowed region, forming a conductive film on the exposed surface of the emitter protection layer, performing a heat treatment, and forming the conductive film and the emitter protection layer in the region where the conductive film is formed. Alloying a first emitter layer to make ohmic contact between the conductive film and the base layer. 28. III-V containing arsenic as a group V element
A base layer made of a group III compound semiconductor, a first emitter layer made of a group III-V compound semiconductor containing phosphorus as a group V element, an emitter protection layer made of a group III-V compound semiconductor containing arsenic as a group V element, and said emitter protection A semiconductor substrate having a multilayer structure including, in this order, an etching stop layer made of a III-V compound semiconductor having a different etching resistance from a layer, and a second emitter layer made of a III-V compound semiconductor having a different etching resistance from the etching stop layer. Providing a step of: partially etching the second emitter layer to stop etching at the surface of the etching stop layer; and partially etching the etching stop layer using the second emitter layer as a mask. Stopping the etching on the surface of the emitter protection layer; Forming an insulating film over the entire exposed surface; forming an opening in the base electrode forming region of the insulating film by photolithography to expose the emitter protective layer surface; and exposing the emitter protective layer surface Forming a base electrode on the substrate; performing a heat treatment to alloy the emitter protective layer and the first emitter layer in a region where the base electrode is formed; and bringing the base electrode and the base layer into ohmic contact. A method for manufacturing a hetero-bipolar semiconductor device including: 29. III-V containing arsenic as a group V element
A base layer made of a group III compound semiconductor, a first emitter layer made of a group III-V compound semiconductor containing phosphorus as a group V element, an emitter protection layer made of a group III-V compound semiconductor containing arsenic as a group V element, and said emitter protection A second emitter layer made of a III-V compound semiconductor having a different etching resistance from the layer, an etching stop layer made of a III-V compound semiconductor having a different etching resistance from the second emitter layer, and having a different etching resistance from the etching stop layer. A step of preparing a semiconductor substrate having a multilayer structure including an emitter cap layer composed of a III-V compound semiconductor in this order; and partially etching the emitter cap layer dry to stop etching at the surface of the etching stop layer. Using the emitter cap layer as a mask. Partially etching the etching stopper layer to stop etching at the surface of the second emitter layer; and partially etching the second emitter layer using the etching stopper layer as a mask to form the emitter protective layer. Stopping etching at the surface; forming an insulating film on the entire exposed surface of the semiconductor substrate; forming an opening in a base electrode formation region of the insulating film by photolithography; Exposing; forming a base electrode on the exposed surface of the emitter protection layer; performing heat treatment to alloy the emitter protection layer and the first emitter layer in a region where the base electrode is formed; A method of manufacturing a hetero-bipolar semiconductor device, comprising: a step of making a base electrode and the base layer in ohmic contact.