JP2005294804A - Hetero-junction bipolar transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an excellent contact property at each electrode as well as reduction in manufacturing cost for hetero-junction bipolar transistors. <P>SOLUTION: A manufacturing method of a hetero-junction bipolar transistor comprises the steps of: forming a high concentration n-type second sub-collector layer 108 that is made of small band gap materials, an i-type or a low concentration n-type collector layer 103, a high concentration p-type base layer 104, an n-type emitter layer 105 that is made of large band gap materials, a high concentration n-type emitter cap layer 106, and a high concentration n-type emitter contact layer 107 that is made of small band gap materials on a first sub-collector layer 102 of an high concentration n-type in this order. Wherein an alloying reaction layers 114-116 are formed below an emitter electrode 111, a base electrode 112, and collector electrode 113, respectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a heterojunction bipolar transistor widely used in a transmission high output power amplifier and the like, and a method of manufacturing the same.

  In recent years, with higher functionality and higher capacity communication of mobile phones, higher performance is also required for high-frequency analog elements used in mobile phones. Among high-frequency analog elements, a heterojunction bipolar transistor (hereinafter referred to as HBT) has already been put into practical use as a transmission high-power amplifier. In order to improve the performance of the HBT, it is necessary to reduce parasitic element effects, that is, parasitic resistance and parasitic capacitance. This parasitic resistance is roughly divided into an emitter resistance, a base resistance, and a collector resistance. In order to reduce the contact resistance, an HBT using an alloying reaction layer as an ohmic electrode has been proposed.

  Hereinafter, a conventional HBT structure and manufacturing method using an alloying reaction layer as an ohmic electrode and a manufacturing method (for example, see Patent Document 1) will be described with reference to FIG.

  FIG. 7 is a diagram showing a schematic cross-sectional structure of a conventional HBT using an alloying reaction layer as an ohmic electrode. As shown in FIG. 7, a subcollector layer 202 made of a high-concentration n-type GaAs layer is formed on a semi-insulating substrate 201 made of GaAs. A collector layer 203 made of a low-concentration n-type GaAs layer, a base layer 204 made of a high-concentration p-type GaAs layer, and an emitter layer 205 made of an n-type AlGaAs layer are formed on the collector formation region in the subcollector layer 202. . Here, a predetermined portion of the emitter layer 205 is formed to be thinner than the other portions, and the predetermined portion becomes the base protective layer 205a. An emitter cap layer 206 made of a high-concentration n-type GaAs layer and an emitter contact layer 207 made of a high-concentration n-type InGaAs layer are formed on a region of the emitter layer 205 other than the base protective layer 205a.

  Further, as shown in FIG. 7, on the emitter contact layer 207, an emitter electrode having a Pt / Ti / Pt / Au structure (a structure in which a Pt layer, a Ti layer, a Pt layer, and an Au layer are stacked in order from the bottom). 211 is formed. A base electrode 212 having a Pt / Ti / Pt / Au structure is formed on the base protective layer 205a which is an n-type AlGaAs layer. In addition, a collector electrode 213 having an AuGe / Ni / Au structure (a structure in which an AuGe layer, a Ni layer, and an Au layer are stacked in order from the bottom) is formed on a region other than the collector formation region in the subcollector layer 202. Is formed.

  In addition, as shown in FIG. 7, a first Pt alloying reaction layer 214 is formed on the emitter contact layer 207 below the emitter electrode 211, and below the base electrode 212 in the base protective layer 205a. A second Pt alloying reaction layer 215 is formed on the side portion. The first Pt alloying reaction layer 214 and the second Pt alloying reaction layer 215 are formed by reacting an electrode material (specifically, Pt constituting the lowermost layer) and a semiconductor material by heat treatment. is there. The second Pt alloying reaction layer 215 extends through the base protective layer 205a to the upper part of the base layer 204.

  In the conventional HBT shown in FIG. 7, the base protective layer 205a prevents carrier recombination on the surface of the base layer 204, thereby suppressing a decrease in current gain. However, since the base protective layer 205a covers the surface of the base layer 204, the base electrode 212 and the base layer 204 cannot be brought into direct contact with each other. Therefore, by forming a second Pt alloying reaction layer 215 that penetrates the base protective layer 205a under the base electrode 212 by heat treatment, the base electrode 212 and the base electrode 212 are interposed via the second Pt alloying reaction layer 215. An ohmic contact is obtained by contacting the base layer 204. On the other hand, the first Pt alloying reaction layer 214 below the emitter electrode 211 is formed only inside the emitter contact layer 207.

As described above, in the conventional HBT, by forming the Pt alloying reaction layers 214 and 215, the width of the potential barrier at the junction between the emitter contact layer 207 and the first Pt alloying reaction layer 214 is narrowed. In addition, the width of the potential barrier at the junction between the base layer 204 and the second Pt alloying reaction layer 215 can be reduced. In this way, a good ohmic characteristic can be obtained due to the tunneling effect of carriers, so that the contact resistance at each of the emitter and the base can be reduced, thereby reducing the emitter resistance and the base resistance.
JP 2001-308103 A

  However, in the conventional HBT shown in FIG. 7, the emitter electrode 211 and the base electrode 212 have a Pt / Ti / Pt / Au structure, whereas the collector electrode 213 has an AuGe / Ni / Au structure. The following problems arise.

  That is, all of the emitter electrode 211, the base electrode 212, and the collector electrode 213 cannot be formed simultaneously. In other words, the step of simultaneously forming the emitter electrode 211 and the base electrode 212 and the step of forming the collector electrode 213 must be performed separately. Specifically, in each electrode formation step, a resist formation for forming a photoresist having a pattern corresponding to the electrode shape, a metal thin film formation for forming a metal thin film using vapor deposition or sputtering, and a photoresist It is necessary to perform lift-off to remove the metal thin film only at a necessary portion by removing the metal thin film. Therefore, the conventional HBT has a problem that the manufacturing cost increases as the number of manufacturing steps increases.

  In the conventional HBT, the optimum heat treatment condition for the emitter electrode 211 and the base electrode 212 having the Pt / Ti / Pt / Au structure is different from the optimum heat treatment condition for the collector electrode 213 having the AuGe / Ni / Au structure. There is a problem of end. Hereinafter, it demonstrates concretely, referring drawings. FIG. 8A shows the heat treatment time dependence at 390 ° C. of the contact resistivity of an electrode having an AuGe / Ni / Au structure formed on GaAs, and FIG. 8B is formed on GaAs. The dependence of the contact resistivity of the electrode having the Pt / Ti / Pt / Au structure on the heat treatment time at 390 ° C. is shown. As shown in FIGS. 8A and 8B, the contact resistivity of the AuGe / Ni / Au electrode on GaAs gradually increases after 60 seconds, whereas Pt / Ti on GaAs. The contact resistivity of the / Pt / Au electrode is so high that sufficient ohmic characteristics cannot be obtained if it is less than 90 seconds. Therefore, when the heat treatment conditions for each electrode are matched with the optimum heat treatment conditions for the emitter electrode 211 and the base electrode 212 having the Pt / Ti / Pt / Au structure, the ohmic of the collector electrode 213 having the AuGe / Ni / Au structure is used. There arises a problem that the characteristics deteriorate. Further, when the heat treatment condition for each electrode is matched with the optimum heat treatment condition for the collector electrode 213, there arises a problem that sufficient ohmic characteristics cannot be obtained in the emitter electrode 211 and the base electrode 212.

  In view of the above, an object of the present invention is to provide an HBT that can reduce the manufacturing cost and that can realize good contact characteristics in all the electrodes, and a manufacturing method thereof.

  In order to achieve the above object, a first HBT according to the present invention is formed on a high-concentration n-type first subcollector layer and a first subcollector layer, and has a band higher than that of the first subcollector layer. A high-concentration n-type second subcollector layer made of a material having a small gap, an i-type or low-concentration n-type collector layer formed on a predetermined portion of the second subcollector layer, and a collector layer A high-concentration p-type base layer, an n-type emitter layer formed on the base layer and made of a material having a larger band gap than the base layer, and a high level formed on a predetermined portion of the emitter layer An n-type emitter cap layer; a high-concentration n-type emitter contact layer formed on the emitter cap layer and made of a material having a smaller band gap than the emitter cap layer; An emitter electrode made of one or more conductive layers and a base made of one or more conductive layers on the portion of the emitter layer where the emitter cap layer is not formed A portion of the second sub-collector layer formed on the portion of the second sub-collector layer where the collector layer is not formed, and a collector electrode made of one or a plurality of conductive layers. A first alloying reaction layer is formed, a second alloying reaction layer is formed in a lower part of the base electrode in the emitter layer, and a lower part of the collector electrode in the second subcollector layer is formed. A third alloying reaction layer is formed in the portion.

  The second HBT according to the present invention is a high-concentration n-type first subcollector layer and a high-concentration material formed on the first subcollector layer and made of a material having a smaller band gap than the first subcollector layer. An n-type second subcollector layer, an i-type or low-concentration n-type collector layer formed on a predetermined portion of the second subcollector layer, and a high-concentration p-type formed on the collector layer A base layer; an n-type emitter layer formed on a predetermined portion of the base layer and made of a material having a larger band gap than the base layer; and a high-concentration n-type emitter cap layer formed on the emitter layer A high-concentration n-type emitter contact layer formed on the emitter cap layer and made of a material having a smaller band gap than the emitter cap layer, and an emitter contact layer, An emitter electrode made of one or more conductive layers, a base electrode made of one or more conductive layers formed on a portion of the base layer where the emitter layer is not formed, and a second subcollector layer And a collector electrode formed of one or a plurality of conductive layers, and a first alloying reaction layer in a lower portion of the emitter electrode in the emitter contact layer. The second alloying reaction layer is formed in the lower portion of the base electrode in the base layer, and the third alloying reaction is formed in the lower portion of the collector electrode in the second subcollector layer. A layer is formed.

  In addition, the first HBT manufacturing method according to the present invention includes a high-concentration n-type first subcollector layer and a material having a smaller band gap than the first subcollector layer on one main surface of the semi-insulating substrate. A high-concentration n-type second subcollector layer, an i-type or low-concentration n-type collector layer forming film, a high-concentration p-type base layer forming film, and a material having a larger band gap than the base layer forming film. An n-type emitter layer forming film, a high-concentration n-type emitter cap layer forming film, and a high-concentration n-type emitter contact layer forming film made of a material having a smaller band gap than the emitter cap layer forming film are sequentially formed. The emitter contact layer forming film and the emitter cap layer forming film are patterned so that the base electrode forming region in the emitter layer forming film is exposed and the emitter contact layer forming film is exposed. And forming the emitter cap layer, and patterning the emitter layer forming film, the base layer forming film, and the collector layer forming film to expose the collector electrode forming region in the second subcollector layer, Forming a base layer and a collector layer; forming an emitter electrode made of one or more conductive layers on the emitter electrode formation region in the emitter contact layer; and on the base electrode formation region in the emitter layer. Forming a base electrode made of one or more conductive layers, forming a collector electrode made of one or more conductive layers on the collector electrode formation region in the second subcollector layer, and heat treatment Is used to place the first alloying reaction layer on the lower side of the emitter electrode in the emitter contact layer. The second alloying reaction layer in the lower portion of the base electrode, and a step of forming respectively a third alloying reaction layer of the lower part of the collector electrode of the second sub-collector layer.

  The second HBT manufacturing method according to the present invention includes a high-concentration n-type first subcollector layer and a material having a smaller band gap than the first subcollector layer on one main surface of the semi-insulating substrate. A high-concentration n-type second subcollector layer, an i-type or low-concentration n-type collector layer forming film, a high-concentration p-type base layer forming film, and a material having a larger band gap than the base layer forming film. An n-type emitter layer forming film, a high-concentration n-type emitter cap layer forming film, and a high-concentration n-type emitter contact layer forming film made of a material having a smaller band gap than the emitter cap layer forming film are sequentially formed. And patterning the emitter contact layer forming film, the emitter cap layer forming film, and the emitter layer forming film so that the base electrode forming region in the base layer forming film is exposed. Patterning the base layer forming film and the collector layer forming film so as to expose the collector electrode forming region in the second subcollector layer, and the step of forming the mitter contact layer, the emitter cap layer, and the emitter layer A step of forming a collector layer, a step of forming an emitter electrode made of one or more conductive layers on the emitter electrode formation region in the emitter contact layer, and a step of forming one on the base electrode formation region in the base layer. Or a step of forming a base electrode made of a plurality of conductive layers, a step of forming a collector electrode made of one or more conductive layers on the collector electrode formation region in the second subcollector layer, and heat treatment. A first alloying reaction layer on the lower side of the emitter electrode in the emitter contact layer, and a base layer in the base layer. The second alloying reaction layer in the lower portion of the electrode, and a step of forming respectively a third alloying reaction layer of the lower part of the collector electrode of the second sub-collector layer.

In the present application, high concentration means that the impurity concentration is 1 × 10 ¹⁸ cm ⁻³ or more, and low concentration means that the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or less.

  According to the present invention, since each of the emitter contact layer and the second subcollector layer uses a high-concentration n-type semiconductor made of a material having a small band gap, the emitter contact layer and the metal constituting the emitter electrode formed thereon The ohmic connection between the second sub-collector layer and the metal constituting the collector electrode formed thereon can be easily realized. Accordingly, the same material as that of the base electrode can be used as the material of the emitter electrode and the collector electrode, whereby each electrode can be formed at the same time, so that the number of manufacturing steps can be reduced, thereby reducing the manufacturing cost. Can be reduced.

  Further, according to the present invention, the emitter electrode, the base electrode, and the collector electrode are all made of the same material, in other words, by making the structure of the single layer or the plurality of layers constituting each electrode the same, The optimum heat treatment conditions for forming the alloying reaction layers on the lower side can be set to the same conditions. Specifically, the optimum heat treatment conditions for forming the first alloying reaction layer below the emitter electrode, and the optimum heat treatment conditions for forming the second alloying reaction layer below the base electrode, The optimum heat treatment conditions for forming the third alloying reaction layer below the collector electrode can be matched. Therefore, good ohmic contact can be obtained in all electrodes.

  According to the HBT and the manufacturing method thereof of the present invention, the emitter electrode, the base electrode, and the collector electrode can be formed at the same time, so that the number of manufacturing steps can be reduced, thereby reducing the manufacturing cost. In addition, the emitter electrode, the base electrode, and the collector electrode can be made of the same material, so that the optimum heat treatment conditions for forming the alloying reaction layers under each electrode can be set to the same conditions. Good ohmic contact can be obtained at the electrodes.

(First embodiment)
Hereinafter, the HBT and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing the structure of the HBT according to this embodiment.

As shown in FIG. 1, on a semi-insulating substrate 101 made of GaAs, for example, a first n-type GaAs layer having a thickness of 600 nm doped with, for example, an n-type impurity at a high concentration of 5 × 10 ¹⁸ cm ⁻³ . One subcollector layer 102 is formed. On the first subcollector layer 102, for example, a second subcollector layer 108 made of an n-type InGaAs layer having a thickness of 100 nm doped with n-type impurities at a high concentration of 1 × 10 ¹⁹ cm ⁻³ is formed. ing. The band gap of InGaAs constituting the second subcollector layer 108 is smaller than the band gap of GaAs constituting the first subcollector layer 102.

On a predetermined region in the second subcollector layer 108, for example, a collector layer 103 made of an n-type GaAs layer having a thickness of 500 nm doped with n-type impurities at a low concentration of 1 × 10 ¹⁶ cm ⁻³ , for example, p A base layer 104 made of a p-type GaAs layer with a thickness of 100 nm doped with a high concentration of 4 × 10 ¹⁹ cm ⁻³ and an n-type impurity of 3 × 10 ¹⁷ cm ⁻³ , for example. An emitter layer 105 made of an n-type InGaP layer (specifically, In _0.48 Ga _0.52 P having an In composition ratio of about 48%) having a thickness of 30 nm is sequentially stacked. That is, on the second subcollector layer 108, the stacked structure of the collector layer 103, the base layer 104, and the emitter layer 105 is formed in a convex shape. Note that an i-type GaAs layer may be used as the collector layer 103. The band gap of In _0.48 Ga _0.52 P constituting the emitter layer 105 is larger than the band gap of GaAs constituting the base layer 104.

On a predetermined region of the emitter layer 105, an emitter cap layer 106 made of an n-type GaAs layer with a thickness of 200 nm doped with, for example, an n-type impurity at a high concentration of 3 × 10 ¹⁸ cm ⁻³ , and an n-type, for example, An emitter contact layer 107 made of an n-type InGaAs layer having a thickness of 100 nm doped with impurities at a high concentration of 1 × 10 ¹⁹ cm ⁻³ is sequentially laminated. That is, on the emitter layer 105, the emitter cap layer 106 and the emitter contact layer 107 are formed in a convex shape. The band gap of InGaAs constituting the emitter contact layer 107 is smaller than the band gap of GaAs constituting the emitter cap layer 106.

  On the emitter contact layer 107, for example, an emitter electrode 111 having a Pt / Ti / Pt / Au structure is formed. A base electrode 112 having a Pt / Ti / Pt / Au structure, for example, is formed on the exposed portion of the emitter layer 105 where the emitter cap layer 106 is not formed. A collector electrode 113 having, for example, a Pt / Ti / Pt / Au structure is formed on the exposed portion of the second subcollector layer 108 where the collector layer 103 is not formed.

  A first Pt alloying reaction layer 114 is formed on the emitter contact layer 107 below the emitter electrode 111. Here, the first Pt alloying reaction layer 114 is formed by reacting Pt constituting the lowermost layer of the emitter electrode 111 and InGaAs constituting the emitter contact layer 107 by heat treatment. The first Pt alloying reaction layer 114 is formed only inside the emitter contact layer 107.

  A second Pt alloying reaction layer 115 is formed on the lower portion of the base electrode 112 in the emitter layer 105. Here, the second Pt alloying reaction layer 115 is formed by reacting Pt constituting the lowermost layer of the base electrode 112 and InGaP constituting the emitter layer 105 by heat treatment. Further, the second Pt alloying reaction layer 115 is formed so as to penetrate the emitter layer 105 and reach the base layer 104. As a result, the base electrode 112 and the base layer 104 can be brought into contact with each other via the second Pt alloying reaction layer 115, so that an ohmic contact can be reliably obtained.

  A third Pt alloying reaction layer 116 is formed in a portion of the second subcollector layer 108 below the collector electrode 113. Here, the third Pt alloying reaction layer 116 is formed by reacting Pt constituting the lowermost layer of the collector electrode 113 and InGaAs constituting the second sub-collector layer 108 by heat treatment. is there. The third Pt alloying reaction layer 116 is formed only inside the second subcollector layer 108.

  In this embodiment, in order to electrically isolate individual HBTs, the substrate is formed through the stacked structure of the second subcollector layer 108 and the first subcollector layer 102 around each HBT formation region. An element isolation region 141 reaching 101 is formed.

  Hereinafter, a method for manufacturing the HBT of this embodiment shown in FIG. 1 will be described with reference to the drawings.

  2 (a) to 2 (c) and FIGS. 3 (a) and 3 (b) are cross-sectional views showing respective steps of the method of manufacturing the HBT according to the present embodiment.

First, as shown in FIG. 2A, a semi-insulating substrate 101 made of GaAs, for example, is formed by a crystal growth method such as MBE (molecular beam epitaxy) or MOCVD (metal organic chemical vapor deposition). On top of this, for example, a first subcollector layer 102 made of an n-type GaAs layer with a thickness of 600 nm doped with an n-type impurity at a high concentration of 5 × 10 ¹⁸ cm ⁻³ , and an n-type impurity of 1 × 10 ¹⁹ cm, for example. ^-3 and a second sub-collector layer 108 made of a highly doped n-type InGaAs layer with a thickness of 100 nm, for example, a n-type impurity of 1 × 10 ¹⁶ cm ^-3 and a lightly doped 500 nm thick a collector layer forming film 123 made of n-type GaAs layer, for example, a base layer forming film 124 a p-type impurity is a p-type GaAs layer having a thickness of 100nm which is heavily doped with 4 × 10 ¹⁹ cm ^-3 For example the emitter layer n-type InGaP (specifically an In composition ratio of about 48% of In _0.48 Ga _0.52 P) having a thickness of 30nm which an n-type impurity is doped at a concentration of 3 × 10 ¹⁷ cm ^-3 consisting layer formed For example, an emitter cap layer forming film 126 made of an n-type GaAs layer with a thickness of 200 nm doped with a high concentration of 3 × 10 ¹⁸ cm ⁻³ , for example, n-type impurities, and an n-type impurity of 1 × An emitter contact layer forming film 127 made of an n-type InGaAs layer having a thickness of 10 ¹⁹ cm ⁻³ and a high doping concentration of 100 nm is sequentially formed. An i-type GaAs layer may be formed as the collector layer forming film 123. Further, the band gap of In _0.48 Ga _0.52 P constituting the emitter layer forming film 125 is larger than the band gap of GaAs constituting the base layer forming film 124. The band gap of InGaAs constituting the emitter contact layer forming film 127 is smaller than the band gap of GaAs constituting the emitter cap layer forming film 126.

Next, as shown in FIG. 2B, using the photoresist pattern 131 that protects the emitter formation region as a mask, the emitter contact layer formation film 127 and the emitter cap layer formation film using, for example, a phosphoric acid-based etching solution. Etching is sequentially performed on 126. As a result, an emitter island region having a laminated structure of the emitter cap layer 106 and the emitter contact layer 107 is formed, and a base electrode forming region in the emitter layer forming film 125 is exposed. At this time, the emitter layer forming film 125 made of In _0.48 Ga _0.52 P is hardly etched.

  Next, as shown in FIG. 2C, with the photoresist pattern 132 protecting the base formation region including the emitter formation region as a mask, for example, hydrochloric acid diluted with water is used to form the emitter layer formation film 125. Etching is performed selectively, and then, using the patterned emitter layer forming film 125, that is, the emitter layer 105 as a mask, using, for example, a citric acid-based etching solution, the base layer forming film 124 and the collector layer forming film Etching is sequentially performed on 123. As a result, a base island region having a stacked structure of the collector layer 103, the base layer 104, and the emitter layer 105 is formed, and the collector electrode formation region in the second subcollector layer 108 is exposed. At this time, the second subcollector layer 108 made of InGaAs is hardly etched. That is, in the present embodiment, the second sub-collector layer 108 that is an InGaAs layer functions as an etching stopper layer in wet etching using a citric acid-based etching solution. The etching accuracy when forming the film can be greatly improved.

  Next, as shown in FIG. 3A, each of the second sub-collector layer 108 and the first sub-collector layer 102 is used with the photoresist pattern 133 protecting each unit HBT cell (individual HBT formation region) as a mask. In contrast, for example, He (helium) ions are implanted to form the element isolation region 141. Thereby, each unit HBT cell is separated.

  Next, as shown in FIG. 3B, the photoresist pattern 134 for forming each electrode, specifically, each of the emitter electrode formation region, the base electrode formation region, and the collector electrode formation region is opened. A photoresist pattern 134 is formed. Thereafter, for example, by vapor deposition, the entire surface of the substrate, for example, a Pt / Ti / Pt / Au structure (specifically, a 30 nm thick Pt film, a 100 nm thick Ti film, a 50 nm thick Pt film, and a thickness) An electrode forming film 135 having a structure in which 50 nm Au films are sequentially stacked is formed. Thereafter, an unnecessary electrode formation film 135 is peeled off together with the photoresist pattern 134 by, for example, a lift-off method, thereby forming an emitter electrode 111 on the emitter electrode formation region in the emitter contact layer 107, and a base electrode in the emitter layer 105. A base electrode 112 is formed on the formation region, and a collector electrode 113 is formed on the collector electrode formation region in the second subcollector layer 108. That is, in this embodiment, the emitter electrode 111, the base electrode 112, and the collector electrode 113 are formed simultaneously.

  Finally, in order to complete the HBT of this embodiment shown in FIG. 1, the structure of the metal (specifically, Pt) constituting each electrode and the semiconductor layer under each electrode by, for example, heat treatment at 390 ° C. for 120 seconds. React with the material. As a result, the first Pt alloying reaction layer 114 is formed in the lower part of the emitter electrode 111 in the emitter contact layer 107, and the second Pt alloying reaction is performed in the lower part of the base electrode 112 in the emitter layer 105. The layer 115 is formed, and the third Pt alloying reaction layer 116 is formed in the lower portion of the collector electrode 113 in the second subcollector layer 108. The first Pt alloying reaction layer 114 is formed only inside the emitter contact layer 107, and the second Pt alloying reaction layer 115 is formed so as to penetrate the emitter layer 105 and reach the base layer 104. The third Pt alloying reaction layer 116 is formed only inside the second subcollector layer 108. In the present embodiment, the deactivation process for the element isolation region (isolation region formed by ion implantation) 141 for electrically isolating the unit HBT cells from each other is performed on each Pt alloying reaction layer 114 to 116. At the same time, the heat treatment is performed to form the film, thereby reducing the number of manufacturing steps.

  As described above, according to the present embodiment, the emitter contact layer 107 and the second subcollector layer 108 are made of a high-concentration n-type semiconductor made of a material having a small band gap. The ohmic connection between the metal constituting the emitter electrode 111 formed on the second sub-collector layer 108 and the metal constituting the collector electrode 113 formed thereon can be easily realized. Can be realized easily. Therefore, the same material as that of the base electrode 112 can be used as the material of the emitter electrode 111 and the collector electrode 113, whereby each of the electrodes 111 to 113 can be formed at the same time, thereby reducing the number of manufacturing steps. Therefore, the manufacturing cost can be reduced.

  Further, according to the present embodiment, the emitter electrode 111, the base electrode 112, and the collector electrode 113 are all made of the same material, in other words, by making the metal laminated structure of the electrodes 111 to 113 the same, The optimum heat treatment conditions for forming the alloying reaction layers 114 to 116 below 111 to 113 can be set to the same conditions. Specifically, the optimum heat treatment conditions for forming the first alloying reaction layer 114 under the emitter electrode 111 and the second alloying reaction layer 115 under the base electrode 112 are formed. The optimum heat treatment condition and the optimum heat treatment condition for forming the third alloying reaction layer 116 below the collector electrode 113 can be matched. Therefore, good ohmic contact can be obtained in all the electrodes 111 to 113.

(Second Embodiment)
Hereinafter, an HBT and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings. The HBT according to the present embodiment is different from the first embodiment in that the base electrode 112 is formed on the base layer 104 with the emitter layer 105 interposed therebetween in the first embodiment. In this embodiment, the base electrode 112 is formed immediately above the base layer 104 as will be described later.

  FIG. 4 is a cross-sectional view showing the structure of the HBT according to this embodiment.

As shown in FIG. 4, on a semi-insulating substrate 101 made of GaAs, for example, a first n-type GaAs layer having a thickness of 600 nm doped with, for example, an n-type impurity at a high concentration of 5 × 10 ¹⁸ cm ⁻³ . One subcollector layer 102 is formed. On the first subcollector layer 102, for example, a second subcollector layer 108 made of an n-type InGaAs layer having a thickness of 100 nm doped with n-type impurities at a high concentration of 1 × 10 ¹⁹ cm ⁻³ is formed. ing. The band gap of InGaAs constituting the second subcollector layer 108 is smaller than the band gap of GaAs constituting the first subcollector layer 102.

On a predetermined region of the second subcollector layer 108, for example, a collector layer 103 made of an n-type GaAs layer having a thickness of 500 nm doped with n-type impurities at a low concentration of 1 × 10 ¹⁶ cm ⁻³ , for example, A base layer 104 made of a p-type GaAs layer having a thickness of 100 nm doped with p-type impurities at a high concentration of 4 × 10 ¹⁹ cm ⁻³ is sequentially laminated. That is, the stacked structure of the collector layer 103 and the base layer 104 is formed in a convex shape on the second subcollector layer 108. Note that an i-type GaAs layer may be used as the collector layer 103.

On a predetermined region in the base layer 104, for example, n-type InGaP with a thickness of 30 nm doped with n-type impurities at a concentration of 3 × 10 ¹⁷ cm ⁻³ (specifically, the In composition ratio is about 48%). An emitter layer 105 made of an In _0.48 Ga _0.52 P) layer, for example, an emitter cap layer 106 made of an n-type GaAs layer having a thickness of 200 nm and highly doped with n-type impurities of 3 × 10 ¹⁸ cm ⁻³ , and n An emitter contact layer 107 made of an n-type InGaAs layer having a thickness of 100 nm doped with a high concentration of 1 × 10 ¹⁹ cm ^{−3 of a} type impurity is sequentially laminated. That is, the laminated structure of the emitter layer 105, the emitter cap layer 106, and the emitter contact layer 107 is formed in a convex shape on the base layer 104. Here, the band gap of In _0.48 Ga _0.52 P constituting the emitter layer 105 is larger than the band gap of GaAs constituting the base layer 104. The band gap of InGaAs constituting the emitter contact layer 107 is smaller than the band gap of GaAs constituting the emitter cap layer 106.

  On the emitter contact layer 107, for example, an emitter electrode 111 having a Pt / Ti / Pt / Au structure is formed. A base electrode 112 having, for example, a Pt / Ti / Pt / Au structure is formed on the exposed portion of the base layer 104 where the emitter layer 105 is not formed. A collector electrode 113 having, for example, a Pt / Ti / Pt / Au structure is formed on the exposed portion of the second subcollector layer 108 where the collector layer 103 is not formed.

  A first Pt alloying reaction layer 114 is formed on the emitter contact layer 107 below the emitter electrode 111. Here, the first Pt alloying reaction layer 114 is formed by reacting Pt constituting the lowermost layer of the emitter electrode 111 and InGaAs constituting the emitter contact layer 107 by heat treatment. The first Pt alloying reaction layer 114 is formed only inside the emitter contact layer 107.

  A second Pt alloying reaction layer 115 is formed on the lower portion of the base electrode 112 in the base layer 104. Here, the second Pt alloying reaction layer 115 is formed by reacting Pt constituting the lowermost layer of the base electrode 112 and GaAs constituting the base layer 104 by heat treatment. The second Pt alloying reaction layer 115 is formed only inside the base layer 104.

  A third Pt alloying reaction layer 116 is formed in a portion of the second subcollector layer 108 below the collector electrode 113. Here, the third Pt alloying reaction layer 116 is formed by reacting Pt constituting the lowermost layer of the collector electrode 113 and InGaAs constituting the second sub-collector layer 108 by heat treatment. is there. The third Pt alloying reaction layer 116 is formed only inside the second subcollector layer 108.

  In this embodiment, in order to electrically isolate individual HBTs, the substrate is formed through the stacked structure of the second subcollector layer 108 and the first subcollector layer 102 around each HBT formation region. An element isolation region 141 reaching 101 is formed.

  Hereinafter, a method for manufacturing the HBT of this embodiment shown in FIG. 4 will be described with reference to the drawings.

  FIGS. 5A to 5C and FIGS. 6A and 6B are cross-sectional views showing respective steps of the method for manufacturing the HBT according to the present embodiment.

First, as shown in FIG. 5A, an n-type impurity, for example, 5 × 10 ¹⁸ cm ⁻³ is formed on a semi-insulating substrate 101 made of GaAs, for example, by a crystal growth method such as MBE or MOCVD. A first sub-collector layer 102 made of a highly doped n-type GaAs layer with a thickness of 600 nm, and an n-type impurity with a thickness of 100 nm doped with n-type impurities at a high concentration of 1 × 10 ¹⁹ cm ⁻³ , for example. A second subcollector layer 108 made of an InGaAs layer, a collector layer forming film 123 made of an n-type GaAs layer having a thickness of 500 nm doped with n-type impurities at a low concentration of 1 × 10 ¹⁶ cm ⁻³ , for example, A base layer forming film 124 made of a p-type GaAs layer with a thickness of 100 nm doped with p-type impurities at a high concentration of 4 × 10 ¹⁹ cm ⁻³ , for example, an n-type impurity with a concentration of 3 × 10 ¹⁷ cm ⁻³ At do Been (specifically an In composition ratio of about 48% of In _0.48 Ga _0.52 P) n-type InGaP thickness 30nm and an emitter layer forming film 125 made of layers, for example, n-type impurity 3 × 10 ¹⁸ cm ^{- 3} and an emitter cap layer forming film 126 made of a highly doped n-type GaAs layer having a thickness of 200 nm, and a n-type impurity of 1 × 10 ¹⁹ cm ⁻³ and a highly doped n-type GaAs layer 126 having a thickness of 100 nm. An emitter contact layer forming film 127 made of an n-type InGaAs layer is sequentially formed. An i-type GaAs layer may be formed as the collector layer forming film 123. Further, the band gap of In _0.48 Ga _0.52 P constituting the emitter layer forming film 125 is larger than the band gap of GaAs constituting the base layer forming film 124. The band gap of InGaAs constituting the emitter contact layer forming film 127 is smaller than the band gap of GaAs constituting the emitter cap layer forming film 126.

  Next, as shown in FIG. 5B, using the photoresist pattern 131 that protects the emitter formation region as a mask, the emitter contact layer formation film 127 and the emitter cap layer formation film using, for example, a phosphoric acid-based etching solution. Etching is sequentially performed on 126. Subsequently, using the photoresist pattern 131 as a mask, the emitter layer forming film 125 is selectively etched using, for example, hydrochloric acid diluted with water. As a result, an emitter island region having a laminated structure of the emitter layer 105, the emitter cap layer 106, and the emitter contact layer 107 is formed, and the base electrode forming region in the base layer forming film 124 is exposed. At this time, the base layer forming film 124 made of a GaAs layer is hardly etched.

  Next, as shown in FIG. 5C, using the photoresist pattern 132 that protects the base formation region including the emitter formation region as a mask, using, for example, a citric acid-based etching solution, the base layer formation film 124 and Etching is sequentially performed on the collector layer forming film 123. As a result, a base island region having a stacked structure of the collector layer 103 and the base layer 104 is formed, and a collector electrode formation region in the second subcollector layer 108 is exposed. At this time, the second subcollector layer 108 made of InGaAs is hardly etched. That is, in the present embodiment, the second sub-collector layer 108 that is an InGaAs layer functions as an etching stopper layer in wet etching using a citric acid-based etching solution. The etching accuracy when forming the film can be greatly improved.

  Next, as shown in FIG. 6A, each of the second sub-collector layer 108 and the first sub-collector layer 102 is used with the photoresist pattern 133 protecting each unit HBT cell (individual HBT formation region) as a mask. In contrast, for example, He (helium) ions are implanted to form the element isolation region 141. Thereby, each unit HBT cell is separated.

  Next, as shown in FIG. 6B, the photoresist pattern 134 for forming each electrode, specifically, each of the emitter electrode formation region, the base electrode formation region, and the collector electrode formation region is opened. A photoresist pattern 134 is formed. Thereafter, for example, by vapor deposition, the entire surface of the substrate, for example, a Pt / Ti / Pt / Au structure (specifically, a 30 nm thick Pt film, a 100 nm thick Ti film, a 50 nm thick Pt film, and a thickness) An electrode forming film 135 having a structure in which 50 nm Au films are sequentially stacked is formed. Thereafter, an unnecessary electrode formation film 135 is peeled off together with the photoresist pattern 134 by, for example, a lift-off method, thereby forming an emitter electrode 111 on the emitter electrode formation region in the emitter contact layer 107, and a base electrode in the base layer 104. A base electrode 112 is formed on the formation region, and a collector electrode 113 is formed on the collector electrode formation region in the second subcollector layer 108. That is, in this embodiment, the emitter electrode 111, the base electrode 112, and the collector electrode 113 are formed simultaneously.

  Finally, in order to complete the HBT of this embodiment shown in FIG. 4, the structure of the metal (specifically, Pt) constituting each electrode and the semiconductor layer under each electrode by, for example, heat treatment at 390 ° C. for 120 seconds. React with the material. As a result, the first Pt alloying reaction layer 114 is formed in the lower portion of the emitter electrode 111 in the emitter contact layer 107, and the second Pt alloying reaction is performed in the lower portion of the base electrode 112 in the base layer 104. The layer 115 is formed, and the third Pt alloying reaction layer 116 is formed in the lower portion of the collector electrode 113 in the second subcollector layer 108. The first Pt alloying reaction layer 114 is formed only inside the emitter contact layer 107, and the second Pt alloying reaction layer 115 is formed only inside the base layer 104, and a third Pt alloying reaction layer is formed. The layer 116 is formed only inside the second subcollector layer 108. In the present embodiment, the deactivation process for the element isolation region (isolation region formed by ion implantation) 141 for electrically isolating the unit HBT cells from each other is performed on each Pt alloying reaction layer 114 to 116. At the same time, the heat treatment is performed to form the film, thereby reducing the number of manufacturing steps.

  In this embodiment, all the emitter layer forming film 125 outside the emitter forming region is removed (see FIG. 5B), but instead, the region outside the base forming region and the base electrode forming region. The emitter layer forming film 125 may be removed. In this manner, in the HBT of this embodiment shown in FIG. 4, the base layer 104 other than the base electrode formation region is covered with the emitter layer 105 while the base electrode 112 is provided immediately above the base layer 104 in the base electrode formation region. Can do.

  As described above, according to the present embodiment, the emitter contact layer 107 and the second subcollector layer 108 are made of a high-concentration n-type semiconductor made of a material having a small band gap. The ohmic connection between the metal constituting the emitter electrode 111 formed on the second sub-collector layer 108 and the metal constituting the collector electrode 113 formed thereon can be easily realized. Can be realized easily. Therefore, the same material as that of the base electrode 112 can be used as the material of the emitter electrode 111 and the collector electrode 113, whereby each of the electrodes 111 to 113 can be formed at the same time, thereby reducing the number of manufacturing steps. Therefore, the manufacturing cost can be reduced.

  Further, according to the present embodiment, the emitter electrode 111, the base electrode 112, and the collector electrode 113 are all made of the same material, in other words, by making the metal laminated structure of the electrodes 111 to 113 the same, The optimum heat treatment conditions for forming the alloying reaction layers 114 to 116 below 111 to 113 can be set to the same conditions. Specifically, the optimum heat treatment conditions for forming the first alloying reaction layer 114 under the emitter electrode 111 and the second alloying reaction layer 115 under the base electrode 112 are formed. The optimum heat treatment condition and the optimum heat treatment condition for forming the third alloying reaction layer 116 below the collector electrode 113 can be matched. Therefore, good ohmic contact can be obtained in all the electrodes 111 to 113.

  In the first or second embodiment, it goes without saying that the impurity concentration, thickness, composition ratio, and the like in each semiconductor layer constituting the HBT are not limited to the above-described numerical values.

  In the first or second embodiment, the Pt layer is used as the lowermost layer in each of the emitter electrode 111, the base electrode 112, and the collector electrode 113. Instead, for example, a Pd layer or a Ni layer is used. Even in this case, an alloying reaction layer is formed on the lower side of each electrode, whereby the same effect as in this embodiment can be obtained. Further, as the emitter electrode 111, the base electrode 112, and the collector electrode 113, a single layer structure made of Pt, Pd, or Ni may be used.

  Further, in the first or second embodiment, the element isolation region is formed by using ion implantation, but instead of this, for example, a trench serving as the element isolation region may be formed by using wet etching.

  In the first or second embodiment, the InGaP layer is used as the emitter layer 105, but an AlGaAs layer, for example, may be used instead.

  In the first or second embodiment, the InGaAs layer is used as the second sub-collector layer 108 and the emitter contact layer 107, but a semiconductor stacked structure including an InGaAs layer may be used instead.

  In the first or second embodiment, an HBT using a GaAs substrate as the semi-insulating substrate 101 is targeted, but instead, an InP substrate is used as the semi-insulating substrate 101 and the emitter layer 105 is used. Needless to say, the same effect can be obtained when an HBT using an InP layer or an InAlAs layer is used.

  The present invention relates to an HBT and a manufacturing method thereof, and when applied to an HBT in which an alloying reaction layer is used as an ohmic electrode in order to reduce contact resistance, the manufacturing cost is reduced, and good contact characteristics are achieved in each electrode. The effect is obtained and useful.

It is sectional drawing which shows the structure of HBT which concerns on the 1st Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of HBT which concerns on the 1st Embodiment of this invention. (A) And (b) is sectional drawing which shows each process of the manufacturing method of HBT which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure of HBT which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of HBT which concerns on the 2nd Embodiment of this invention. (A) And (b) is sectional drawing which shows each process of the manufacturing method of HBT which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the conventional HBT. (A) And (b) is a figure which shows the heat processing time dependence of the contact resistivity in case a metal and a semiconductor contact.

Explanation of symbols

101 Substrate 102 First Subcollector Layer 103 Collector Layer 104 Base Layer 105 Emitter Layer 106 Emitter Cap Layer 107 Emitter Contact Layer 108 Second Subcollector Layer 111 Emitter Electrode 112 Base Electrode 113 Collector Electrode 114 First Pt Alloying Reaction Layer 115 Second Pt alloying reaction layer 116 Third Pt alloying reaction layer 123 Collector layer forming film 124 Base layer forming film 125 Emitter layer forming film 126 Emitter cap layer forming film 127 Emitter contact layer forming film 131 Photoresist pattern 132 Photoresist pattern 133 Photoresist pattern 134 Photoresist pattern 135 Electrode forming film 141 Element isolation region

Claims (20)

A high-concentration n-type first subcollector layer;
A high-concentration n-type second subcollector layer formed on the first subcollector layer and made of a material having a smaller band gap than the first subcollector layer;
An i-type or low-concentration n-type collector layer formed on a predetermined portion of the second subcollector layer;
A high-concentration p-type base layer formed on the collector layer;
An n-type emitter layer formed on the base layer and made of a material having a larger band gap than the base layer;
A high-concentration n-type emitter cap layer formed on a predetermined portion of the emitter layer;
A high-concentration n-type emitter contact layer formed on the emitter cap layer and made of a material having a smaller band gap than the emitter cap layer;
An emitter electrode formed on the emitter contact layer and comprising one or more conductive layers;
A base electrode formed on a portion of the emitter layer where the emitter cap layer is not formed and made of one or more conductive layers;
A collector electrode formed on a portion of the second subcollector layer where the collector layer is not formed, and comprising one or a plurality of conductive layers;
A first alloying reaction layer is formed in a lower portion of the emitter electrode in the emitter contact layer;
A second alloying reaction layer is formed in a lower portion of the base electrode in the emitter layer;
A heterojunction bipolar transistor, wherein a third alloying reaction layer is formed in a lower portion of the collector electrode in the second subcollector layer.   The heterojunction bipolar transistor according to claim 1, wherein the emitter electrode, the base electrode, and the collector electrode are made of the same material. The first alloying reaction layer is formed only inside the emitter contact layer,
The third alloying reaction layer is formed only inside the second subcollector layer,
3. The heterojunction bipolar transistor according to claim 1, wherein the second alloying reaction layer is formed so as to penetrate the emitter layer and reach the base layer. 4.   4. The heterojunction bipolar transistor according to claim 1, wherein each of the second subcollector layer and the emitter contact layer is a semiconductor layer including an InGaAs layer. 5.   The lowermost conductive layer constituting the emitter electrode, the lowermost conductive layer constituting the base electrode, and the lowermost conductive layer constituting the collector electrode are all made of Pt, Pd or Ni. The heterojunction bipolar transistor according to any one of claims 1 to 4. A high-concentration n-type first subcollector layer;
A high-concentration n-type second subcollector layer formed on the first subcollector layer and made of a material having a smaller band gap than the first subcollector layer;
An i-type or low-concentration n-type collector layer formed on a predetermined portion of the second subcollector layer;
A high-concentration p-type base layer formed on the collector layer;
An n-type emitter layer formed on a predetermined portion of the base layer and made of a material having a larger band gap than the base layer;
A high-concentration n-type emitter cap layer formed on the emitter layer;
A high-concentration n-type emitter contact layer formed on the emitter cap layer and made of a material having a smaller band gap than the emitter cap layer;
An emitter electrode formed on the emitter contact layer and comprising one or more conductive layers;
A base electrode formed on a portion of the base layer where the emitter layer is not formed and comprising one or more conductive layers;
A collector electrode formed on a portion of the second subcollector layer where the collector layer is not formed, and comprising one or a plurality of conductive layers;
A first alloying reaction layer is formed in a lower portion of the emitter electrode in the emitter contact layer;
A second alloying reaction layer is formed in a lower portion of the base electrode in the base layer;
A heterojunction bipolar transistor, wherein a third alloying reaction layer is formed in a lower portion of the collector electrode in the second subcollector layer.   The heterojunction bipolar transistor according to claim 6, wherein the emitter electrode, the base electrode, and the collector electrode are made of the same material. The first alloying reaction layer is formed only inside the emitter contact layer,
The second alloying reaction layer is formed only inside the base layer,
The heterojunction bipolar transistor according to claim 6 or 7, wherein the third alloying reaction layer is formed only inside the second subcollector layer.   The heterojunction bipolar transistor according to any one of claims 6 to 8, wherein each of the second sub-collector layer and the emitter contact layer is a semiconductor layer including an InGaAs layer.   The lowermost conductive layer constituting the emitter electrode, the lowermost conductive layer constituting the base electrode, and the lowermost conductive layer constituting the collector electrode are all made of Pt, Pd or Ni. The heterojunction bipolar transistor according to any one of claims 6 to 9. A high-concentration n-type first subcollector layer, a high-concentration n-type second subcollector layer made of a material having a smaller band gap than the first subcollector layer, and an i-type on one main surface of the semi-insulating substrate Alternatively, a low-concentration n-type collector layer forming film, a high-concentration p-type base layer forming film, an n-type emitter layer forming film made of a material having a larger band gap than the base layer-forming film, and a high-concentration n Forming a type emitter cap layer forming film, a high concentration n type emitter contact layer forming film made of a material having a smaller band gap than the emitter cap layer forming film,
Patterning the emitter contact layer forming film and the emitter cap layer forming film so as to expose a base electrode forming region in the emitter layer forming film to form an emitter contact layer and an emitter cap layer;
The emitter layer forming film, the base layer forming film, and the collector layer forming film are patterned to expose the emitter layer, the base layer, and the collector layer so that the collector electrode forming region in the second subcollector layer is exposed. Forming, and
Forming an emitter electrode composed of one or a plurality of conductive layers on the emitter electrode formation region in the emitter contact layer;
Forming a base electrode comprising one or more conductive layers on the base electrode formation region in the emitter layer;
Forming a collector electrode composed of one or more conductive layers on the collector electrode formation region in the second subcollector layer;
Using a heat treatment, a first alloying reaction layer is formed on a lower portion of the emitter electrode in the emitter contact layer, and a second alloying reaction layer is formed on a lower portion of the base electrode in the emitter layer, Forming a third alloying reaction layer in a lower portion of the collector electrode in the second subcollector layer. A method of manufacturing a heterojunction bipolar transistor, comprising:   12. The method of manufacturing a heterojunction bipolar transistor according to claim 11, wherein the semi-insulating substrate is a GaAs substrate or an InP substrate.   13. The heterojunction bipolar transistor according to claim 11 or 12, wherein the step of forming the emitter electrode, the step of forming the base electrode, and the step of forming the collector electrode are performed simultaneously. Method.   The lowermost conductive layer constituting the emitter electrode, the lowermost conductive layer constituting the base electrode, and the lowermost conductive layer constituting the collector electrode are all made of Pt, Pd or Ni. A method for manufacturing a heterojunction bipolar transistor according to any one of claims 11 to 13. A step of forming an element isolation region by implanting ions into a region other than the element formation region in each of the second subcollector layer and the first subcollector layer;
15. The deactivation process for the element isolation region into which the ions have been implanted is simultaneously performed by the heat treatment in the step of forming the alloying reaction layers. A method for producing a heterojunction bipolar transistor according to 1. A high-concentration n-type first subcollector layer, a high-concentration n-type second subcollector layer made of a material having a smaller band gap than the first subcollector layer, and an i-type on one main surface of the semi-insulating substrate Alternatively, a low-concentration n-type collector layer forming film, a high-concentration p-type base layer forming film, an n-type emitter layer forming film made of a material having a larger band gap than the base layer-forming film, and a high-concentration n Forming a type emitter cap layer forming film, a high concentration n type emitter contact layer forming film made of a material having a smaller band gap than the emitter cap layer forming film,
The emitter contact layer forming film, the emitter cap layer forming film, and the emitter layer forming film are patterned so as to expose a base electrode forming region in the base layer forming film, thereby forming an emitter contact layer and an emitter cap layer. And forming an emitter layer;
Patterning the base layer forming film and the collector layer forming film so as to expose a collector electrode forming region in the second subcollector layer, and forming a base layer and a collector layer;
Forming an emitter electrode composed of one or a plurality of conductive layers on the emitter electrode formation region in the emitter contact layer;
Forming a base electrode composed of one or more conductive layers on the base electrode formation region of the base layer;
Forming a collector electrode composed of one or more conductive layers on the collector electrode formation region in the second subcollector layer;
Using a heat treatment, a first alloying reaction layer is formed on a lower portion of the emitter electrode in the emitter contact layer, and a second alloying reaction layer is formed on a lower portion of the base electrode in the base layer, Forming a third alloying reaction layer in a lower portion of the collector electrode in the second subcollector layer. A method of manufacturing a heterojunction bipolar transistor, comprising:   The method of manufacturing a heterojunction bipolar transistor according to claim 16, wherein the semi-insulating substrate is a GaAs substrate or an InP substrate.   18. The method of manufacturing a heterojunction bipolar transistor according to claim 16, wherein the step of forming the emitter electrode, the step of forming the base electrode, and the step of forming the collector electrode are performed simultaneously. Method.   The lowermost conductive layer constituting the emitter electrode, the lowermost conductive layer constituting the base electrode, and the lowermost conductive layer constituting the collector electrode are all made of Pt, Pd or Ni. The method for producing a heterojunction bipolar transistor according to any one of claims 16 to 18. A step of forming an element isolation region by implanting ions into a region other than the element formation region in each of the second subcollector layer and the first subcollector layer;
20. The deactivation process for the element isolation region implanted with the ions is simultaneously performed by the heat treatment in the step of forming the alloying reaction layers. A method for producing a heterojunction bipolar transistor according to 1.

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