JP2006093616A - Semiconductor resistive element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor resistive element which can realize a low cost of an MMIC (monolithic microwave integrated circuit), and a method for manufacturing the element. <P>SOLUTION: The semiconductor resistive element comprises a channel layer 104, a Schottky layer 107 formed above the channel layer 104, an active region 115 formed on the same substrate 101 as an FET 110 having a gate electrode 121 formed on the Schottky layer 107 and having part of the Schottky layer 107 and the channel layer 104 isolated by an element isolation region 123 from the FET 110, a contact layer 116 and a gate metal 124 formed on the active region 115, and two ohmic electrodes 122 formed on the contact layer 116. The gate metal 124, which is made of the same material of the gate electrode 121, covers an AlGaAs layer 114 exposed between the two ohmic electrodes 122. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor resistance element and a manufacturing method thereof, and more particularly to a semiconductor resistance element using a compound semiconductor and a manufacturing method thereof.

  In recent years, field effect transistors (hereinafter referred to as FET (Field Effect Transistor)) using a compound semiconductor such as GaAs have been widely used for wireless communication, particularly for power amplifiers and switches of mobile phone terminals. This FET (Field Effect Transistor) is generally an FET using AlGaAs called PHEMT as a Schottky layer. A semiconductor device such as a monolithic microwave integrated circuit (MMIC) in which an active element such as an FET and a passive element such as a semiconductor resistance element, a metal resistance element, or a capacitor are integrated has been widely put into practical use. In such a technical field, a manufacturing method with fewer steps is strongly demanded as in other industries, and the process needs to be simplified.

  FIG. 5A shows an upper surface of an FET as an active element and a semiconductor resistance element as a passive element (see Patent Document 1) in a conventional MMIC (hereinafter referred to as GaAs MMIC) using a semi-insulating substrate made of GaAs. FIG. 5B is a cross-sectional view of the FET and the semiconductor resistance element (cross-sectional view taken along line X1-X1 ′ in FIG. 5A).

  The semiconductor resistance element 21 and the FET 22 are formed on the same substrate and are separated, that is, electrically separated by the element isolation region 23.

The FET 22 includes a substrate 1 made of semi-insulating GaAs and an epitaxial layer 9 formed by crystal growth of a semiconductor layer on the substrate 1. The epitaxial layer 9 has a 1 μm thick buffer layer 2 made of undoped GaAs and a buffer layer 3 made of undoped AlGaAs for relaxing lattice mismatch between the epitaxial layer 9 and the substrate 1. A channel layer 4 made of undoped In _0.2 Ga _0.8 As with a thickness of 20 nm and carrying carriers, a spacer layer 5 made of undoped AlGaAs with a thickness of 5 nm, and only one atomic layer of Si as n-type impurity ions. A carrier supply layer 6 made of planar doped AlGaAs, a Schottky layer 7 made of undoped AlGaAs with a thickness of 30 nm, and a contact layer 8 made of n ⁺ -type GaAs with a thickness of 100 nm are sequentially formed. It is constructed by stacking.

  Here, two ohmic electrodes 10 are formed on the contact layer 8. Further, the contact layer 8 is removed in the region between the two ohmic electrodes 10, and the gate electrode 11 is formed on the Schottky layer 7 exposed on the surface of the epitaxial layer 9.

The semiconductor resistance element 21 is formed on the semi-insulating substrate 1, the buffer layer 2 and the buffer layer 3 formed on the substrate 1, the active region 17 formed on the buffer layer 3, and the active region 17. and a contact layer 18 made of n ⁺ -type GaAs. The active region 17 is part of the channel layer 4, the spacer layer 5, the carrier supply layer 6 and the Schottky layer 7 separated from the FET 22 by the element isolation region 23, that is, the InGaAs layer 13, the AlGaAs layer 14, and the n-type AlGaAs layer 15. And the AlGaAs layer 16.

  Here, two ohmic electrodes 24 are formed on the contact layer 18. In the region between the two ohmic electrodes 24, the contact layer 18 is etched to a predetermined depth. Further, a thin insulating protective film (not shown) made of SiN or SiO is formed on the GaAs MMIC so as to cover the FET 22 and the semiconductor resistance element 21.

  Next, a method for manufacturing the GaAs MMIC configured as described above will be described with reference to the drawings.

6A to 6G are cross-sectional views of a GaAs MMIC.
First, as shown in FIG. 6A, a buffer layer 2, a buffer layer 3, and a channel are formed on a substrate 1 by MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxial growth). The epitaxial layer 9 is formed by epitaxially growing the layer 4, the spacer layer 5, the carrier supply layer 6, the Schottky layer 7 and the contact layer 8 in this order.

  Next, as shown in FIG. 6B, a pattern is formed by a photoresist 30 to protect a predetermined position, and for example, a mixed solution of phosphoric acid, hydrogen peroxide solution and water is used for the epitaxial layer 9. The element isolation region 23 is formed by performing wet etching. As a result, the contact layer 18 and the active region 17 of the semiconductor resistance element 21 are formed.

  Next, as shown in FIG. 6C, after removing the photoresist 30, a pattern is formed with a new photoresist, and ohmic metal made of Ni / Au / Ge alloy is deposited on the entire surface (not shown). The ohmic electrodes 10 and 24 are formed by lifting off.

  Next, as shown in FIG. 6D, a resist pattern 31 having an opening wider than the contact layer 18 of the semiconductor resistance element 21 is formed.

  Next, as shown in FIG. 6E, for example, a mixed solution of phosphoric acid, hydrogen peroxide solution and water is used for the contact layer 18 so that the resistance value of the semiconductor resistance element 21 becomes a desired value. The contact layer 18 having a desired film thickness is formed by wet etching.

  Next, as shown in FIG. 6F, a pattern is formed with a new photoresist, and recess etching is performed on the contact layer 8 in a predetermined region between the two ohmic electrodes 10 of the FET 22, thereby opening the openings. 32 is formed. Thereafter, a gate metal made of, for example, a Ti / Pt / Au alloy is deposited on the entire surface and lifted off, thereby forming the gate electrode 11 on the Schottky layer 7 where the opening 32 is exposed.

Next, as shown in FIG. 6G, a thin insulating protective film 33 made of SiN or SiO so as to cover the gate electrode 11, the Schottky layer 7, the contact layers 8, 18 and the like exposed on the surface. Form.
JP-A-6-77019

  By the way, in the GaAs MMIC, since the epitaxial structure is generally designed with the FET characteristics given the highest priority, it is difficult to set the resistance value of the semiconductor resistance element to a desired value. Therefore, according to the conventional GaAs MMIC manufacturing method, the contact resistance 18 of the semiconductor resistance element is etched to a predetermined depth in the step shown in FIG. It is adjusted to. At this time, since the area of the contact layer 18 and the accuracy of the resistance value are in a trade-off relationship, it is necessary to set an appropriate sheet resistance.

Therefore, the step of etching the contact layer of the semiconductor resistance element (first step) is followed by the FET gate electrode formation step, that is, the normal recess etching that completely removes the contact layer between the ohmic electrodes of the FET. Although the step (second step) is a step of etching the same n ⁺ -type GaAs layer as in the first step, the resist is different from the resist pattern used in the first step. Pattern formation is required. Therefore, the conventional GaAs MMIC has a problem that the manufacturing cost increases.

  The present invention has been made to solve the above-described problems, and can reduce the manufacturing cost of the MMIC including the semiconductor resistance element and the FET, that is, the semiconductor resistance element capable of reducing the cost of the MMIC. It aims at providing the manufacturing method.

  In order to achieve the above object, a semiconductor resistance element of the present invention includes an active element having a channel layer, a Schottky layer formed on the channel layer, and a gate electrode formed on the Schottky layer. An active region formed on the same substrate and separated from the active element by an element isolation region and having a part of the Schottky layer and a channel layer; a contact layer and a metal electrode formed on the active region; Two ohmic electrodes formed on the contact layer, the Schottky layer is exposed between the two ohmic electrodes, the metal electrode is made of the same material as the gate electrode, and the two The exposed Schottky layer between the ohmic electrodes is covered. Here, the metal electrode may not be electrically connected to any circuit but may be in a floating state in potential.

  According to this configuration, it is possible to increase the mesa resistance, that is, to remove the contact layer at the same time as the formation of the gate electrode of the FET represented by the pseudomorphic HEMT. The manufacturing cost can be reduced.

  The active region surface may be located in the same plane as the element isolation region surface, or the element isolation region may be formed by boron ion implantation.

  According to this configuration, the surface portion of the mesa resistor is not uneven, and the element isolation region is formed on the side surface of the mesa resistor. Therefore, the side surface of the mesa resistor is covered with the metal electrode, and the channel layer separated from the FET is formed. Depletion from the side of the existing electrons occurs and the resistance is not increased. That is, the spread of the depletion layer from the mesa resistor side wall can be suppressed. This is particularly effective when the mesa resistance width is reduced in order to achieve high resistance.

  Further, the present invention is formed on the same substrate as an active element having a channel layer, a Schottky layer formed on the channel layer, and a contact layer and a gate electrode formed on the Schottky layer. A method of manufacturing a semiconductor resistance element, wherein a photoresist pattern is formed on the contact layer, a predetermined region of the contact layer is removed using the photoresist pattern, and a part of the contact layer is separated from the active element Forming an isolation region in the Schottky layer and the channel layer by performing etching using the photoresist pattern, and forming one of the Schottky layer and the channel layer separated from the active element. An active region forming step of forming an active region having a portion, and two ohmic layers on the contact layer separated from the active element. Forming an ohmic electrode, and removing a predetermined region of the contact layer separated from the active element so that the Schottky layer separated from the active element is exposed between the two ohmic electrodes. And a metal electrode forming step of forming a metal electrode on the active region so as to cover the exposed Schottky layer between the two ohmic electrodes, and the removing step and the metal electrode forming step include: The semiconductor resistance element manufacturing method may be performed simultaneously with the formation of the gate electrode of the active element.

  According to this manufacturing method, since the mesa resistance can be increased simultaneously with the recess etching for forming the gate electrode of the FET, the manufacturing cost of the MMIC can be reduced.

  The present invention further includes a channel layer, a Schottky layer formed on the channel layer, a contact layer formed on the Schottky layer, and a gate electrode formed on the Schottky layer. A method of manufacturing a semiconductor resistance element formed on the same substrate as an active element, wherein a photoresist pattern is formed on the contact layer, and a predetermined region of the contact layer is removed using the photoresist pattern to make a contact Forming a contact isolation layer in the Schottky layer and the channel layer by performing a contact layer forming step of separating a part of the layer from the active element, and ion implantation using the photoresist pattern; An active region forming step of forming an active region having a part of the separated Schottky layer, channel layer, and contact layer; An ohmic electrode forming step of forming two ohmic electrodes on the contact layer separated from the moving element; and the active element so that the Schottky layer separated from the active element is exposed between the two ohmic electrodes. Removing a predetermined region of the contact layer separated from each other, and a metal electrode forming step of forming a metal electrode on the active region so as to cover the exposed Schottky layer between the two ohmic electrodes In addition, the removal step and the metal electrode formation step may be performed simultaneously with the formation of the gate electrode of the active element.

  According to this manufacturing method, since the mesa resistance can be increased simultaneously with the recess etching for forming the gate electrode of the FET, the manufacturing cost of the MMIC can be reduced. Moreover, since the semiconductor resistance element whose active region surface is located in the same plane as the surface of the element isolation region is obtained, the spread of the depletion layer from the mesa resistance side wall can be suppressed.

  Here, in the contact layer forming step, a predetermined region of the contact layer may be removed using dry etching which is selective and anisotropic with respect to the Schottky layer separated from the active element.

  According to this manufacturing method, the pattern accuracy of injection separation can be improved, and a fine semiconductor resistance pattern of several microns or less can be produced uniformly and with good reproducibility.

  According to the present invention, in the MMIC using a compound semiconductor, the step of removing the contact layer of the semiconductor resistance element can be performed simultaneously with the gate electrode forming step of the FET, thereby reducing the man-hours and the manufacturing cost. An MMIC including a semiconductor resistance element and an FET can be realized. Furthermore, since the element isolation regions on the left and right of the channel layer of the FET are on the same plane with respect to the active region of the semiconductor resistance element and are formed by injection isolation, the spread of the depletion layer from the mesa resistor side wall is suppressed, A high resistance semiconductor resistance element suitable for miniaturization can be realized.

  The semiconductor resistance element according to the present invention is capable of simultaneously performing the recess etching of the FET and increasing the resistance of the mesa resistance, reducing the number of manufacturing steps, and reducing the manufacturing cost of the MMIC. Therefore, it is possible to realize a low-cost MMIC including a high-resistance semiconductor resistance element and FET, which is useful for applications such as mobile phone terminals.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
Hereinafter, a GaAs MMIC according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A is a top view of an FET as an active element and a semiconductor resistance element as a passive element in the GaAs MMIC of the first embodiment, and FIG. 1B is a cross-sectional view of the FET and the semiconductor resistance element. It is sectional drawing in the X2-X2 'line | wire of Fig.1 (a).

  The FET 110 and the semiconductor resistance element 100 are formed on the same substrate and are element-isolated, that is, electrically isolated by the element isolation region 123.

The FET 110 includes a substrate 101 made of semi-insulating GaAs and an epitaxial layer 109 formed by crystal growth of a semiconductor layer on the substrate 101. The epitaxial layer 109 includes a 1 μm thick buffer layer 102 made of undoped GaAs and a buffer layer 103 made of undoped AlGaAs for relaxing lattice mismatch between the epitaxial layer 109 and the substrate 101. A channel layer 104 made of undoped In _0.2 Ga _0.8 As with a thickness of 20 nm and carrying carriers, a spacer layer 105 made of undoped AlGaAs with a thickness of 5 nm, and only one atomic layer of Si as n-type impurity ions. A carrier supply layer 106 made of planar-doped AlGaAs, a Schottky layer 107 made of undoped AlGaAs with a thickness of 30 nm, and a contact layer 108 made of n ⁺ -type GaAs with a thickness of 100 nm are sequentially stacked. Configured.

  Here, two ohmic electrodes 120 are formed on the contact layer 108. In the region between the two ohmic electrodes 120, the contact layer 108 is etched to a depth at which the Schottky layer 107 is exposed on the surface of the epitaxial layer 109, and the gate electrode 121 is formed on the exposed Schottky layer 107. Has been. Further, the element isolation region 123 includes the channel layer 104, the spacer layer 105, the carrier formed in the channel layer 104, the spacer layer 105, the carrier supply layer 106, and the Schottky layer 107 between the FET 110 and the semiconductor resistance element 100. A groove that penetrates the supply layer 106 and the Schottky layer 107 is formed.

  The semiconductor resistance element 100 includes a semi-insulating substrate 101, a buffer layer 102 and a buffer layer 103 formed on the substrate 101, an active region 115 formed on the buffer layer 103, and a contact layer 108 by an element isolation region 123. And a contact layer 116 formed on the active region 115. The active region 115 is part of the channel layer 104, the spacer layer 105, the carrier supply layer 106, and the Schottky layer 107 separated from the FET 110 by the element isolation region 123, that is, the InGaAs layer 111, the AlGaAs layer 112, and the n-type AlGaAs layer 113. And the AlGaAs layer 114.

  Here, two ohmic electrodes 122 are formed on the contact layer 116. In the region between the two ohmic electrodes 122, the contact layer 116 is etched to a depth that completely removes the contact layer 116, and the AlGaAs layer 114 exposed on the surface of the active region 115 by the etching is formed on the active region 115. Covered with a gate metal 124 formed on the substrate. Further, a thin insulating protective film (not shown) made of SiN or SiO is formed on the GaAs MMIC so as to cover the FET 110 and the semiconductor resistance element 100. At this time, the gate metal 124 is a metal electrode made of the same material as the gate electrode 121 of the FET 110, and is not electrically connected to any circuit and is in a floating state in potential.

  Next, a manufacturing method of the GaAs MMIC having the above structure will be described with reference to the drawings.

2A to 2F are cross-sectional views of a GaAs MMIC.
First, as shown in FIG. 2A, a buffer layer 102, a buffer layer 103, a channel layer 104, a spacer layer 105, a carrier supply layer 106, a Schottky layer are formed on a substrate 101 by using the MOCVD method or the MBE method. The epitaxial layer 109 is formed by sequentially epitaxially growing the contact layer 107 and the contact layer 108.

  Next, as shown in FIG. 2B, a pattern is formed by a photoresist 201 to protect a predetermined position, and for example, a mixed solution of phosphoric acid, hydrogen peroxide solution and water is used for the epitaxial layer 109. The predetermined regions of the contact layer 108, the Schottky layer 107, the carrier supply layer 106, the spacer layer 105, and the channel layer 104 are removed to form an element isolation region 123. As a result, the contact layer 116 and the active region 115 of the semiconductor resistance element 100 are formed.

  Next, as shown in FIG. 2C, after removing the photoresist 201, a pattern is formed with a new photoresist, and an ohmic metal made of Ni / Au / Ge alloy is deposited on the entire surface (not shown). The ohmic electrodes 120 and 122 are formed by lifting off.

Next, as shown in FIG. 2 (d), after forming a photoresist 202, recess etching is performed on the contact layer 108 in a predetermined region between the two ohmic electrodes 120 of the FET 110, thereby opening the opening 203. Form. At the same time, selective wet etching using the AlGaAs layer 114 as a stopper layer is performed on the contact layer 116 between the two ohmic electrodes 122 using the photoresist 202 having an opening pattern wider than the contact layer 116 of the semiconductor resistance element 100. The contact layer 116 is completely removed to form the opening 204. In this recess etching, for example, a mixed solution of citric acid, hydrogen peroxide solution, and water is used. Therefore, the etching selectivity between the Schottky layer 107 and the contact layer 108 is large, and the contact layer 108 portion can be selectively removed. It becomes possible. That is, stable recess etching is possible. The contact layer 108 can be removed anisotropically and selectively with respect to the Schottky layer 107 even by dry etching using a mixed gas of SiCl ₄ , SF ₆ and N _2. Pattern openings 203 can be formed. As a result, the contact layer 116 of the semiconductor resistance element 100 is completely removed, so that a high resistance semiconductor resistance element determined by the amount of the two-dimensional electron gas of HEMT can be obtained.

  Next, as shown in FIG. 2E, a gate metal made of, for example, a Ti / Pt / Au alloy is deposited on the entire surface and lifted off to form the gate electrode 121 on the Schottky layer 107 where the opening 203 is exposed. Form. At the same time, a gate metal 124 is formed on the active region 115 between the two ohmic electrodes 122 so as to cover the AlGaAs layer 114 exposed on the surface of the semiconductor resistance element 100.

  Next, as shown in FIG. 2F, a thin insulating protective film 205 made of SiN or SiO is formed so as to cover the gate electrode 121, Schottky layer 107, contact layer 108 and the like exposed on the surface. To do.

As described above, according to the GaAs MMIC manufacturing method of this embodiment, the recess etching of the FET and the process of increasing the resistance of the semiconductor resistance element are shared. Therefore, man-hours can be reduced and the manufacturing cost of MMIC can be reduced.
(Second Embodiment)
A GaAs MMIC according to a second embodiment of the present invention will be described below with reference to the drawings.

  FIG. 3A is a top view of an FET as an active element and a semiconductor resistance element as a passive element in the GaAs MMIC of the second embodiment, and FIG. 3B is a cross-sectional view of the FET and the semiconductor resistance element. It is sectional drawing in the X3-X3 'line | wire of Fig.3 (a).

  The FET 310 and the semiconductor resistance element 300 are formed on the same substrate and are element-isolated, that is, electrically isolated by the element isolation region 323.

The FET 310 includes a substrate 301 made of semi-insulating GaAs and an epitaxial layer 309 formed by crystal growth of a semiconductor layer on the substrate 301. The epitaxial layer 309 includes a 1 μm-thick buffer layer 302 made of undoped GaAs and a buffer layer 303 made of undoped AlGaAs for relaxing lattice mismatch between the epitaxial layer 309 and the substrate 301. A channel layer 304 made of undoped In _0.2 Ga _0.8 As with a thickness of 20 nm and carrying carriers, a spacer layer 305 made of undoped AlGaAs with a thickness of 5 nm, and only one atomic layer of Si as n-type impurity ions. A carrier supply layer 306 made of planar doped AlGaAs, a Schottky layer 307 made of undoped AlGaAs with a thickness of 30 nm, and a contact layer 308 made of n ⁺ type GaAs with a thickness of 100 nm are sequentially stacked. Configured.

  Here, two ohmic electrodes 320 are formed on the contact layer 308. In the region between the two ohmic electrodes 320, the contact layer 308 is etched to a depth at which the Schottky layer 307 is exposed on the surface of the epitaxial layer 309, and the gate electrode 321 is formed on the exposed Schottky layer 307. Has been. Further, the element isolation region 323 includes impurity regions formed in the channel layer 304, the spacer layer 305, the carrier supply layer 306, and the Schottky layer 307 between the FET 310 and the semiconductor resistance element 300.

  The semiconductor resistance element 300 includes a semi-insulating substrate 301, a buffer layer 302 and a buffer layer 303 formed on the substrate 301, an active region 315 formed on the buffer layer 303, and a contact layer 308 by an element isolation region 323. And a contact layer 316 formed on the active region 315. The active region 315 is a part of the channel layer 304, the spacer layer 305, the carrier supply layer 306, and the Schottky layer 307 separated from the FET 310 by the element isolation region 323, that is, the InGaAs layer 311, the AlGaAs layer 312, and the n-type AlGaAs layer 313. And an AlGaAs layer 314.

  Here, two ohmic electrodes 322 are formed on the contact layer 316. Further, in the region between the two ohmic electrodes 322, the contact layer 316 is etched to a depth that completely removes the contact layer 316, and the AlGaAs layer 314 exposed on the surface of the active region 315 by the etching is formed on the active region 315. It is covered with a gate metal 324 formed. Further, a thin insulating protective film (not shown) made of SiN or SiO is formed on the GaAs MMIC so as to cover the FET 310 and the semiconductor resistance element 300. Furthermore, the surface of the active region 315, that is, the surface of the AlGaAs layer 314 and the surface of the element isolation region 323 are located in the same plane with almost no step. Thereby, the spread of the depletion layer from the side wall of the semiconductor resistance element 300 can be suppressed. At this time, the gate metal 324 is a metal electrode made of the same material as the gate electrode 321 of the FET 310 and is not electrically connected to any circuit and is in a floating state in potential.

  Next, a manufacturing method of the GaAs MMIC having the above structure will be described with reference to the drawings.

4A to 4F are cross-sectional views of the GaAs MMIC.
First, as shown in FIG. 4A, a buffer layer 302, a buffer layer 303, a channel layer 304, a spacer layer 305, a carrier supply layer 306, a Schottky layer are formed on a substrate 301 by using the MOCVD method or the MBE method. The epitaxial layer 309 is formed by sequentially epitaxially growing the contact layer 307 and the contact layer 308.

Next, as shown in FIG. 4B, a pattern is formed by a photoresist 401 to protect a predetermined position, and a mixed gas of, for example, SiCl ₄ , SF ₆ , and N ₂ is used for the epitaxial layer 309. Dry etching is performed to remove a predetermined region of the contact layer 308. After that, using the photoresist 401 as it is, for example, boron is ion-implanted, so that the element isolation region 323 reaching below the channel layer 304 is formed into the Schottky layer 307, the carrier supply layer 306, the spacer layer 305, and the channel layer 304. It is formed in a predetermined area. As a result, the contact layer 316 and the active region 315 of the semiconductor resistance element 300 are formed. At this time, the Schottky layer 307 functions as a stopper layer in the dry etching, and the contact layer 308 can be removed anisotropically and selectively with respect to the Schottky layer 307, so that it is the same as in the first embodiment. Also by this method, it is possible to form a semiconductor resistance element 300 that has been subjected to fine processing by performing highly accurate etching and ion implantation on a fine pattern.

  Next, as shown in FIG. 4C, after removing the photoresist 401, a pattern is formed with a new photoresist, and an ohmic metal made of a Ni / Au / Ge alloy is deposited on the entire surface (not shown). The ohmic electrodes 320 and 322 are formed by lifting off.

Next, as shown in FIG. 4D, after forming a photoresist 402, recess etching is performed on the contact layer 308 in a predetermined region between the two ohmic electrodes 320 of the FET 310, thereby opening the opening 403. Form. At the same time, selective wet etching using the AlGaAs layer 314 as a stopper layer is performed on the contact layer 316 between the two ohmic electrodes 322 by using the photoresist 402 having an opening pattern wider than the contact layer 316 of the semiconductor resistance element 300. Then, the contact layer 316 is completely removed to form an opening 404. In this recess etching, for example, a mixed solution of citric acid, hydrogen peroxide solution, and water is used. Therefore, the etching selectivity between the Schottky layer 307 and the contact layer 308 is large, and the contact layer 308 portion can be selectively removed. It becomes possible. That is, stable recess etching is possible. Note that the contact layer 308 can be anisotropically and selectively removed from the Schottky layer 307 even by dry etching using a mixed gas of SiCl ₄ , SF ₆ and N _2. Pattern openings 403 can be formed. As a result, the contact layer 316 of the semiconductor resistance element 300 is completely removed, so that a high resistance semiconductor resistance element determined by the amount of the two-dimensional electron gas of HEMT can be obtained.

  Next, as shown in FIG. 4E, a gate metal made of, for example, a Ti / Pt / Au alloy is deposited on the entire surface and lifted off to form the gate electrode 321 on the Schottky layer 307 where the opening 403 is exposed. Form. At the same time, a gate metal 324 is formed on the active region 315 between the two ohmic electrodes 322 so as to cover the AlGaAs layer 314 exposed on the surface of the semiconductor resistance element 300.

  Next, as shown in FIG. 4F, a thin insulating protective film 405 made of SiN or SiO is formed so as to cover the gate electrode 321, the Schottky layer 307, the contact layer 308 and the like exposed on the surface. To do.

  As described above, according to the GaAs MMIC manufacturing method of the present embodiment, the recess etching of the FET and the process of increasing the resistance of the semiconductor resistance element are shared. Therefore, man-hours can be reduced and the manufacturing cost of MMIC can be reduced.

Further, according to the GaAs MMIC manufacturing method of the present embodiment, the contact layer 308 is anisotropic with respect to the Schottky layer 307 by dry etching using a mixed gas of SiCl ₄ , SF ₆ and N ₂ , for example. Since it can be selectively removed, the pattern accuracy of the impurity implantation region for forming the element isolation region 323 can be improved, and fine semiconductor resistance elements of several microns or less can be manufactured uniformly and with good reproducibility.

  In the above description, an example using a GaAs / InGaAs-based epitaxial layer has been described, but it goes without saying that other InP-based and other heterosystems have the same effect.

  The present invention can be used for a semiconductor resistance element and a manufacturing method thereof, and in particular, for a GaAs MMIC including an FET and a high resistance semiconductor resistance element.

(A) It is a top view of FET and semiconductor resistance element in GaAs MMIC of the 1st Embodiment of this invention. (B) It is sectional drawing (sectional drawing in the X2-X2 'line | wire of Fig.1 (a)) of FET of the same embodiment and a semiconductor resistance element. It is sectional drawing which shows the manufacturing method of the GaAs MMIC of the embodiment. (A) It is a top view of FET and the semiconductor resistance element in the GaAs MMIC of the 2nd Embodiment of this invention. (B) It is sectional drawing (sectional drawing in the X3-X3 'line | wire of Fig.3 (a)) of FET of the same embodiment and a semiconductor resistance element. It is sectional drawing which shows the manufacturing method of the GaAs MMIC of the embodiment. (A) It is a top view of FET and semiconductor resistance element in the conventional GaAs MMIC. (B) It is sectional drawing (sectional drawing in the X1-X1 'line | wire of Fig.5 (a)) of conventional FET and a semiconductor resistance element. It is sectional drawing which shows the manufacturing method of the conventional GaAs MMIC.

Explanation of symbols

1, 101, 301 Substrate 2, 3, 102, 103, 302, 303 Buffer layer 4, 104, 304 Channel layer 5, 105, 305 Spacer layer 6, 106, 306 Carrier supply layer 7, 107, 307 Schottky layer 8 , 18, 108, 116, 308, 316 Contact layer 9, 109, 309 Epitaxial layer 10, 24, 120, 122, 320, 322 Ohmic electrode 11, 121, 321 Gate electrode 13, 111, 311 InGaAs layer 14, 112, 312 AlGaAs layer 15, 113, 313 n-type AlGaAs layer 16, 114, 314 AlGaAs layer 17, 115, 315 Active region 21, 100, 300 Semiconductor resistance element 22, 110, 310 FET
23, 123, 323 Element isolation region 33, 205, 405 Insulating protective film 30, 31, 201, 202, 401, 402 Photoresist 32, 203, 204, 403, 404 Opening 124, 324 Gate metal

Claims (7)

Formed on the same substrate as an active element having a channel layer, a Schottky layer formed on the channel layer, and a gate electrode formed on the Schottky layer;
An active region having a part of the Schottky layer and the channel layer separated from the active element by an element isolation region;
A contact layer and a metal electrode formed on the active region;
Two ohmic electrodes formed on the contact layer,
The Schottky layer is exposed between the two ohmic electrodes,
The metal resistor is made of the same material as the gate electrode, and covers the exposed Schottky layer between the two ohmic electrodes. 2. The semiconductor resistance element according to claim 1, wherein the metal electrode is not electrically connected to any circuit and is in a floating state in potential. The semiconductor resistance element according to claim 1, wherein the surface of the active region is located in the same plane as the surface of the element isolation region. The semiconductor resistance element according to claim 3, wherein the element isolation region is formed by boron ion implantation. Manufacturing method of semiconductor resistance element formed on same substrate as active element having channel layer, Schottky layer formed on channel layer, contact layer and gate electrode formed on Schottky layer Because
Forming a photoresist pattern on the contact layer, removing a predetermined region of the contact layer using the photoresist pattern, and separating a part of the contact layer from the active element; and
Etching using the photoresist pattern forms an element isolation region in the Schottky layer and channel layer, and forms an active region having a part of the Schottky layer and channel layer separated from the active element An active region forming step,
Forming an ohmic electrode on the contact layer separated from the active element;
Removing a predetermined region of the contact layer separated from the active element such that a Schottky layer separated from the active element is exposed between the two ohmic electrodes;
Forming a metal electrode on the active region so as to cover an exposed Schottky layer between the two ohmic electrodes,
The removal step and the metal electrode formation step are performed simultaneously with the formation of the gate electrode of the active element. On the same substrate as the active element having a channel layer, a Schottky layer formed on the channel layer, a contact layer formed on the Schottky layer, and a gate electrode formed on the Schottky layer A method of manufacturing a semiconductor resistance element formed in
Forming a photoresist pattern on the contact layer, removing a predetermined region of the contact layer using the photoresist pattern, and separating a part of the contact layer from the active element; and
By performing ion implantation using the photoresist pattern, an element isolation region is formed in the Schottky layer and the channel layer, and a part of the Schottky layer, the channel layer, and the contact layer separated from the active element is included. An active region forming step of forming an active region;
Forming an ohmic electrode on the contact layer separated from the active element;
Removing a predetermined region of the contact layer separated from the active element such that a Schottky layer separated from the active element is exposed between the two ohmic electrodes;
Forming a metal electrode on the active region so as to cover an exposed Schottky layer between the two ohmic electrodes,
The removal step and the metal electrode formation step are performed simultaneously with the formation of the gate electrode of the active element. The predetermined region of the contact layer is removed by using selective and anisotropic dry etching with respect to the Schottky layer separated from the active element in the contact layer forming step. 6. A method for producing a semiconductor resistance element according to 6.

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