JP2007335586A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a constitution in which a transistor for a switch and the transistor for a power amplifier are integrated in one chip, and each has characteristics required for each. <P>SOLUTION: A semiconductor integrated circuit device comprises the transistor 2 for the switch by a junction-gate field-effect transistor constitution and the transistor 3 for the power amplifier by a metamorphic hetero-junction bipolar transistor constitution. Consequently, these transistors are formed on the same substrate 1; and can be realized as an integrated module with a low on resistance, high breakdown strength, low-loss switch, and the power amplifier having a high-speed operation and a high-current gain. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which an antenna switch and a power amplifier are formed on the same chip, and a method for manufacturing the semiconductor integrated circuit device.

Conventionally, as a transistor used in an antenna switch module for a portable communication device, a low-loss, low on-resistance junction gate field effect transistor required for this is used.
This junction gate field effect transistor can increase the thickness of the diffusion gate formation layer (cap layer) on the channel layer while keeping the distance between the channel of the field effect transistor and the lower surface of the effective gate close. In addition, a low on-resistance and a high breakdown voltage can be obtained.
Typical examples of the junction gate field effect transistor include the transistors described in Patent Documents 1 and 2, for example.

  On the other hand, as a transistor used in a power amplifier module for portable communication devices, a heterojunction bipolar transistor (HBT) or a high electron mobility transistor (PHEMT) capable of obtaining high gain and high power handling characteristics is used. Typical examples of the power amplifier HBT include the transistors described in Patent Documents 3 and 4.

As described above, different devices are usually used for the antenna switch and the power amplifier, and these are manufactured and mounted on different chips.
On the other hand, if a switch / power amplifier integrated module in which an antenna switch and a power amplifier are integrated on a single chip can be configured, the overall chip size can be reduced, the cost can be reduced, and the reliability can be improved by reducing the number of parts. The
However, conventionally, in such a switch / power amplifier integrated module, in order to form each of the transistors so as to exhibit the high performance required for each of the above, the switch transistor and the power transistor are separately formed. It was necessary and difficult to realize.

For example, Si CMOS, GaAs FET, GaAs HEMT, etc. are used as an attempt to integrate a switch and a power amplifier on one chip.
For example, Non-Patent Document 1 proposes a GaAs MESFET.
A non-patent document 2 proposes a GaAs switch and a CMOS buffer amplifier.
Non-Patent Document 3 describes the use of CMOS.
Non-Patent Document 4 describes the use of GaAs PHEMT.
A switch using Si BJT as a switch and SiGe HBT as an amplifier is disclosed in FIG.
An integrated structure of the Si CMOS switch and the GaN FET is disclosed in FIG.
Further, the InGaAs / InP MISFET and HBT having a Darlington pair configuration are disclosed in FIG. 3 of Patent Document 7, and the HBT switch and the HEMT low noise amplifier are disclosed in FIG. 4 of Patent Document 8, respectively. .
Japanese Patent Application No. 10-2558989 JP-A-11-150264 JP-A-7-106343 JP-A-11-288946 JP 2000-332547 A JP 2004-281454 A US Pat. No. 5,187,110 US Pat. No. 5,554,865 O'Sullivan, P .; St Onge, G .; Heaney, E .; McGrath, F .; Kermarrec, C .; GalliumArsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual 10-13 Oct . 1993 Page (s): 33-35 Urata, R .; Nathawad, LY; Kai Ma; Takahashi, R .; Miller, DAB; Wooley, BA; Harris, JSJr .; Lasersand Electro-Optics Society, 2002. LEOS 2002. The 15th Annual Meeting of the IEEE Volume 2 , 10-14 Nov. 2002 Page (s): 809-810 vol.2 Point, R .; Zhenbiao Li; Foley, W .; Ingersoll, B .; Borelli, J .; Segarra, D .; Donoghue, D .; Liss, C .; Mendes, M .; Feigin, J .; Georgiadis, A .; Valery, M .; Dawe, E .; Losanno, D .; Quintal, R .; Nikitin, M .; Jabor, R .; Morin, M .; O, KK; Dawe, G .; RadioFrequency Integrated Circuits (RFIC) Symposium, 2003 IEEE 8-10 June 2003 Page (s): 431-434 Morkner, H .; Ruby, R .; Frank, M .; Figueredo, D .; MicrowaveSymposium Digest, 1999 IEEE MTT-S International Volume 4, 13-19 June 1999 Page (s): 1393-1396 vol.4

As described above, many attempts have been made to integrate switch transistors and power amplifier transistors on one chip.
However, each of the switch and power amplifier, both those that use Si-based materials that are easy to integrate, those that make up the switch and power amplifier with the same device, and those that use different elements for the switch and power amplifier, Is not composed of optimized ones.

  The present invention relates to a semiconductor integrated circuit device and a semiconductor integrated circuit device using a switch / power amplifier integrated module in which a switch transistor and a power amplifier transistor are integrated on a single chip and each has a characteristic required for each. A manufacturing method is provided.

The present invention is a semiconductor integrated circuit device in which a switch circuit section and a power amplifier circuit section are formed on the same substrate, wherein the transistors of the switch circuit section have a junction gate field effect transistor configuration, and the power amplifier circuit A part of the transistors is a metamorphic heterojunction bipolar transistor configuration.
In the semiconductor integrated circuit device according to the present invention, the junction gate field-effect transistor of the switch circuit unit is composed of a high electron mobility transistor.

  In the semiconductor integrated circuit device according to the present invention, the junction gate field effect transistor of the switch circuit section is formed on at least a channel layer made of InGaAs, an electron supply layer made of AlGaAs, a gate formation layer made of AlGaAs, and the gate formation layer. And a gate electrode contact region formed by introducing an impurity having a conductivity type different from the conductivity type of the gate formation layer, and a gate electrode formed on the gate electrode contact region.

  In the semiconductor integrated circuit device according to the present invention, the junction gate field effect transistor of the switch circuit section is formed on at least a channel layer made of InGaAs, an electron supply layer made of AlGaAs, a gate formation layer made of AlGaAs, and the gate formation layer. And a gate electrode contact region formed by introducing an impurity having a conductivity type different from the conductivity type of the gate formation layer, and a gate electrode formed on the gate electrode contact region. The heterojunction bipolar transistor has at least a collector layer, a base layer made of InGaAs having an In composition of less than 53%, and an emitter layer made of InGaP, and the base layer has an In composition that lattice-matches with the base layer. The emitter layer and collector layer having As that reduces or eliminates the conduction band discontinuity between the base layer and the collector layer and between the base layer and the emitter layer. It is characterized by having a graded layer made of InGaAsP whose composition is modulated with the concentration of P and the concentration of P.

  Further, the semiconductor integrated circuit device according to the present invention includes the switch circuit at a depth from the InGaAsP graded layer to the InGaAs base layer between the emitter layer and the base layer of the metamorphic heterojunction bipolar transistor of the power amplifier circuit unit. And a base electrode contact region having the same structure as that of the gate electrode contact region obtained by introducing the impurity of the junction gate field effect transistor in a portion, and a base electrode is formed on the base electrode contact region.

  A method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device in which a switch circuit portion and a power amplifier circuit portion are formed on the same substrate, wherein the switch circuit portion is formed on the substrate. Epitaxial growth of the first stacked semiconductor layer constituting the junction gate field-effect transistor and epitaxial growth of the second stacked semiconductor layer constituting the metamorphic heterojunction bipolar transistor of the power amplifier circuit portion are performed thereon. An epitaxial growth step, and thereafter an etching step for forming an emitter mesa, an etching step for forming a base mesa in the formation portion of the metamorphic heterojunction bipolar transistor, and the above-mentioned on the formation portion of the junction gate field effect transistor of the switch circuit. Second laminated semiconductor Is etched, characterized in that a step of forming a junction gate field effect transistor of the switch circuit according to the first stacked semiconductor layer.

  In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first stacked semiconductor layer includes at least a channel layer made of InGaAs, an electron supply layer made of AlGaAs, and a gate formation layer made of AlGaAs. The stacked semiconductor layer includes at least a collector layer, a base layer made of InGaAs having an In composition smaller than 53%, the base layer comprising an emitter layer made of InGaP having an In composition lattice-matched to the base layer, and the base layer. Between the base layer and the collector layer, and between the base layer and the emitter layer, it is composed of InGaAsP whose composition is modulated by an As concentration and a P concentration that reduce or eliminate conduction band discontinuity between these layers. And a graded layer.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device comprising: a gate electrode contact between a gate forming layer of a junction gate field effect transistor of the switch circuit and a base layer of a metamorphic heterojunction bipolar transistor of the power amplifier circuit; A step of introducing an impurity having a conductivity type different from the conductivity type of the gate formation layer and the base layer to simultaneously form the region and the base electrode contact region, and a gate electrode on the gate electrode contact region and the base electrode contact region And the base electrode are formed in the same process.

  The method for manufacturing a semiconductor integrated circuit device according to the present invention is characterized in that the epitaxial growth of the first stacked semiconductor layer and the second epitaxial growth are performed by continuous epitaxial growth.

  According to the semiconductor integrated circuit device of the present invention, the transistor in the switch circuit section, that is, the switching transistor is configured by a junction gate field effect transistor, and the transistor in the power amplifier circuit section, that is, the power transistor is configured by a heterojunction bipolar transistor. Thus, a switch / power amplifier integrated module in which a switch transistor and a power amplifier transistor are integrated on the same substrate can be configured.

By configuring the switching transistor using a high electron mobility transistor (HEMT), the thickness of the gate formation layer on the channel layer can be increased while keeping the distance from the lower surface of the effective gate close. On-resistance, low loss, and high breakdown voltage can be obtained, and characteristics desired as a switching transistor can be obtained.
Then, as will become clear from the following description, by configuring the power amplifier transistor as a metamorphic heterojunction bipolar transistor, current gain is maintained while maintaining high-speed operation on the same substrate as the switch transistor, for example, a GaAs substrate. Thus, it is possible to build in a power amplifier transistor in which the increase in the number is increased.
That is, a switch / power amplifier integrated module having the desired characteristics in both the switch transistor and the power transistor is configured.

  According to the manufacturing method of the present invention, the transistor in the switch circuit section, that is, the switching transistor is configured by a junction gate field effect transistor, and the transistor in the power amplifier circuit section, that is, the power transistor is configured by a heterojunction bipolar transistor. As a result, these transistors can be formed on the same substrate by epitaxial growth, and a semiconductor integrated circuit device using a switch / power amplifier integrated module can be constructed with a simplified manufacturing method and high performance.

Embodiments of a semiconductor integrated circuit device and a method of manufacturing a semiconductor integrated circuit device according to the present invention will be described, but the present invention is not limited to this embodiment.
FIG. 1 is a schematic cross-sectional view of an embodiment of a semiconductor integrated circuit device constituting an antenna switch / power amplifier integrated module for a communication device such as a portable communication device according to the present invention.
The semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which a switch circuit portion and a power amplifier circuit portion are formed on the same substrate 1, and the switching transistor 2 of the switch circuit portion is connected to the junction gate field effect. A transistor, for example, a high electron mobility transistor (J-FET), and a power amplifier transistor 3 in the power amplifier circuit section, for example, a double heterojunction metamorphic heterojunction bipolar transistor (D-HBT). Thus, both transistors 2 and 3 can be integrally formed on the same substrate 1 by epitaxial growth.

  In a semiconductor integrated circuit device according to the present invention, a first laminated semiconductor layer 20 in which each semiconductor layer constituting a switching transistor 2 is formed is formed on a substrate 1, and a power amplifier transistor is formed thereon. The second semiconductor layer 30 is formed.

  In this example, a first buffer layer 4, a barrier layer 5, an electron supply layer 6, a spacer layer 7, a channel layer 8, a pacer layer 9, an electron supply layer 10, and a gate formation layer 11 are formed on a semi-insulating GaAs substrate 1. A first stacked semiconductor layer 20 is sequentially stacked by epitaxial growth.

  Then, on the gate forming layer 11 of the first stacked semiconductor layer 20, the second buffer layer 12, the subcollector layer 13, the collector layer 14, the first graded layer 15, the base layer 16, and the second gray layer. A second stacked semiconductor layer 30 is formed in which the dud layer 17, the emitter layer 18, and the emitter contact layer 19 are sequentially stacked by epitaxial growth.

The first buffer layer 4 of the first stacked semiconductor layer 20 is made of undoped AlxGa1 _- xAs (x = 0 to 0.3) having a thickness of 500 nm to 1000 nm, for example, 600 nm.
The barrier layer 5 is made of undoped Al _0.2 Ga _0.8 As having a thickness of 200 nm.
Each of the electron supply layers 6 and 10 is made of Al _0.2 Ga _0.8 As having a thickness of 2 nm to 10 nm, for example, 3 nm, and an impurity concentration of 3 × 10 ¹⁸ cm ³ Si.
The spacer layers 7 and 9 are made of undoped Al _0.2 Ga _0.8 As having a thickness of 3 nm.
The channel layer 8 is made of undoped InxGa1-xAs (x = 0.1 to 0.3, for example, x = 0.2) having a thickness of 10 to 30 nm, for example, 15 nm.
The gate forming layer 11 is made of Si-doped Al _0.2 Ga _0.8 As having a thickness of 50 to 200 nm, for example, 130 nm and an impurity concentration of 5 × 10 ¹⁶ cm ³ , for example.

The second buffer layer 12 of the second stacked semiconductor layer 30 is made of, for example, InP, InP, InGaAs, InAlAs, InGaP, or the like, and from the GaAs substrate 1 side to the second stacked semiconductor layer subcollector layer 13 side. An appropriate structure (composition change) is set according to the material composition and lattice constant of the gate forming layer 11 and the material composition and lattice constant of each layer formed thereon. The
The second buffer layer 12 achieves lattice matching with the sub-collector layer 13 of the second stacked semiconductor layer 30 on the gate forming layer 11 of the first stacked semiconductor layer 20. That is, by providing the second buffer layer 12, a metamorphic heterojunction bipolar transistor of the power amplifier transistor 3 having a lattice constant different from that of the substrate 1 is formed on the semiconductor layer forming the switching transistor 2. Each semiconductor layer can be epitaxially grown while suppressing the occurrence of crystal defects.

  The subcollector layer 13 to the emitter contact layer 19 of each semiconductor layer constituting the metamorphic heterojunction bipolar transistor of the power amplifier transistor 3 are lattice-matched so as to have a lattice constant equal to that of the base layer 16.

The metamorphic heterojunction bipolar transistor of the power amplifier transistor 3 can have a double heterojunction bipolar transistor (D-HBT) configuration proposed in Japanese Patent Application No. 2005-17624 filed by the present applicant.
That is, the D-HBT has a composition in which the In composition is larger than 0% and smaller than 53% in the base layer 16 made of InGaAs.
The In composition of the base layer 16 made of InGaAs is determined by the high-speed operation performance and current gain required for the metamorphic heterojunction bipolar transistor. That is, the speed is further increased by increasing the In composition, and the current gain is increased by decreasing the In composition, and these relationships are a trade-off. Here, in order to obtain both high-speed operation performance and current gain, the In composition of the base layer 16 is preferably 30% to 40%.
In this embodiment, the base layer 16 is made of p-type InGaAs having an In composition of 40% and a lattice constant between GaAs and InP, and has a thickness of 20 nm to 100 nm, for example, 75 nm. As the p-type impurity, for example, C (carbon) is used, and the concentration thereof is 5 × 10 ¹⁸ cm ⁻³ to 4 × 10 ¹⁹ cm ⁻³ , for example, 2 × 10 ¹⁹ cm ⁻³ .

The subcollector layer 13 is composed of an n-type InGaAs layer having a lattice constant equal to that of the base layer 16. That is, the subcollector layer 13 is made of InGaAs having an In composition of 40% with the same composition as the base layer 16, and an n-type impurity such as Si is 5 × 10 ¹⁸ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ , for example, 1 It is set as the structure which doped n-type impurity to * 10 < ¹⁹ > cm < ^-3 >. And the film thickness shall be 100 nm-500 nm, for example, 300 nm.

The collector layer 14 is also made of n-type InGaP having a lattice constant equal to that of the base layer 16. The In composition in the collector layer 14 is greater than 49% and less than 100%, and more preferably, the In composition is set between 77% and 88%. Here, InGaP having an In composition of 87% is used as the collector layer 14 in accordance with the lattice constant of the base layer 16 made of InGaAs having an In composition of 40%, and the film thickness is set to 200 nm to 600 nm, for example, 450 nm. Further, as the n-type impurity, for example, Si is used, and the impurity concentration is set to 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁶ cm ⁻³ , for example, 2 × 10 ¹⁶ cm ⁻³ .

The emitter layer 18 disposed above the base layer 16 is also composed of n-type InGaP having a lattice constant equal to that of the base layer 16. For this reason, the In composition in the emitter layer 18 is set to be greater than 49% and less than 100%, more preferably between 77% and 88%. Here, in accordance with the lattice constant of the base layer 16 made of InGaAs having an In composition of 40%, InGaP having an In composition of 87% is used as the emitter layer 18, and the film thickness thereof is set to 20 nm to 100 nm, for example, 60 nm. For example, Si is used as the n-type impurity, and the impurity concentration is set to 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , for example, 5 × 10 ¹⁷ cm ⁻³ .

The emitter contact layer 19 is made of n-type InGaAs having the same In composition and lattice constant as the base layer 16, and the thickness thereof is set to 10 nm to 100 nm, for example, 75 nm. For example, Si is used as the n-type impurity, and the concentration thereof is set to 5 × 10 ¹⁸ cm ^{−3 to} 3 × 10 ¹⁹ cm ⁻³ , for example, 1 × 10 ¹⁹ cm ⁻³ .

The first graded layer 15 arranged between the collector layer and the base layer described above is made of n-type InGaAsP maintained at the same lattice constant as that of the base layer 16.
The composition of the first graded layer 15 is modulated by the concentration of As and the concentration of P so as to substantially eliminate the conduction band discontinuity between the collector layer 14 and the base 16 layer.
The closer to the collector layer 14 made of InGaP, the lower the As composition, and the closer to the InGaAs base layer 16, the lower the P composition.
In this way, the composition is modulated so that the composition is continuous with the collector layer made of InGaP at the interface with the collector layer 14 and the composition is continuous with the base layer 16 made of InGaAs at the interface with the base layer 16.
For example, as described above, when the collector layer 14 is made of InGaP having an In composition of 87% and the base layer 16 is made of InGaP having an In composition of 40%, the first graded layer 15 has the base layer from the collector layer 14 side. The In composition gradually decreases from 87% to 40% toward the 16 side, and As gradually increases from 0% to 100%.
The film thickness of the first graded layer 15 is 20 nm to 100 nm, for example, 45 nm.
As this n-type impurity, for example, Si is used, and its concentration is set to 1 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁶ cm ^−3, for example, 2 × 10 ¹⁶ cm ⁻³ .

On the other hand, the second graded layer 17 disposed between the base layer 16 and the emitter layer 18 is also n-type maintained at the same lattice constant as the base layer 16 as in the first graded layer 15. Of InGaAsP.
The composition of the second graded layer 17 is modulated by the concentration of As and the concentration of P so as to substantially eliminate the conduction band discontinuity between the base layer 16 and the emitter layer 18.
In this case, the closer the InGaP emitter layer 18 is, the lower the As composition is, and the closer the InGaAs base layer 16 is, the lower the P composition. At the interface with the emitter layer 18, the composition is continuous with the InGaP emitter layer. The composition of the interface with the layer 16 is modulated so that the composition is continuous with that of the InGaAs base layer 16.
For example, as described above, when the emitter layer 18 is made of InGaP with an In composition of 87% and the base layer 16 is made of InGaAs with an In composition of 40%, the second graded layer 17 has an emitter layer from the base layer 16 side. The In composition gradually increases from 40% to 87% toward the 18th side, and As gradually decreases from 100% to 0%.
The film thickness of the second graded layer 17 is 5 nm to 50 nm, for example, 10 nm.
In addition, as the n-type impurity of the second graded layer 17, for example, Si is used, and the impurity concentration thereof is 1 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁶ cm ⁻³ , for example, 2 × 10 ¹⁶ cm ^{−. 3} .

A gate electrode contact region 41 doped with a p-type impurity of a different conductivity type, for example, Zn, is formed on the gate formation layer 11 of the switching transistor 2, and a gate electrode 42 is formed thereon.
Further, a source electrode 43 and a drain electrode 44 are formed on both sides of the gate electrode at a depth from the gate formation layer 11 to the channel layer 8.

A part of the subcollector 13 of the power amplifier transistor 3 forms a base mesa 45 from the second graded layer 17 to the collector layer 14, and the collector electrode 46 contacts the subcollector layer 13 exposed thereby. Is done.
Further, an emitter mesa 47 is formed in the emitter contact layer 19 and the emitter layer 18, and the base electrode contact region is made to have the same conductivity as the base layer 16 to the depth from the exposed second graded layer 17 to the base layer 16. A p-type impurity of a type is selectively introduced to form a base electrode contact region 48, and a base electrode 49 is contacted thereon.
Further, the emitter electrode 50 is contacted on the emitter electrode contact layer 19.

  In the first stacked semiconductor layer 20 between the switching transistor 2 and the power amplifier transistor 3 having this configuration, an isolation region 51 for electrically separating them is formed by, for example, boron ion implantation.

  In the semiconductor integrated circuit device according to the above-described configuration of the present invention, the switching transistor 2 is a junction gate field effect transistor (J-HEMT), so that the gate contact region is formed on the lower surface of the effective gate, that is, in the configuration of FIG. The gate forming layer 11 on the channel layer 18 can be made thicker while keeping the distance from the lower surface of 41 close, and low on-resistance, low loss and high breakdown voltage can be obtained, which is desirable as a switching transistor. It can be set as a characteristic.

The power amplifier transistor 3 formed on the same substrate 1 as the switching transistor 2 is composed of a metamorphic heterojunction bipolar transistor whose base layer has an InGaAs base layer whose In composition is smaller than 53%. Thus, a switch / power amplifier integrated module having excellent target characteristics is formed.
That is, in the power amplifier transistor described above, the In composition of the base layer is set to be smaller than 53%. However, when the In composition is reduced in the InGaAs base layer as described above, As the decrease, the Auger recombination coefficient approaches the Auger recombination coefficient in GaAs. That is, the recombination coefficient decreases.
Therefore, in the metamorphic heterojunction bipolar transistor having this configuration, the recombination probability in the base layer is higher than that of the InP-based D-HBT in which the In composition of the base layer using the conventional InP substrate is 53%. Since it can be decreased, the current gain can be increased.
At the same time, the carrier mobility can be maintained at a large value as compared with the HBT based on the GaAs base layer using the GaAs substrate.

  In order to realize a base layer having such an In composition, the collector layer 14 and the emitter layer 18 sandwiching the base layer 16 are made of InGaP, and the lattice constants thereof are matched.

  That is, according to the above-described configuration of the present invention, it is possible to increase the current gain while maintaining high-speed operation in comparison with InGaAs / InP D-HBT, AlGaAs / GaAs HBT, and InGaP / GaAs HBT. Thus, a metamorphic heterojunction bipolar transistor that is optimal for improving the performance of a power amplifier is formed.

Next, an embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention described with reference to FIG. 1 will be described with reference to the process diagrams of FIGS.
First, as shown in FIG. 2, the first laminated semiconductor layer 20 and the second laminated semiconductor layer 30 constituting the semiconductor integrated circuit device according to the present invention described with reference to FIG. 1 are formed on the semi-insulating GaAs substrate 1. Then, an epitaxial growth process for continuously epitaxially growing on the entire surface is performed.
That is, the first buffer layer 4, the barrier layer 5, the electron supply layer 6, the spacer layer 7, the channel layer 8, the pacer layer 9, the electron supply layer 10, and the gate formation layer 11 are sequentially formed, for example, by MOCVD (Metal Organic Chemical Vapor Deposition). The first stacked semiconductor layer 20 is formed by epitaxial growth.

Subsequently, the second buffer layer 12, the subcollector layer 13, the collector layer 14, the first graded layer 15, and the base layer 16 are continuously formed on the gate forming layer 11 of the first stacked semiconductor layer 20. Similarly, the second graded layer 17, the emitter layer 18, and the emitter contact layer 19 are epitaxially grown by, for example, MOCVD to form the second stacked semiconductor layer 30.
A semiconductor layer lattice-matched on the substrate 1 by selecting the composition, impurity concentration, film thickness, and the like of each of the semiconductor layers 4 to 19 as the composition, impurity concentration, film thickness, and the like described in FIG. A stacked semiconductor substrate 60 is formed by stacking.

Then, an emitter electrode 50 is finally formed on the laminated semiconductor layer substrate 60 at the formation portion of the power amplifier transistor 3.
The emitter electrode 50 is formed by forming an electrode material layer for forming the emitter electrode 50 on the entire surface of the emitter electrode contact layer 19, forming a photoresist on the entire surface, patterning this by photolithography, Ion milling is performed on the electrode material using the formed photoresist as a mask to form an emitter electrode 50 at a desired position and pattern, and then alloyed.
The mitter electrode material layer has, for example, a three-layer structure of Ti / Pt / Au in which titanium, platinum, and gold are sequentially stacked, and each is formed by a deposited film having a thickness of, for example, 50 nm / 50 nm / 250 nm.

  Next, as shown in a schematic cross-sectional view in FIG. 3, for example, the InGaAsP emitter electrode contact layer 19 is pattern-etched with a phosphoric acid-based etchant using the emitter electrode 50 as a mask, and the InGaAs emitter layer 18 exposed by this etching is converted into hydrochloric acid An emitter mesa 27 is formed by etching with a system etchant.

As shown in a schematic cross-sectional view in FIG. 4, the first stacked semiconductor layer 20 in the formation portion of the switching transistor (J-HEMT) 2 described in FIG. 1 is left and left after the formation of the mesa emitter 27 thereon. The second laminated semiconductor layer 30 is removed by etching.
Although this etching is not shown, a photoresist can be formed on the entire surface, patterned by photolithography, and etched with a phosphoric acid etching solution and a hydrochloric acid etching solution using the patterned photoresist as a mask.

  Then, the remaining first stacked semiconductor layer 20 is separated between the formation portion of the power amplifier transistor (HBT) 3 and the finally formed switch transistor 2 and power amplifier transistor. An isolation region 51 is formed. Although the isolation region 51 is not shown in the drawing, for example, a photoresist layer is formed over the entire surface, an opening is formed in the isolation forming portion by photolithography, and the photoresist layer is used as a mask through the opening. It can be formed by oxygen ion implantation.

Next, as shown in FIG. 5, the gate electrode contact region 41 is formed in the gate forming portion of the gate forming layer 11 of the first stacked semiconductor layer 20, and the emitter mesa 24 of the second stacked semiconductor layer 30 is formed to externally. A base electrode contact region 48 is formed in the second graded layer 17 exposed to the depth to reach the base layer 16.
The gate electrode contact region 41 and the base electrode contact region 48 can be formed simultaneously by selective diffusion of zinc (Zn). Although formation of these regions 41 and 48 is not shown, an insulating film such as SiN is deposited on the entire surface to a thickness of 200 nm to 300 nm, for example, 250 nm. Then, pattern etching by photolithography is performed on the insulating layer to form openings in the formation portions of the regions 41 and 48. Then, using this insulating layer as a diffusion mask, the above-described Zn diffusion, for example, through the opening is performed to a concentration of 1 × 10 ¹⁸ cm ⁻³ or more, preferably about 1 × 10 ¹⁹ cm ⁻³ to form a p-type gate. An electrode contact region 41 and a base electrode contact region 48 are formed.

Further, for example, Pt / Ti / Pt / Au four-layer structure in which platinum, titanium, platinum and gold are laminated in this order over the entire surface through an opening of an insulating layer (not shown) in which the regions 41 and 48 are formed. After the electrode metal material layers were deposited to a thickness of 50 nm / 30 nm / 50 nm / 120 nm, the insulating layer was removed, and along with the removal of the insulating layer, the electrode metal agent layer on the insulating layer was lifted off.
In this manner, the gate electrode 42 is formed on the gate electrode contact region 41 and the base electrode 49 is formed on the base electrode contact region 48.

  Next, as shown in FIG. 6, the second graded layer 17, the base layer 16, the first graded layer 15, and the collector layer 14 are crossed across the second collector layer 13 in the formation portion of the power amplifier transistor 3. Etching for forming the base mesa 45 is performed so as to expose the portion. The base mesa 45 can also be formed by patterning using a photoresist mask by photolithography.

As shown in FIG. 1, the source and drain electrodes 43 and 44 are formed on the gate forming layer 11 on both sides of the gate electrode 42, and the sub-collector layer 13 exposed to the outside by the formation of the base mesa 45 is formed. A collector electrode 46 is formed on the surface.
Although the source and drain electrodes 43 and 44 and the collector electrode 46 are not shown in the drawing, the photoresist is patterned by photolithography to form openings in the portions where the source and drain electrodes 43 and 44 and the collector electrode 46 are formed. A patterned photoresist mask is formed. And an electrode metal material layer is vapor-deposited on the whole surface. Thereafter, the photoresist mask layer is removed, and the electrode metal material formed on the photoresist mask layer is patterned by lifting off and alloyed.
The source and drain electrodes 43 and 44 are formed to a depth reaching the channel layer 8.

  Thus, when the drain electrode 43 and the collector electrode are simultaneously formed in the same process, the depth of these alloys is actually the same depth, but the thickness of the gate layer 11 and the subcollector layer 13 are substantially the same. By selecting the relationship with the thickness of the source electrode 43 and the drain electrode 44, the source electrode 43 and the drain electrode 44 can be set to a depth reaching the channel layer 8, and the collector electrode 46 can be set to a depth suitable for contact with the collector layer 13.

In this manner, a semiconductor integrated circuit device is formed by the switch / power amplifier integrated module according to the present invention in which the switch transistor 2 and the power amplifier transistor 3 are formed on the common substrate.
As described above, the semiconductor integrated circuit device according to the present invention formed as described above is an integrated module of a power amplifier having a low on-resistance, a high breakdown voltage, a low loss switch, a high-speed operation, and a high current gain. realizable. Therefore, this module is particularly useful for enhancing the functionality, integration, and cost of the power amplifier module for mobile communication terminals.

  The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention are not limited to the above-described example, and various modifications and changes can be made without departing from the configuration of the present invention. For example, a switch transistor is configured. The junction gate field effect transistor is not limited to the HEMT, and can be a so-called MES-FET configuration using a Schottky gate.

It is a schematic sectional drawing of an example of the semiconductor integrated circuit device by this invention. It is a schematic sectional drawing of one manufacturing process of an example of the manufacturing method of the semiconductor integrated circuit device by this invention. It is a schematic sectional drawing of one manufacturing process of an example of the manufacturing method of the semiconductor integrated circuit device by this invention. It is a schematic sectional drawing of one manufacturing process of an example of the manufacturing method of the semiconductor integrated circuit device by this invention. It is a schematic sectional drawing of one manufacturing process of an example of the manufacturing method of the semiconductor integrated circuit device by this invention. It is a schematic sectional drawing of one manufacturing process of an example of the manufacturing method of the semiconductor integrated circuit device by this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Switch transistor, 3 ... Power transistor, 4 ... 1st buffer layer, 5 ... Barrier layer, 6, 10 ... Electron supply layer, 7, 9 ... Spacer layer , 8... Channel layer, 11... Gate forming layer, 12... Second buffer layer, 13... Subcollector layer, 14... Collector layer, 15. 17 ... Second graded layer, 18 ... Emitter layer, 19 ... Emitter contact layer, 20 ... First laminated semiconductor layer, 30 ... Second laminated semiconductor layer, 41 ... Gate electrode Contact region 42... Gate electrode 43. Source electrode 44. Drain electrode 45. Base mesa 46. Collector electrode 47. Emitter mesa 48 Base electrode 49 Base electrode 50 ...... Emi Electrode, 51 ...... isolation region, 60 ...... laminated semiconductor substrate

Claims (9)

A semiconductor integrated circuit device in which a switch circuit portion and a power amplifier circuit portion are formed on the same substrate,
The transistor of the switch circuit unit is a junction gate field effect transistor configuration,
A semiconductor integrated circuit device, wherein the transistor of the power amplifier circuit section has a metamorphic heterojunction bipolar transistor configuration. 2. The semiconductor integrated circuit according to claim 1, wherein the junction gate field effect transistor of the switch circuit section is constituted by a high electron mobility transistor. The junction gate field effect transistor of the switch circuit unit is different from at least a channel layer made of InGaAs, an electron supply layer made of AlGaAs, a gate formation layer made of AlGaAs, and a conductivity type of the gate formation layer formed in the gate formation layer. 3. The semiconductor integrated circuit device according to claim 2, further comprising: a gate electrode contact region formed by introducing a conductivity type impurity; and a gate electrode formed on the gate electrode contact region. The junction gate field effect transistor of the switch circuit unit is different from at least a channel layer made of InGaAs, an electron supply layer made of AlGaAs, a gate formation layer made of AlGaAs, and a conductivity type of the gate formation layer formed in the gate formation layer. A gate electrode contact region formed by introducing an impurity of a conductive type; and a gate electrode formed on the gate electrode contact region.
The metamorphic heterojunction bipolar transistor of the power amplifier circuit unit has at least a collector layer, a base layer made of InGaAs having an In composition smaller than 53%, and an emitter layer made of InGaP,
The base layer has a configuration sandwiched between the emitter layer and the collector layer each having an In composition lattice-matched to the base layer,
Composition-modulated InGaAsP with As and P concentrations between the base layer and the collector layer and between the base layer and the emitter layer to reduce or eliminate conduction band discontinuities between these layers. The semiconductor integrated circuit device according to claim 1, further comprising a graded layer made of The impurity of the junction gate field effect transistor of the switch circuit unit is formed at a depth from the InGaAsP graded layer to the InGaAs base layer between the emitter layer and the base layer of the metamorphic heterojunction bipolar transistor of the power amplifier circuit unit. 5. The semiconductor integrated circuit device according to claim 4, further comprising a base electrode contact region having the same structure as that of the introduced gate electrode contact region, wherein the base electrode is formed on the base electrode contact region. A method of manufacturing a semiconductor integrated circuit device in which a switch circuit unit and a power amplifier circuit unit are formed on the same substrate,
Epitaxial growth of a first stacked semiconductor layer constituting a junction gate field effect transistor of the switch circuit portion on the substrate, and a second constituting a metamorphic heterojunction bipolar transistor of the power amplifier circuit portion thereon. An epitaxial growth step in which the epitaxial growth of the laminated semiconductor layer is performed;
Thereafter, in the formation part of the metamorphic heterojunction bipolar transistor, an etching process for forming an emitter mesa, an etching process for forming a base mesa, and the second stack on the formation part of the junction gate field effect transistor of the switch circuit And a step of etching the semiconductor layer to form a junction gate field effect transistor of the switch circuit portion by the first laminated semiconductor layer. The first laminated semiconductor layer has at least a channel layer made of InGaAs, an electron supply layer made of AlGaAs, and a gate forming layer made of AlGaAs,
The second stacked semiconductor layer includes at least a collector layer, a base layer made of InGaAs having an In composition smaller than 53%, and the base layer being an emitter layer made of InGaP having an In composition lattice-matched with the base layer. And between the base layer and the collector layer, and between the base layer and the emitter layer, the composition is modulated by the As concentration and the P concentration that reduce or eliminate the conduction band discontinuity between these layers. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, further comprising a graded layer made of InGaAsP. Forming the gate electrode contact region and the base electrode contact region simultaneously on the gate forming layer of the junction gate field effect transistor of the switch circuit and the base layer of the metamorphic heterojunction bipolar transistor of the power amplifier circuit; A step of introducing impurities of a conductivity type different from the conductivity type of the layer and the base layer,
8. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the gate electrode and the base electrode are formed in the same step on the gate electrode contact region and the base electrode contact region. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the epitaxial growth of the first stacked semiconductor layer and the second epitaxial growth are performed by continuous epitaxial growth.

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