JP2010263018A - Method of manufacturing epitaxial wafer for transistor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an epitaxial wafer for a transistor element capable of manufacturing an epitaxial wafer for a transistor element having an excellent electric characteristic without degrading mobility of an epitaxial layer for an HEMT. <P>SOLUTION: In this method of manufacturing an epitaxial wafer 1 for a transistor element, an epitaxial layer 3 for a high-electron-mobility transistor is formed on a substrate 2, and an epitaxial layer 4 for a hetero bipolar transistor is formed on the epitaxial layer 3 for a high-electron-mobility transistor. In the method, the epitaxial layer 3 for a high-electron-mobility transistor is grown at a growth temperature of 600-750&deg;C and at a V/III ratio of 10-150, and the epitaxial layer 4 for a hetero bipolar transistor is grown at low temperature relative to the growth temperature of the epitaxial layer 3 for a high-electron-mobility transistor. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing an epitaxial wafer for transistor elements having good electrical characteristics.

  In recent years, communication terminal devices such as mobile phones are required to transmit and receive not only voice and text data but also large-capacity and diverse information such as moving images at high speed. For this reason, transmission / reception power amplifiers used in these terminal devices are required to support high-speed and high-frequency operation, reduce power consumption, and the like.

  For such a power amplifier for terminal equipment, a hetero bipolar transistor (HBT) or a high electron mobility transistor (HEMT) formed using a compound semiconductor is used.

  The operation of the hetero bipolar transistor (HBT) is basically the same as that of a normal bipolar transistor (BJT).

  In the npn-type BJT, the amount of electrons flowing from the emitter to the collector is controlled by the base current (hole current), thereby operating as a transistor. That is, the collector current increases by increasing the Hall current. However, in the npn-type BJT, when the hole current is further increased, holes leak from the base toward the emitter, and there is a problem that the current amplification factor of the transistor is lowered.

  On the other hand, in an npn type HBT configured using a semiconductor material having a large band gap for the emitter, since a barrier is formed at the base-emitter interface, leakage of holes to the emitter can be suppressed. Therefore, in the HBT, the collector current can be increased without reducing the current amplification factor.

As shown in FIG. 5, the conventional HBT element 50 has a semi-insulating GaAs substrate 51 with an n-GaAs layer serving as a subcollector layer 52 having a thickness of 500 nm and an n-GaAs layer serving as a collector layer 53 having a thickness. 700 nm thick, the p-GaAs layer serving as the base layer 54 is 80 nm thick, the n-In _x Ga _1-x P layer (x = 0.48) serving as the emitter layer 55 is 40 nm, and the n − serving as the emitter contact layer 56. The GaAs layer is 100 nm, the n-In _x Ga _1-x As layer (x = 0 to 0.5) to be the graded non-alloy layer 57 is 50 nm, and the n-In _x Ga _1-x As layer to be the uniform composition non-alloy layer 58 (X = 0.5) are stacked in order of 50 nm.

  On the other hand, the HEMT has an InGaAs layer as a channel layer and has an electron supply layer on both sides or one side of the channel layer. The heterojunction HEMT not only enables high-speed operation by taking advantage of the high-speed movement of electrons, but also enables high-power and high-efficiency operation in an ultra-high frequency band such as a microwave band.

As shown in FIG. 6, the conventional HEMT device 61 includes an undoped GaAs buffer layer 63, an n-Al _x Ga _1-x As electron supply layer 64, an undoped Al _x Ga ₁₋ , on a semi-insulating GaAs substrate 62. _x As spacer layer 65, undoped In _x Ga _1-x As channel layer 66, undoped Al _x Ga _1-x As spacer layer 67, n-Al _x Ga _1-x As electron supply layer 68, n-GaAs cap layer 69 Are sequentially laminated.

  In the HEMT, by increasing the amplification efficiency, it is possible to operate at a low voltage and meet the demand for reduction in power consumption. However, when operating with a high amplification factor, there is a problem that distortion occurs in the output signal.

  Therefore, an HBT having a high current driving capability and a HEMT having low power consumption and good high-frequency noise characteristics are used in one amplifier module to suppress output signal distortion and reduce power consumption. For example, Patent Document 1 discloses an integrated transistor element in which an HBT epitaxial layer is formed on a GaAs substrate, and an HEMT epitaxial layer is formed on the HBT epitaxial layer.

JP 2006-228784 A

  However, in the transistor element structure as in Patent Document 1, the HEMT epitaxial layer is grown on the HBT epitaxial layer, and therefore the HBT epitaxial layer is grown at the growth temperature when the HEMT epitaxial layer is grown on the HBT epitaxial layer. As a result, the crystallinity of the channel layer or the like deteriorates and the current gain decreases in the HBT epitaxial layer.

  In addition, a transistor element in which an HEMT epitaxial layer is grown on a substrate and an HBT epitaxial layer is grown on the HEMT epitaxial layer has been studied, but the carrier concentration of the electron supply layer of the HEMT epitaxial layer is increased to increase the capacity. If the thickness is too high, there is a problem that the mobility of the HEMT epitaxial layer is lowered.

Therefore, the present inventor has studied the upper limit value of the carrier concentration that does not decrease the mobility of the HEMT epitaxial layer, and the carrier concentration of the electron supply layer of the HEMT epitaxial layer is set to 1 × 10 ¹⁹ cm ⁻³ or less. Thus, it has been proposed that the mobility of the HEMT epitaxial layer can be maintained high (Japanese Patent Application No. 2008-007853).

In the invention of this prior application, in order to increase the capacity, the carrier concentration of the electron supply layer is focused, the relationship between the carrier concentration of the electron supply layer and the mobility of the HEMT epitaxial layer is measured, and the carrier concentration is set to 1 × 10. It has been found that the mobility is lowered even if it is higher than ¹⁹ cm ⁻³ , and that the mobility of the epitaxial layer for HEMT can be kept high by defining the upper limit of the carrier concentration.

  In the further examination, the HEMT epitaxial layer is maintained even when the carrier concentration of the electron supply layer of the HEMT epitaxial layer is kept appropriate when the carrier concentration is defined and the HBT epitaxial layer is grown on the HEMT epitaxial layer. It has been found that the initial mobility is not sufficiently exhibited.

  Accordingly, an object of the present invention is to provide a method for manufacturing an epitaxial wafer for a transistor element, which can manufacture an epitaxial wafer for a transistor element with good electrical characteristics without reducing the mobility of the epitaxial layer for HEMT. is there.

  The present invention was devised to achieve the above object, and the invention of claim 1 forms an epitaxial layer for a high electron mobility transistor on a substrate, and the epitaxial layer for the high electron mobility transistor is formed on the epitaxial layer. In the method for manufacturing an epitaxial wafer for a transistor element for forming an epitaxial layer for a heterobipolar transistor, the epitaxial layer for a high electron mobility transistor is grown at a growth temperature of 600 ° C. or more and 750 ° C. or less and a V / III ratio of 10 or more and 150 or less. And manufacturing the epitaxial wafer for transistor elements by growing the epitaxial layer for heterobipolar transistors at a temperature lower than the growth temperature.

According to a second aspect of the present invention, an epitaxial layer for a high electron mobility transistor is formed on a substrate, and an epitaxial layer for a heterobipolar transistor having a subcollector layer and a collector layer is formed on the epitaxial layer for a high electron mobility transistor. In the method for producing an epitaxial wafer for a transistor element, the epitaxial layer for a high electron mobility transistor is grown at a growth temperature of 600 ° C. or more and 750 ° C. or less, a V / III ratio of 10 or more and 150 or less, by a metal organic chemical vapor deposition method. Growing at 0.1 nm / sec or more and 2.0 nm / sec or less, and growing at least the subcollector layer and the collector layer of the heterobipolar transistor epitaxial layer by a metal organic vapor phase epitaxy method at a growth temperature of 400 ° C. or more and 600 ° C. The V / III ratio is 1 or more and 75 or less. So long is, the sub-collector layer has a carrier concentration of 1 × 10 ¹⁸ cm ^-3 or more 7 × 10 ¹⁸ cm ^-3 or less, and formed to a film thickness of 200nm or more 800nm or less, the collector layer has a carrier This is a method for producing an epitaxial wafer for a transistor element, which is formed so as to have a concentration of 5 × 10 ¹⁵ cm ⁻³ or more and 3 × 10 ¹⁶ cm ⁻³ or less and a film thickness of 400 nm or more and 800 nm or less.

According to a third aspect of the present invention, the epitaxial layer for a high electron mobility transistor has an electron supply layer having a carrier concentration of 5.0 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. 2. A method for producing an epitaxial wafer for transistor elements according to 2.

  The invention of claim 4 is the method for producing an epitaxial wafer for a transistor element according to claim 3, wherein the electron supply layer has a thickness of 1 nm or more and 20 nm or less.

  5. The transistor according to claim 3, wherein the electron supply layer is an n-AlGaAs layer doped with any of Si, Se, or Te, or an n-InGaP layer doped with Si. It is a manufacturing method of the epitaxial wafer for elements.

  According to a sixth aspect of the present invention, a stopper layer having a thickness of 6 nm or more and 12 nm or less is formed between the epitaxial layer for a high electron mobility transistor and the epitaxial layer for a heterobipolar transistor. It is a manufacturing method of the epitaxial wafer for transistor elements as described in above.

  ADVANTAGE OF THE INVENTION According to this invention, the epitaxial wafer for transistor elements with a favorable electrical property can be manufactured.

It is a laminated structure figure of the epitaxial wafer for transistor elements manufactured from this invention. It is a figure which shows the relationship between the carrier concentration of a 1st electron supply layer, and the mobility of the epitaxial layer for high electron mobility transistors. It is a figure which shows the relationship between the film thickness of a stopper layer, and a sheet carrier density | concentration. It is a figure which shows the relationship between the board | substrate maximum temperature at the time of the epitaxial layer growth for HBT, and the mobility of the epitaxial layer for high electron mobility transistors. It is a laminated structure figure of an HBT element. It is a laminated structure figure of a HEMT element.

  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

  First, an epitaxial wafer for a transistor element manufactured according to the present invention will be described.

  FIG. 1 is a stacked structure diagram of an epitaxial wafer for transistor elements manufactured according to the present invention.

As shown in FIG. 1, an epitaxial wafer for transistor element 1 is formed with a high electron mobility transistor epitaxial layer (HEMT epitaxial layer) 3 on a substrate 2 made of semi-insulating GaAs, and the HEMT epitaxial layer. 3 is a heterobipolar transistor epitaxial layer (HBT epitaxial layer) 4 formed on the substrate 3 via a stopper layer 12 made of an n-In _x Ga _1-x P layer (x = 0.48). -FET (registered trademark) structure).

The HEMT epitaxial layer 3 is an un-Al _x Ga _1-x As layer (x = 0.28) serving as the buffer layer 5 having a thickness of 500 nm, and an n-Al _x Ga _{1-x serving as} the first electron supply layer 6. The As layer (x = 0.3) has a thickness of 15 nm, and the un-Al _x Ga _1-x As layer (x = 0.3) that becomes the spacer layer 7 has a thickness of 10 nm and the channel layer 8 In _x Ga _{1 -x} As layer (x = 0.18) is 15 nm thick, un-Al _x Ga _1-x As layer (x = 0.3) to be the spacer layer 9 is 10 nm thick, and the second electron supply layer 10 The n-In _x Ga _1-x P layer (x = 0.48) to be formed is formed by sequentially stacking a thickness of 15 nm and the un-GaAs layer to be the Schottky layer 11 is formed by stacking a thickness of 30 nm.

The HBT epitaxial layer 4 has an n-GaAs layer serving as the subcollector layer 13 having a thickness of 500 nm, an n-GaAs layer serving as the collector layer 14 having a thickness of 700 nm, a p-GaAs layer serving as the base layer 15 having a thickness of 120 nm, and an emitter layer. The n-In _x Ga _1-x P layer (x = 0.48) that becomes 16 has a thickness of 40 nm, the n-GaAs layer that becomes the ballast layer 17 has a thickness of 100 nm, and the n-In _x Ga that becomes the graded non-alloy layer 18. _{The 1-x} As layer (x = 0 to 0.5) has a thickness of 50 nm, and the n-In _x Ga _1-x As layer (x = 0.5) to be the uniform composition non-alloy layer 19 has a thickness of 50 nm. It is formed by stacking.

  As described above, the transistor element epitaxial wafer 1 has a structure in which the first electron supply layer 6 is provided below the channel layer 8 and the second electron supply layer 10 is provided above the channel layer 8.

  Next, the manufacturing method of the epitaxial wafer 1 for transistor elements of this invention is demonstrated.

  When the epitaxial wafer 1 for transistor elements is manufactured, the epitaxial layer 4 for HBT is grown after the epitaxial layer 3 for HEMT is grown, but the epitaxial layer 4 for HBT formed after the epitaxial layer 3 for HEMT is formed. Depending on the growth temperature, the heat diffuses from the electron supply layers 6 and 10 of the lower HEMT epitaxial layer 3 to reduce mobility.

  Therefore, the inventor has studied a method for manufacturing the epitaxial wafer 1 for transistor elements in which the epitaxial layer 4 for HBT is grown without reducing the mobility of the epitaxial layer 3 for HEMT, and as a result, the present invention has been achieved.

  In the method for manufacturing the epitaxial wafer 1 for transistor elements of the present invention, first, a group III source gas, a group V source gas, a dopant source gas, etc. are supplied onto the substrate 2 and the buffer layer 5, The electron supply layer 6, the spacer layer 7, the channel layer 8, the spacer layer 9, the second electron supply layer 10, and the Schottky layer 11 are sequentially grown to form the HEMT epitaxial layer 3, and a stopper is formed on the HEMT epitaxial layer 3. Layer 12 is grown. When growing each layer of the HEMT epitaxial layer 3 and the stopper layer 12, the growth temperature is 600 ° C. or higher and 750 ° C. or lower, the growth pressure is 6666 Pa (50 torr), and the growth rate of each layer is 0.1 nm / sec or higher and 2.0 nm / second. sec or less, and the V / III ratio is 10 or more and 150 or less.

Si may be used as a doping agent for doping the electron supply layers 6 and 10. The carrier concentration of the first electron supply layer 6 and the second electron supply layer 10 is preferably 5.0 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. Thereby, the fall of the mobility of the epitaxial layer 3 for HEMT can be prevented.

  The thickness of the stopper layer 12 formed on the HEMT epitaxial layer 3 is 6 nm or more and 12 nm or less, more preferably 9.5 nm or less. As a result, it can sufficiently serve as a stopper during etching. The reason why the thickness is preferably 9.5 nm or less is to suppress the resistance in the vertical direction (on-resistance) (when the thickness of the stopper layer 12 is increased, the on-resistance increases).

  Thereafter, the subcollector layer 13, collector layer 14, base layer 15, emitter layer 16, ballast layer 17, graded non-alloy layer 18, and uniform composition non-alloy layer 19 are sequentially grown on the stopper layer 12 to form the HBT epitaxial layer 4. Form. When each layer of the HBT epitaxial layer 4 is grown, the growth temperature is lower than the growth temperature of the HEMT epitaxial layer 3, specifically, 400 ° C. or more and 600 ° C. or less. The growth pressure is set to 6666 Pa (50 torr), the growth rate of each layer is set to 0.1 nm / sec to 3.0 nm / sec, and the V / III ratio is set to 0.5 to 300. Among these, the V / III ratio during the growth of the subcollector layer 13 and the collector layer 14 is 1 or more and 75 or less.

Since the subcollector layer 13 is a layer for forming an ohmic contact with the metal electrode, the carrier concentration is high. Specifically, the carrier concentration is 1 × 10 ¹⁸ cm ⁻³ or more and 7 × 10 ¹⁸ cm ⁻³ or less. In order to reduce the series resistance value, the film thickness is increased to 200 nm to 800 nm.

Further, since the collector layer 14 is a layer for extracting electrons from the base layer 15, the carrier concentration is small, specifically, the carrier concentration is set to 5 × 10 ¹⁵ cm ⁻³ or more and 3 × 10 ¹⁶ cm ⁻³ or less. In order to reduce the series resistance value, the film thickness is increased to 400 nm to 800 nm.

  From the above, the epitaxial wafer 1 for transistor elements is obtained. By processing the obtained epitaxial wafer 1 for transistor elements into a desired element shape by etching, when used in a power amplifier for transmission, it can operate at a low voltage, suppress distortion of output signals, and reduce power consumption. In addition, a high mobility transistor element can be manufactured.

  Next, the reason for limiting the numerical values of the present invention will be described.

  First, the reason why the epitaxial layer 4 for HBT is grown at a temperature of 400 ° C. or higher and 600 ° C. or lower will be described.

The inventor makes the growth temperature of the HEMT epitaxial layer 3 (600 ° C. or higher and 750 ° C. or lower) constant, and increases the growth temperature (substrate maximum temperature) of each layer constituting the HBT epitaxial layer 4 from 350 ° C. to 650 ° C. The epitaxial wafers for transistor elements of Examples and Comparative Examples were manufactured by changing the temperature to 0 ° C., transistor elements were manufactured from the respective epitaxial wafers for transistor elements, and the mobility was confirmed. The carrier concentration of the first electron supply layer 6 and the second electron supply layer 10 was 5 × 10 ¹⁸ cm ⁻³ .

  Table 1 and FIG. 2 show the operation results (difference in mobility) of each manufactured transistor element.

  In Table 1, the mobility is the mobility of the HEMT epitaxial layer 3.

As shown in Table 1 and FIG. 2, when the substrate maximum temperature is 400 ° C. or more and 600 ° C. or less, the mobility of the HEMT epitaxial layer 3 is stabilized at a high position of about 5500 cm ² / V · s. When the growth temperature exceeds 600 ° C., it is considered that the heat applied to each layer constituting the HEMT epitaxial layer 3 is large, and the mobility is lowered due to diffusion of electrons from the electron supply layers 6 and 10. Note that at a temperature lower than 400 ° C., gas decomposition hardly occurs or hardly occurs, and growth of the HBT epitaxial layer 4 is difficult, so the lower limit was set to 400 ° C.

Regarding the epitaxial wafer for transistor elements in which the carrier concentration of each of the electron supply layers 6 and 10 is 1 × 10 ¹⁸ cm ⁻³ , the mobility was confirmed by changing the substrate maximum temperature in the same manner. Below 600 ° C., the mobility was stable at a high position of about 5300 cm ² / V · s. However, when the temperature was lower than 400 ° C. or exceeded 600 ° C., it was confirmed that the mobility dropped rapidly. . Further, it has been found that good results can be obtained if the thickness of each of the electron supply layers 6 and 10 is 1 nm to 20 nm, more preferably 8 nm to 15 nm.

  Therefore, in the present invention, the growth temperature of the epitaxial layer 4 for HBT is set to 400 ° C. or more and 600 ° C. or less.

Next, the reason why the carrier concentration of the first electron supply layer 6 and the second electron supply layer 10 is 5.0 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less will be described.

The inventor changed the carrier concentration of the first electron supply layer 6 from 1.5 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ¹⁷ cm ^−3, and the transistors of the examples and comparative examples were changed as shown in Table 2. Element epitaxial wafers were manufactured, transistor elements were manufactured from the respective transistor element epitaxial wafers, and the mobility was confirmed. At this time, the carrier concentration of the second electron supply layer 10 was made equal to the carrier concentration of the first electron supply layer 6, and the manufacturing conditions other than the carrier concentration were the same. The growth temperature of the HBT epitaxial layer 4 was 570 ° C.

Table 2 and FIG. 3 show the operation results (difference in mobility) of each manufactured transistor element. Further, in each manufactured transistor element, the base resistance of the HBT epitaxial layer 4 was 220 Ω / sq, and the current gain was 120 (current density 1 kA / cm ² ).

  In Table 2, the mobility is the mobility of the HEMT epitaxial layer 3, the sheet carrier concentration is the sheet carrier concentration of the HEMT epitaxial layer 3, and the pinch-off voltage is the pinch-off voltage of the HBT epitaxial layer 4. .

  As shown in Table 2 and FIG. 3, when the carrier concentration of the first electron supply layer 6 is increased, the mobility of the HEMT epitaxial layer 3 can be suppressed low, whereas the carrier concentration of the first electron supply layer 6 is decreased. Then, the mobility of the HEMT epitaxial layer 3 can be increased.

In particular, by setting the carrier concentration of the first electron supply layer 6 to 1 × 10 ¹⁹ cm ⁻³ or less, it can be kept substantially constant with a high mobility of 5000 cm ² / V · s or more. In other words, when the carrier concentration exceeds a certain threshold value, the mobility rapidly decreases.

  This is because when the HBT epitaxial layer 4 is grown on the HEMT epitaxial layer 3, heat during the growth of the epitaxial layer constituting the HBT epitaxial layer 4 is applied to the HEMT epitaxial layer 3. This is probably because electrons diffuse from the first electron supply layer 6 to the spacer layer 7.

That is, by setting the carrier concentration of the first electron supply layer 6 to 1 × 10 ¹⁹ cm ⁻³ or less, the diffusion of electrons from the first electron supply layer 6 is suppressed, and as a result, the movement of the HEMT epitaxial layer 3 The degree is considered to be maintained sufficiently high. Similarly, if the carrier concentration of the second electron supply layer 10 is 1 × 10 ¹⁹ cm ⁻³ or less, it is considered that the mobility of the HEMT epitaxial layer 3 is maintained sufficiently high.

In addition, when the carrier concentration of the first electron supply layer 6 was less than 5.0 × 10 ¹⁷ cm ⁻³ , good operation as a HEMT could not be obtained.

Therefore, in the present invention, the carrier concentration of the first electron supply layer 6 and the second electron supply layer 10 is set to 5.0 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. From the viewpoint of electrical characteristics as a transistor element, the upper limit of the carrier concentration of the first electron supply layer 6 and the second electron supply layer 10 is more preferably 2.5 × 10 ¹⁸ cm ⁻³ or less. Thereby, it is possible to maintain good electrical characteristics as a transistor element by suppressing the diffusion of Si.

  Next, the reason why the thickness of the stopper layer 12 provided between the HEMT epitaxial layer 3 and the HBT epitaxial layer 4 is 6 nm or more and 12 nm or less will be described.

  The transistor element is formed by processing the epitaxial wafer 1 for transistor elements into a desired element shape by appropriate etching in order to obtain a transistor element structure.

  At this time, the progress of the etching is stopped by the stopper layer 12 formed on the Schottky layer 11, but the stopper layer 12 has a problem of degrading the characteristics of the HEMT epitaxial layer 3, so that it is as thin as possible. It is desirable to form.

The inventor manufactured the epitaxial wafers for the transistor elements of Examples and Comparative Examples by changing the thickness of the stopper layer 12, manufactured the transistor elements from the epitaxial wafers for the transistor elements, and confirmed the sheet carrier concentration. did. The carrier concentration of the first electron supply layer 6 and the second electron supply layer 10 was 5 × 10 ¹⁸ cm ⁻³ .

  FIG. 4 shows an operation result (difference in sheet carrier concentration) of each manufactured transistor element. As shown in FIG. 4, when the thickness of the stopper layer 12 is less than 6 nm, the sheet carrier concentration rapidly decreases.

  In an epitaxial wafer for a transistor element having a conventional structure (a structure in which an HEMT epitaxial layer is formed on an HTB epitaxial layer) as in Patent Document 1, excellent electrical characteristics can be obtained by setting the thickness of the stopper layer to about 4 nm. In the epitaxial wafer 1 for a transistor element having a structure in which the HBT epitaxial layer 4 is formed on the HEMT epitaxial layer 3, the stopper layer 12 has a thickness of less than 6 nm. 12, it was found that the etching could not be completely stopped. In the present invention, the epitaxial layer 4 for HBT is grown after the stopper layer 12 is formed, so that heat is applied to the stopper layer 12 to deteriorate the performance as a stopper.

  Therefore, in the present invention, the thickness of the stopper layer 12 is set to 6 nm or more. Further, considering that increasing the thickness of the stopper layer 12 causes a decrease in mobility of the HEMT epitaxial layer 3, the upper limit of the thickness of the stopper layer 12 is set to 12 nm.

  As described above, according to the present invention, the HEMT epitaxial layer 3 is grown at a growth temperature of 600 ° C. or more and 750 ° C. or less and the V / III ratio is 10 or more and 150 or less, and the HBT epitaxial layer 4 is grown. Since the growth is performed at a temperature lower than the growth temperature of the layer 3, specifically, 400 ° C. or more and 600 ° C. or less, each electron supply layer 6, 10 is caused by heat generated when the HBT epitaxial layer 4 is grown on the HEMT epitaxial layer 3. Therefore, it is possible to prevent the electrons from diffusing from each other, to prevent the mobility of the HEMT epitaxial layer 3 from being lowered, and it is possible to manufacture the epitaxial wafer 1 for transistor elements having good electrical characteristics.

In the present invention, the subcollector layer 13 is formed so that the carrier concentration is 1 × 10 ¹⁸ cm ⁻³ or more and 7 × 10 ¹⁸ cm ⁻³ or less, and the film thickness is 200 nm or more and 800 nm or less. Since the carrier concentration is 5 × 10 ¹⁵ cm ⁻³ or more and 3 × 10 ¹⁶ cm ⁻³ or less and the film thickness is 400 nm or more and 800 nm or less, ohmic contact with the metal electrode can be formed, and the series resistance value Can be reduced, and good electrical characteristics can be realized.

  Further, in the present invention, the epitaxial layer constituting the HEMT epitaxial layer 3 is grown on the substrate 2 and the epitaxial layer constituting the HBT epitaxial layer 4 is grown thereon, as in the structure of Patent Document 1. The crystallinity of the channel layer 8 and the like is not deteriorated by the growth temperature when the HEMT epitaxial layer is grown, and the current gain does not decrease in the HBT epitaxial layer 4.

Further, in the present invention, the carrier concentration of the first electron supply layer 6 and the second electron supply layer 10 is 5.0 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, and the film thickness thereof is 1 nm or more and 20 nm or less. Therefore, when the HBT epitaxial layer 4 is grown, the diffusion of electrons from the first electron supply layer 6 and the second electron supply layer 10 is suppressed, and as a result, the mobility of the HEMT epitaxial layer 3 is increased. Can be kept high enough.

  In the present invention, since the stopper layer 12 having a film thickness of 6 nm to 12 nm is formed between the HEMT epitaxial layer 3 and the HBT epitaxial layer 4, the mobility of the HEMT epitaxial layer 3 is reduced. In addition, it can sufficiently serve as a stopper during etching, and as a result, the sheet carrier concentration can be prevented from decreasing.

  In this embodiment, Si is used as a doping agent for each of the electron supply layers 6 and 10, but Se or Te may also be used. Further, although a semi-insulating GaAs substrate is used as the substrate 2, the present invention can also be applied to Si substrates and InP substrates.

In the present embodiment, the carrier concentrations of the first electron supply layer 6 and the second electron supply layer 10 are the same, but the carrier concentrations of the first electron supply layer 6 and the second electron supply layer 10 are 5. As long as they are 0 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, they may be different from each other. The second electron supply layer 10 is an n-InGaP layer, but may be an n-AlGaAs layer.

  Further, in the present embodiment, the first electron supply layer 6 is provided below the channel layer 8 and the second electron supply layer 10 is provided above the channel layer 8. An electron supply layer (corresponding to the second electron supply layer 10 in FIG. 1) may be provided only above the channel layer 8 without providing an electron supply layer in the lower part. This electron supply layer may be composed of either an n-InGaP layer or an n-AlGaAs layer.

When the mobility was confirmed even in the epitaxial wafer for transistor elements having a structure in which the electron supply layer is provided only above the channel layer 8, the carrier concentration of the electron supply layer is 5.0 × 10 ¹⁷ cm ⁻³ or more and 1 By reducing the growth temperature of the epitaxial layer 4 for HBT within the range of the above conditions by × 10 ¹⁹ cm ⁻³ or less, a decrease in mobility of the epitaxial layer 3 for HEMT could be suppressed. Further, the same result can be obtained even when the electron supply layer is not provided above the channel layer 8 and the electron supply layer (corresponding to the first electron supply layer 6 in FIG. 1) is provided only below the channel layer 8. can get.

  In the present embodiment, the growth temperature of the epitaxial layer 4 for HBT is 400 ° C. or more and 600 ° C. or less, but the collector layer 14 is grown at 400 ° C. or more and 600 ° C. or less, and the upper layer (base layer 15 To uniform composition non-alloy layer 19) may be grown at a temperature higher than 600 ° C., for example, 650 ° C.

When the mobility of the epitaxial wafer for transistor elements grown on this upper layer at 650 ° C. was confirmed, a slight decrease in mobility was confirmed, but the carrier concentration of each electron supply layer 6, 10 was 5 × 10 ¹⁸ cm. ^In the case of ⁻³ , it was confirmed that the mobility was stable at a high position of about 5400 cm ² / V · s.

  According to this result, even if an annealing process is required after the base layer 15 and the emitter layer 16 are formed, if the subcollector layer 13 and the collector layer 14 are grown at 400 ° C. or more and 600 ° C. or less, the mobility is increased. It is thought that the decrease in the temperature can be prevented. This is because a relatively thick layer such as the sub-collector layer 13 and the collector layer 14 is laminated, so that the distance from the layer to be annealed to the HEMT epitaxial layer 3 is increased, and the uniform composition non-alloy is separated from the base layer 15. This is probably because the layers up to the layer 19 have a short growth time and are not easily affected by the heat applied to the HEMT epitaxial layer 3 by the annealing treatment.

DESCRIPTION OF SYMBOLS 1 Epitaxial wafer for transistor elements 2 Substrate 3 Epitaxial layer for high electron mobility transistor (epitaxial layer for HEMT)
4 Hetero bipolar transistor epitaxial layer (HBT epitaxial layer)

Claims (6)

In a method for manufacturing an epitaxial wafer for a transistor element, an epitaxial layer for a high electron mobility transistor is formed on a substrate, and an epitaxial layer for a heterobipolar transistor is formed on the epitaxial layer for a high electron mobility transistor.
The epitaxial layer for a high electron mobility transistor is grown at a growth temperature of 600 ° C. to 750 ° C. and a V / III ratio of 10 to 150, and the epitaxial layer for a heterobipolar transistor is grown at a temperature lower than the growth temperature. A method for producing an epitaxial wafer for a transistor element, comprising: An epitaxial wafer for a transistor element, wherein an epitaxial layer for a high electron mobility transistor is formed on a substrate, and an epitaxial layer for a heterobipolar transistor having a subcollector layer and a collector layer is formed on the epitaxial layer for a high electron mobility transistor. In the manufacturing method,
The epitaxial layer for the high electron mobility transistor is grown at a growth temperature of 600 ° C. to 750 ° C., a V / III ratio of 10 to 150, and a growth rate of 0.1 nm / sec to 2.0 nm / sec by metal organic vapor phase epitaxy. And at least the subcollector layer and the collector layer of the heterobipolar transistor epitaxial layer are grown at a growth temperature of 400 ° C. or more and 600 ° C. or less and a V / III ratio of 1 or more and 75 or less by metal organic vapor phase epitaxy. The subcollector layer is formed so that the carrier concentration is 1 × 10 ¹⁸ cm ⁻³ or more and 7 × 10 ¹⁸ cm ⁻³ or less and the film thickness is 200 nm or more and 800 nm or less. concentration of 5 × 10 ¹⁵ cm ^-3 or more 3 × 10 ¹⁶ cm ^-3 or less, and the thickness is formed so as to 400nm or 800nm or less Method for producing a transistor element epitaxial wafer characterized and. 3. The transistor element according to claim 1, wherein the epitaxial layer for a high electron mobility transistor has an electron supply layer having a carrier concentration of 5.0 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. Epitaxial wafer manufacturing method.   The method for producing an epitaxial wafer for a transistor element according to claim 3, wherein the electron supply layer has a thickness of 1 nm to 20 nm.   5. The method for producing an epitaxial wafer for a transistor element according to claim 3, wherein the electron supply layer is an n-AlGaAs layer doped with any of Si, Se, or Te, or an n-InGaP layer doped with Si. 6. .   The transistor element epitaxial according to any one of claims 1 to 5, wherein a stopper layer having a film thickness of 6 nm or more and 12 nm or less is formed between the epitaxial layer for high electron mobility transistor and the epitaxial layer for hetero bipolar transistor. Wafer manufacturing method.

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