JP2012160662A - Method of manufacturing epitaxial wafer for transistors - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing an epitaxial wafer for transistors capable of suppressing reduction in HEMT mobility.SOLUTION: A high electron mobility transistor structure layer 3 is grown by the vapor growth method on a condition that a growth temperature is 600°C or more and 750°C or less and that a V/III ratio is 150 or less. A bipolar transistor structure layer 4 is grown by the vapor growth method on a condition that a growth temperature is 400°C or more and 600°C or less and that a V/III ratio is 75 or less. Further, a non-alloy layer 18 is grown at a growth temperature of 380°C or more and 450°C or less.

Description

  The present invention relates to a method for producing an epitaxial wafer for a transistor, comprising: a step of forming a high electron mobility transistor structure layer on a substrate; and a step of forming a bipolar transistor structure layer on the high electron mobility transistor structure layer. It is.

  In power amplifiers for communication terminal equipment, hetero bipolar transistors (hereinafter referred to as HBT) and high electron mobility transistors (hereinafter referred to as HEMT) formed using compound semiconductors are used. It has been.

  First, a hetero bipolar transistor (HBT) will be described.

  The operation of the HBT is basically the same as that of a normal bipolar transistor (hereinafter referred to as BJT). In the npn-type BJT, the amount of electrons flowing from the emitter to the collector is controlled by the base current (hole current), thereby operating as a transistor. That is, the collector current increases by increasing the Hall current. However, if the hole current is further increased, holes leak from the base toward the emitter, and the current amplification factor of the transistor decreases.

  On the other hand, in an npn-type HBT configured using a semiconductor material having a large band gap for the emitter, a barrier is formed at the base-emitter interface, and holes can be prevented from leaking to the emitter. As a result, the HBT has an advantage that the collector current can be increased without reducing the current amplification factor.

A typical structure of HBT is shown in FIG. As shown in FIG. 3, the HBT 31 has a semi-insulating GaAs substrate 32 on which an n-type GaAs layer serving as a subcollector layer 33 is 500 nm, an n-type GaAs layer serving as a collector layer 34 is 700 nm, and a p-layer serving as a base layer 35. 80 nm for the n-type GaAs layer, 40 nm for the n-type In _x Ga _1-x P layer (x = 0.48) serving as the emitter layer 36, 100 nm for the n-type GaAs layer serving as the emitter contact layer 37, and the graded non-alloy layer 38 The n-type In _x Ga _1-x As layer (x = 0 → 0.5) to be 50 nm and the n-type In _x Ga _1-x As layer (x = 0.5) to be the uniform composition non-alloy layer 39 are 50 nm. They are laminated in order.

  Next, a high electron mobility transistor (HEMT) will be described.

  The HEMT has an InGaAs layer as a channel layer and has an electron supply layer on both sides or one side of the channel layer. Heterojunction HEMTs can not only operate at high speed by taking advantage of the high-speed movement of electrons, but also can operate at high power and high efficiency in an ultrahigh frequency band such as a microwave band.

A typical structure of the HEMT is shown in FIG. As shown in FIG. 4, the HEMT 41 becomes an undoped GaAs layer serving as a buffer layer 43, an n-type Al _x Ga _1-x As layer serving as an electron supply layer 44, and a spacer layer 45 on a semi-insulating GaAs substrate 42. undoped Al _x Ga _1-x as layer, an undoped a channel layer 46 In _x Ga _1-x as layer, an undoped Al _x Ga _1-x as layer as the spacer layer 47, the electron supply layer 48 n-type Al _x A Ga _1-x As layer and an n-type GaAs layer serving as a cap layer 49 are sequentially stacked.

In FIG. 3, n ⁺ , n, and n ⁻ are used as the notation indicating the carrier concentration. These are examples of the carrier concentration, and those with + are 10 at a high carrier concentration. ¹⁸ or more, no mark 10 ¹⁷ units, - which is attached represents a 10 ¹⁴ or more 10 than ¹⁷ at a low carrier concentration. 3 and 4, n- means n-type, p- means p-type, and un- means undoped.

  These transistors have been mainly used for power amplifiers for transmitting and receiving mobile terminals, but in recent years, not only voice and text data but also large-capacity and diverse information such as moving images have been required to be transmitted and received at high speed. . For this reason, the power amplifier for transmission / reception, which is the component that consumes the largest amount of power in the portable terminal, is also required to have high performance, and it is required to operate at a low voltage and to reduce power consumption. These requirements can be met by increasing the efficiency of the power amplifier, but generally, when the amplifier is operated with high efficiency, there is a problem that distortion of the output signal becomes large. When the distortion of the output signal increases, there is a problem that radio waves leak to adjacent communication channels due to the distortion, the signals interfere with each other, and the transmission data has different values.

  Therefore, by using multiple HMTs with high current drive capability and HEMTs with low power consumption and good high frequency noise characteristics in one power amplifier module, distortion of the output signal can be suppressed and power consumption can be reduced, resulting in high amplitude. A power amplifier module that can obtain an output signal is used. For example, the power amplifier module 51 shown in FIG. 5 is configured to amplify the input signal by the driving HBT 52 and further amplify the amplified signal by the output HEMT 53 at the subsequent stage to obtain an output signal.

  However, when the HBT 52 and the HEMT 53 are connected by wiring as in the power amplifier module 51 of FIG. 5, RC delay due to the wiring and heat generation of the element become problems.

  Therefore, a transistor having a two-stage transistor structure (BI-FET structure) in which this wiring is eliminated, a HEMT is provided by epitaxial growth on a substrate, and an HBT is further provided on the HEMT is used (for example, Patent Document 1). reference).

JP 2006-228784 A

  However, when manufacturing an epitaxial wafer for a transistor having a BI-FET structure as described above, a plurality of epitaxial layers constituting the HBT are grown on the plurality of epitaxial layers constituting the HEMT. When growing a plurality of epitaxial layers, an annealing effect is added to the plurality of epitaxial layers constituting the HEMT, which causes a problem that the mobility of the HEMT is lowered.

  Therefore, an object of the present invention is to provide a method for manufacturing an epitaxial wafer for a transistor that can solve the above-described problems and can suppress a decrease in mobility of the HEMT.

  The present invention was devised to achieve the above object, and includes a step of forming a high electron mobility transistor structure layer having an electron supply layer and a channel layer on a substrate, and the high electron mobility transistor structure layer. Forming a bipolar transistor structure layer having a collector layer, a base layer, an emitter layer, and a non-alloy layer thereon, wherein the high electron mobility transistor structure layer is vapor-phase grown. The bipolar transistor structure layer is grown at a growth temperature of 400 ° C. to 600 ° C. and a V / III ratio of 75 or less by vapor phase growth. In which the non-alloy layer is further grown at a growth temperature of 380 ° C. or higher and 450 ° C. or lower. It is a manufacturing method of data for epitaxial wafer.

The non-alloy layer has a graded non-alloy layer made of n-type InGaAs doped with Se or Te as an n-type impurity and the In composition is changed in the growth direction, and the graded non-alloy layer is an n-type impurity. It is preferable to grow so that the concentration is in a range of 3.0 × 10 ¹⁸ cm ⁻³ or more and 1.0 × 10 ¹⁹ cm ⁻³ or less.

The non-alloy layer further has a uniform composition non-alloy layer made of n-type InGaAs having a constant In composition ratio of 0.3 to 0.6 on the graded non-alloy layer, and the uniform composition non-alloy layer, n-type impurity concentration becomes 1.0 × 10 ¹⁹ cm ^-3 or more 5.0 × 10 ¹⁹ cm ^-3 or less in the range, as the mobility is equal to or smaller than 500cm ² / V · s or more 1500cm ² / V · s It is good to grow up.

  As mixed concentration between the high electron mobility transistor structure layer and the bipolar transistor structure layer at a growth temperature lower than the growth temperature of the high electron mobility transistor structure layer and at a growth rate of 1.5 nm / sec or less. An etching stopper layer made of InGaP in which the above is controlled may be formed.

  The electron supply layer of the high electron mobility transistor structure layer may be a Siδ doped layer.

The mobility of the channel layer of the high electron mobility transistor structure layer may be 5500 cm ² / V · s or more.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the epitaxial wafer for transistors which can suppress the fall of the mobility of HEMT can be provided.

It is a laminated structure figure of the epitaxial wafer for transistors manufactured with the manufacturing method of the epitaxial wafer for transistors concerning one embodiment of the present invention. In this invention, it is a graph which shows the relationship between the growth temperature of a non-alloy layer, and the mobility of HEMT. It is a laminated structure figure of HBT. It is a laminated structure figure of HEMT. It is a circuit diagram of the conventional power amplifier module.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a stacked structure diagram of a transistor epitaxial wafer manufactured by the method for manufacturing a transistor epitaxial wafer according to the present embodiment.

  As shown in FIG. 1, a transistor epitaxial wafer 1 has a high electron mobility transistor structure layer (hereinafter referred to as HEMT structure layer) 3 formed on a GaAs substrate 2 and a bipolar transistor structure layer (hereinafter referred to as HEMT structure layer 3). (Hereinafter referred to as an HBT structure layer) 4 is formed (BI-FET structure). In addition, the notation of i- in FIG. 1 means that it is undoped.

When manufacturing the epitaxial wafer 1 for transistors, first, an undoped Al _x Ga _1-x As layer (x = 0.28) to be the buffer layer 5 is epitaxially grown on the semi-insulating GaAs substrate 2 by 500 nm. The n-type Al _x Ga _1-x As layer (x = 0.3) serving as the electron supply layer 6 is 30 nm, and the undoped Al _x Ga _1-x As layer (x = 0.3) serving as the spacer layer 7 is 10 nm. The In _x Ga _1-x As layer (x = 0.18) serving as the channel layer 8 is 15 nm, the undoped Al _x Ga _1-x As layer (x = 0.3) serving as the spacer layer 9 is 10 nm, and the electron supply The HEMT structure layer 3 is formed by sequentially stacking an n-type In _x Ga _1-x P layer (x = 0.48) to be the layer 10 and 30 nm and an undoped GaAs layer to be the Schottky layer 11 in this order. . In the present embodiment, the HEMT structure layer 3 is grown by vapor phase epitaxy (MOVPE (Metal Organic Vapor Phase Epitaxy) method) under conditions of a growth temperature of 600 ° C. or more and 750 ° C. or less and a V / III ratio of 150 or less. In the present specification, the growth temperature means the substrate temperature of the GaAs substrate 2 during growth.

  The electron supply layers 6 and 10 of the HEMT structure layer 3 are made of Si δ-doped layers. Note that the δ-doped layer is a region where a dopant (Si in this case) is locally contained at a high concentration, and does not exist as a layer having a reduced scale as shown in FIG. That is, in FIG. 1, the scale of each layer is changed for convenience, and the structure of the transistor epitaxial wafer 1 is schematically shown.

On the HEMT structure layer 3 (between the HEMT structure layer 3 and the HBT structure layer 4), an n-type In _x Ga _1-x P layer (x = 0.48) is laminated to 10 nm by epitaxial growth to form an etching stopper layer. 12 is formed. In the present embodiment, the etching stopper layer 12 made of InGaP in which the As mixing concentration is controlled at a growth temperature lower than the growth temperature of the HEMT structure layer 3 and at a growth rate of 1.5 nm / sec or less is formed.

After that, on the etching stopper layer 12, by epitaxial growth, the n-type GaAs layer to be the subcollector layer 13 is 500 nm, the n-type GaAs layer to be the collector layer 14 is 700 nm, the p-type GaAs layer to be the base layer 15 is 120 nm, the emitter An n-type In _x Ga _1-x P layer (x = 0.48) to be the layer 16 is sequentially stacked to 40 nm, an n-type GaAs layer to be the ballast layer 17 is sequentially stacked to 100 nm, and a non-alloy layer 18 is stacked on the ballast layer 17. Thus, the HBT structure layer 4 is formed. In the present embodiment, the HBT structure layer 4 is grown by a vapor phase growth method (MOVPE method) under conditions of a growth temperature of 400 ° C. or more and 600 ° C. or less and a V / III ratio of 75 or less.

The non-alloy layer 18 includes a graded non-alloy layer 19 made of n-type In _x Ga _1-x As, doped with Se or Te as an n-type impurity, and changed in composition in the growth direction, and a graded non-alloy layer 19. And a uniform composition non-alloy layer 20 made of n-type In _x Ga _1-x As and having a constant In composition ratio of 0.3 to 0.6.

In the present embodiment, the graded non-alloy layer 19 is configured such that the In composition gradually changes from 0 to 0.5 as the distance from the ballast layer 17 increases, and the substrate temperature (growth temperature) of the GaAs substrate 2 is increased. The carbon concentration in the graded non-alloy layer 19 is 3.0 × 10 ¹⁸ by adjusting the temperature of the heater for heating the GaAs substrate 2 as appropriate to adjust the gradient of the In composition ratio and the amount of auto-doped carbon. cm ^-3 to become less, so that n-type impurity concentration of 3.0 × 10 ¹⁸ cm ^-3 or more 1.0 × 10 ¹⁹ cm ^-3 or less in the range, 50 nm n-type an in _x Ga _{1- An x} As layer (x = 0 → 0.5) was grown.

In the present embodiment, the uniform composition non-alloy layer 20 is made constant at an In composition ratio of 0.5, and the amount of auto-doped carbon is adjusted similarly to the graded non-alloy layer 19. The n-type impurity concentration is 1.0 × 10 ¹⁹ cm ⁻³ or more and 5.0 × 10 ¹⁹ cm ⁻³ or less so that the carbon concentration is lower than the SIMS analysis lower limit (1.0 × 10 ¹⁶ cm ⁻³ ). as a range, and as mobility was Hall measurement by Van der Pauw method becomes less 500cm ² / V · s or more 1500cm ² / V · s, 50nm of n-type in _x Ga _1-x An As layer (x = 0.5) was grown.

  In the method for manufacturing an epitaxial wafer for a transistor according to the present embodiment, the non-alloy layer 18 is grown at a growth temperature of 380 ° C. or higher and 450 ° C. or lower. The reason for this will be described.

  FIG. 2 is a graph showing the relationship between the substrate temperature during growth of the non-alloy layer 18 (growth temperature of the non-alloy layer 18) and the mobility (μ) of the HEMT (HEMT structure layer 3).

As shown in FIG. 2, when the growth temperature of the non-alloy layer 18 is higher than 450 ° C., the mobility of the HEMT is drastically lowered. Therefore, it can be said that the growth temperature of the non-alloy layer 18 is desirably 450 ° C. or lower. Further, FIG. 2 shows that the mobility of the HEMT, that is, the mobility of the channel layer 8 of the HEMT structure layer 3 can be increased to 5500 cm ² / V · s or more by setting the growth temperature of the non-alloy layer 18 to 450 ° C. or less. .

On the other hand, TEI (triethylindium), TMI (trimethylindium), and TEG (triethylgallium) used as organometallic raw materials (group V raw materials) can be thermally decomposed even at a substrate temperature (growth temperature) of about 380 ° C. In the present embodiment, the growth temperature of the non-alloy layer 18 is set to 380 ° C. or higher. In order to increase the dopant efficiency of the n-type In _x Ga _1-x As layer doped with Te or Se as the non-alloy layer 18, it is 200 ° C. higher than the normal GaAs layer optimum growth substrate temperature (growth temperature) of 580 ° C. When the substrate temperature (growth temperature) is set to 350 ° C. or lower, the V group material does not undergo thermal decomposition or hardly undergoes thermal decomposition (growth time), so that application is difficult. is there.

  As described above, in the method for manufacturing an epitaxial wafer for a transistor according to the present embodiment, the HEMT structure layer 3 is grown by vapor phase growth under the conditions of a growth temperature of 600 ° C. or higher and 750 ° C. or lower and a V / III ratio of 150 or lower. The HBT structure layer 4 is grown by vapor phase growth at a growth temperature of 400 ° C. or higher and 600 ° C. or lower and a V / III ratio of 75 or lower, and the non-alloy layer 18 is grown at a growth temperature of 380 ° C. or higher and 450 ° C. or lower. Growing in.

The HBT structure layer 4 is grown at a growth temperature of 400 ° C. to 600 ° C. lower than the growth temperature of the HEMT structure layer 3, and the non-alloy layer 18 of the HBT structure layer 4 is grown at a growth temperature of 380 ° C. to 450 ° C. By doing so, it is possible to suppress the annealing effect from being applied to the HEMT structure layer 3, to minimize the influence on the HEMT characteristics, and to suppress the decrease in the mobility of the HEMT. As a result, the mobility of the channel layer 8 of the HEMT structure layer 3 can be set to 5500 cm ² / V · s or more.

According to the present invention, since the mobility in the HEMT structure layer 3 does not deteriorate when the HBT structure layer 4 is grown on the HEMT structure layer 3, a HEMT having a higher mobility than the conventional one can be manufactured. Therefore, according to the present invention, by using the obtained transistor epitaxial wafer 1 as an element, when used as a power amplifier for transmission and reception, it operates at a low voltage, suppresses distortion of an output signal, and reduces power consumption. And a high mobility transistor element can be realized. Specifically, in this embodiment, a base resistance of 220 Ω / sq is amplified to a current gain of 120 (1 kA / cm ² ), the mobility is 5600 cm ² / V · s, and the sheet carrier concentration is 2.1 × 10 ¹² cm ^{−. 2.} A transistor element operating with a pinch-off voltage of −0.5 V could be obtained.

  The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

  For example, in the above embodiment, Si is used as the dopant of the electron supply layers 6 and 10 of the HEMT structure layer 3, but Se and Te may be used as the dopant.

  Further, in the above embodiment, the semi-insulating GaAs substrate 2 is used as the substrate, but the present invention can also be applied to a Si substrate and an InP substrate.

1 Epitaxial wafer for transistor 2 GaAs substrate (substrate)
3 HEMT structure layer (high electron mobility transistor structure layer)
4 HBT structure layer (heterobipolar transistor structure layer)
5 Buffer layers 6, 10 Electron supply layers 7, 9 Spacer layer 8 Channel layer 11 Schottky layer 12 Etching stopper layer 13 Subcollector layer 14 Collector layer 15 Base layer 16 Emitter layer 17 Ballast layer 18 Non-alloy layer 19 Graded non-alloy layer 20 Uniform composition non-alloy layer

Claims (6)

Forming a high electron mobility transistor structure layer having an electron supply layer and a channel layer on a substrate;
Forming a bipolar transistor structure layer having a collector layer, a base layer, an emitter layer, and a non-alloy layer on the high electron mobility transistor structure layer;
In a method of manufacturing an epitaxial wafer for a transistor having
The high electron mobility transistor structure layer is grown by a vapor deposition method at a growth temperature of 600 ° C. to 750 ° C. and a V / III ratio of 150 or less.
The bipolar transistor structure layer is grown by vapor phase growth at a growth temperature of 400 ° C. or more and 600 ° C. or less and a V / III ratio of 75 or less, and the non-alloy layer is grown at a growth temperature of 380 ° C. or more and 450 ° C. or less. A method for producing an epitaxial wafer for a transistor. The non-alloy layer has a graded non-alloy layer made of n-type InGaAs doped with Se or Te as an n-type impurity and having an In composition changed in the growth direction,
The epitaxial wafer for a transistor according to claim 1, wherein the graded non-alloy layer is grown so that the n-type impurity concentration is in a range of 3.0 × 10 ¹⁸ cm ^{−3 to} 1.0 × 10 ¹⁹ cm ^−3. Manufacturing method. The non-alloy layer has a uniform composition non-alloy layer made of n-type InGaAs having a constant In composition ratio of 0.3 to 0.6 on the graded non-alloy layer,
The uniform composition non-alloy layer has an n-type impurity concentration in the range of 1.0 × 10 ¹⁹ cm ^{−3 to} 5.0 × 10 ¹⁹ cm ⁻³ and a mobility of 500 cm ² / V · s to 1500 cm ² / V. The method for producing an epitaxial wafer for a transistor according to claim 2, wherein the epitaxial wafer is grown so as to be s or less. As mixed concentration between the high electron mobility transistor structure layer and the bipolar transistor structure layer at a growth temperature lower than the growth temperature of the high electron mobility transistor structure layer and at a growth rate of 1.5 nm / sec or less. The manufacturing method of the epitaxial wafer for transistors in any one of Claims 1-3 which formed the etching stopper layer which consists of InGaP which controlled this.   5. The method for producing an epitaxial wafer for a transistor according to claim 1, wherein the electron supply layer of the high electron mobility transistor structure layer is a Siδ-doped layer. The method for producing an epitaxial wafer for a transistor according to claim 1, wherein mobility of the channel layer of the high electron mobility transistor structure layer is 5500 cm ² / V · s or more.

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