JP2007103925A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to: carry out doping at a high concentration; and make an excellent ohmic contact with an electrode. <P>SOLUTION: A semiconductor device using a group III-V compound semiconductor has an emitter electrode and a metal electrode contact layer in contact with the emitter electrode, and the metal electrode contact layer is constructed by a quantum structure. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a III-V compound semiconductor and a manufacturing method thereof, and particularly suitable for a heterojunction bipolar transistor (HBT), a field effect transistor (FET), or a high electron mobility transistor (HEMT). It is.

  A semiconductor device using a III-V group compound semiconductor typified by GaAs has a small distortion and can realize an efficient high-frequency characteristic of GHz or more. Therefore, it is widely used as an amplifier in many communication devices such as a mobile phone. in use. Among them, the HBT using a heterojunction for the emitter-base junction can increase the emitter injection efficiency due to the fact that the band gap of the emitter layer is wider than the band gap of the base layer. Widely used in high-power transistors for mobile phones.

  The structure of the conventional InGaP / GaAs HBT shown in FIG. 4 will be described as an example.

  The InGaP / GaAs HBT is formed on a semi-insulating GaAs substrate by vapor phase epitaxy such as MOVPE or MBE, and an n-type GaAs serving as an n-type GaAs subcollector layer 7, an n-type GaAs collector layer 6, and a collector depletion region. The epitaxial layer is formed by laminating the collector layer 5, the p-type GaAs base layer 4, the n-type InGaP emitter layer 3, the n-type GaAs emitter contact layer 2, and the n-type InGaAs non-alloy layer 1. The reason why the n-type InGaAs layer is a non-alloy layer is that the contact resistance is lower than that of the alloy layer.

  As the conductivity types of the collector layers 5 and 6, the base layer 4 and the emitter layer 3, there is also a pnp type, but in most cases, an npn type epitaxial layer is laminated as shown in the illustrated example. is there. Here, Si is generally used as the n-type dopant. Elements such as carbon, zinc and beryllium are used as p-type dopants.

  In the HBT, an emitter (metal) electrode 14 is formed on the n-type InGaAs non-alloy layer 1, a base electrode 13 is formed on the p-type GaAs base layer 4, and a collector electrode 12 is formed on the n-type GaAs subcollector layer 7. Is formed. In the case of grounded emitter, a positive voltage is applied from the power source 15 to the collector electrode 12 and a base current is supplied as a signal input from the base electrode 13 to control the collector current as an output.

Here, the operation principle of the HBT will be described with reference to FIG.
FIG. 6 shows the energy band structure of an npn type HBT. The HBT is a semiconductor element having three basic regions of an emitter, a base, and a collector. The non-alloy region 31, the emitter contact region 32, the emitter region 33, the base region 34, and the collector depletion region corresponding to each of the layers 1-7. 35, a collector region 36, and a sub-collector region 37. In the figure, 9 is the lower end of the conduction band, 10 is the upper end of the valence band, and 11 is the Fermi level.

  Electrons 8 injected from the emitter region 33 through the non-alloy region 31 and the emitter contact region 32 enter the base region 34 and pass through the base region 34 at high speed. In addition, holes injected from the base region 34 to the emitter region 33 are effectively suppressed by adopting a wide gap emitter by InGaP, so that current transmission is possible even when a forward bias is applied between the emitter and the base. The rate does not decrease. After the electrons reach the collector depletion region 35 between the base region 34 and the collector region 36, the electrons are accelerated by a large electric field between the base and collector and enter the collector region 36. The npn type HBT operates at a high speed because the time required for electrons to reach the collector electrode 12 from the emitter electrode 14 is short.

The most important in the HBT is the base region 34. In other words, it is ideal that electrons 8 are injected from the emitter region 33 into the base region 34 and transmitted to the collector regions 35 and 36 without being recombined with holes in the base region 34, thereby reducing current loss. There must be. Therefore, the base region 34 needs to be optimally designed.
Looking at the HBT element as a whole, there are several places where current loss occurs in addition to the base region 34. For example, the sub-collector region 37 and the collector electrode 12 in contact therewith, and the non-alloy region 31 of the metal electrode contact layer and the emitter electrode 14 in contact therewith.

Here, the base region 34 is a p-type GaAs layer of about 10 ¹⁹ to 10 ²⁰ [cm ⁻³ ], and the subcollector region 37 is also very high in concentration of 3.0 to 5.0 × 10 ¹⁸ [cm ⁻³ ]. The n-type GaAs layer is doped with the base electrode 13 and the collector electrode 12, which are metal electrodes, and can make good ohmic contact.
On the other hand, the non-alloy layer 1 corresponding to the non-alloy region 31 which is a metal electrode contact layer normally uses a GaAs layer, but as shown in FIG. 4, an n-type InGaAs layer is used instead of an n-type GaAs layer. Many. This is because InGaAs exhibits metal-like properties compared to GaAs, and a large amount of dopant can be doped, so that an n-type layer of 1 × 10 ¹⁹ [cm ⁻³ ] can be formed. Furthermore, these metal-like materials can be doped with a large amount of dopant because they have the advantage of being amplified by increasing the In composition. Therefore, in order for the non-alloy layer 1 to have good ohmic contact with the emitter electrode 14 which is a metal electrode, it is preferable to increase the In composition of InGaAs constituting the non-alloy layer 1.

However, when the In composition of InGaAs is increased, its lattice constant is further away from that of GaAs. Therefore, as shown in FIG. 5, when the In _x Ga _1-x As layer 17 corresponding to the non-alloy layer 1 is directly deposited on the GaAs layer 16 corresponding to the emitter contact layer 2 with a desired In composition ratio x. Dislocations 18 as shown in FIG. 5 are generated at the interface. Since the dislocation 18 is a kind of crystal defect, for example, when a semiconductor element is manufactured, an electrical defect occurs in the element including the dislocation.

In order to avoid this situation, it is necessary to grow the InGaAs non-alloy layer 17 by changing the In composition in order to match the lattice constant at the interface between the non-alloy layer 1 and the emitter contact layer 2. That is, when depositing In _x Ga _1-x As on a GaAs layer, first, the In composition is set to 0, and the In composition is gradually increased to change to a desired composition capable of achieving good ohmic contact. To do.

  For example, Patent Document 1 proposes that the InGaAs non-alloy layer is composed of a step graded layer in which the In composition is changed to a step shape, and a uniform composition layer having a uniform In composition formed thereon.

  In Patent Document 2, an inclined layer (linear graded layer) in which the In composition is changed from 0 to 60% is inserted between the non-alloy layer and the ohmic contact layer. The reason why the In composition is set to 60% is that an InGaAs layer that exhibits p-type carrier concentration when originally doped with C (carbon) exhibits an n-type carrier concentration by setting its In composition x to 0.5 or more. , And the In composition x of the InGaAs non-alloy layer is set to about 0.6 so that an n-type InGaAs non-alloy layer is obtained, thereby reducing the contact resistance.

On the other hand, when a GaAs layer is used as usual for the non-alloy layer 1 corresponding to the non-alloy region 31 which is a metal electrode contact layer, Si is exclusively used as n-type doping.
JP 2004-207546 A JP 2005-79268 A

(1) When InGaAs is used for the metal electrode contact layer The above-described conventional method for gradually increasing the In composition to a desired composition has the following problems. That is, when the thickness of the In _x Ga _1-x As layer having the desired In composition exceeds the critical thickness, it is difficult to suppress the occurrence of dislocations. Here, the critical film thickness means the maximum In _x Ga _1-x As film thickness at which dislocation does not occur for a certain In composition x. For example, when x = 0.5, it has only a critical film thickness of several nm. The critical film thickness decreases as the In composition x increases, and conversely increases as the In composition x decreases. Therefore, the film thickness of the InGaAs layer having the desired In composition may easily exceed the critical film thickness, resulting in the occurrence of dislocations.

(2) When using GaAs for the metal electrode contact layer As usual, when using GaAs with an In composition of zero for the non-alloy layer that is the metal electrode contact layer, the same material as the GaAs layer below the non-alloy layer is used. Therefore, no defect occurs at the epitaxial layer interface. However, if GaAs is not metal-like and Si is used as an n-type dopant, it is difficult to do n-type doping to 1 × 10 ¹⁹ [cm ⁻³ ] or more. Therefore, it is difficult to make good ohmic contact with the metal electrode.

  Accordingly, an object of the present invention is to solve the above-described problems, and to provide a semiconductor device having a metal electrode contact layer capable of performing high-concentration doping and taking good ohmic contact with the metal electrode, and a method for manufacturing the same. It is to provide.

In order to achieve the above object, the present invention is configured as follows.
A first invention is a semiconductor device using a group III-V compound semiconductor, having an emitter electrode and a metal electrode contact layer in contact with the emitter electrode, the metal electrode contact layer having a quantum structure. It is characterized by that.

According to a second invention, in the first invention, the quantum structure includes an In _x Ga _1-x As (x = 0.1-1) layer having a critical film thickness or less and a GaAs layer provided thereon. It is characterized by being configured by laminating a plurality of periods as a period.

  A third invention is characterized in that, in the first or second invention, the metal electrode contact layer composed of the quantum structure is a non-alloy layer.

  According to a fourth invention, in the first to fourth inventions, the quantum structure is any one of a quantum dot, a quantum wire, or a quantum well.

According to a fifth invention, in the first invention, the metal electrode contact layer is formed of an n-type GaAs layer doped with Se at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more, instead of the quantum structure. It is characterized by that.

  According to a sixth invention, in the first to fifth inventions, the semiconductor device is any one of a heterojunction bipolar transistor, a field effect transistor, and a high electron mobility transistor.

  According to a seventh invention, in the method of manufacturing a semiconductor device using a group III-V compound semiconductor having an emitter electrode and a metal electrode contact layer in contact with the emitter electrode, the metal electrode contact layer is formed with a quantum structure. It is characterized by.

According to an eighth invention, in the seventh invention, the quantum structure is composed of an In _x Ga _1-x As (x = 0.1-1) layer having a critical thickness or less and a GaAs layer provided thereon. It is characterized by being formed by laminating a plurality of periods as a period.

  A ninth invention is characterized in that, in the seventh or eighth invention, the metal electrode contact layer formed of the quantum structure is a non-alloy layer.

  A tenth invention is characterized in that, in the seventh to ninth inventions, the quantum structure is any one of a quantum dot, a quantum wire, or a quantum well.

In an eleventh aspect based on the seventh aspect, instead of forming the metal electrode contact layer with the quantum structure, the metal electrode contact layer is formed with an n-type GaAs layer doped with Se at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more. The GaAs layer is grown later than when the GaAs layer under the metal electrode contact layer is grown.

  According to a twelfth aspect, in the seventh to eleventh aspects, the semiconductor device is any one of a heterojunction bipolar transistor, a field effect transistor, and a high electron mobility transistor.

  According to the present invention, high concentration doping can be performed, and good ohmic contact with the metal electrode can be obtained.

  Hereinafter, the present invention will be described based on embodiments.

First Embodiment [Non-alloy layer using a quantum structure]
The critical film thickness of the In _x Ga _1-x As layer varies depending on the value of the In composition x. As described above, the In _x Ga _1-x As layer has a critical film thickness of only a few nm when x = 0.5. Therefore, the structure using the film thickness necessarily becomes a quantum structure. One embodiment of the present invention has been created based on this finding.

  One embodiment of the present invention is to provide a non-alloy layer with a quantum structure as a method capable of suppressing the occurrence of dislocations at the interface between the emitter contact layer and the non-alloy layer as a metal electrode contact layer formed thereon. suggest. Types of quantum structures include quantum wells, quantum wires, and quantum dots.

FIG. 2 shows a quantum structure in which a non-alloy layer provided as a metal electrode contact layer on a GaAs layer 19 constituting an emitter contact layer is also used as a superlattice buffer layer for relaxing strain at the interface between the non-alloy layer and GaAs 19. An example of a well structure is shown. The quantum well structure has a laminated structure in which an n-type In _x Ga _1-x As well layer 20 having a critical thickness or less and a very thin n-type GaAs barrier layer 21 formed thereon are laminated in a plurality of periods. It is configured. In the illustrated example, five cycles are stacked.

By adopting such a quantum well structure for the non-alloy layer, the film thickness is controlled so that the non-alloy layer has a desired in-plane resistance while suppressing the occurrence of dislocations at the interface between the GaAs layer 19 and the non-alloy layer. It can be so. The In composition of the In _x Ga _1-x As well layer is preferably x = 0.1-1. If the composition is in such a range, it exhibits metal-like properties compared to GaAs, and a large amount of n-type dopant can be doped into the In _x Ga _1-x As well layer.

As long as the In composition x is small, In _x Ga _1-x As performs two-dimensional growth, so that the quantum structure becomes a quantum well as described above. When the In composition x exceeds 0.5 to 0.7, the critical film thickness is on the order of several atomic layers, and the growth mode shifts from 2D to 3D, causing 3D growth and immediately stopping the growth. A large number of microcrystalline grains (quantum dots) 23 made of InGaAs as shown in FIG. The periphery of the quantum dots 23 is buried and grown with a very thin GaAs layer 24. The form of FIG. 3 is a form constituted by a laminated structure in which a very thin GaAs layer 24 including the quantum dots 23 made of InGaAs is laminated as one period. In the illustrated example, three periods are stacked.

  The quantum structure may be a quantum wire other than the above-described quantum well and quantum dot. Further, any of a heterojunction bipolar transistor, a field effect transistor, and a high electron mobility transistor can be applied to a non-alloy layer as the metal electrode contact layer.

  By configuring the metal electrode contact layer as shown in FIG. 2 or FIG. 3, it is possible to deposit a metal electrode contact layer that suppresses the occurrence of dislocations at the interface between the metal electrode contact layer and the n-type GaAs layer. Loss of electrical characteristics in the semiconductor element can be suppressed.

FIG. 1 shows the structure of an InGaP / GaAs HBT according to an embodiment of the present invention.
The InGaP / GaAs HBT is formed on a semi-insulating GaAs substrate by an MOVPE method, an n-type GaAs subcollector layer 7, an n-type GaAs collector layer 6, a collector layer 5 serving as a collector depletion region, and a p-type GaAs base layer 4 The n-type InGaP emitter layer 3, the n-type GaAs emitter contact layer 2, and the quantum structure non-alloy layer 25 are stacked. An emitter electrode 14 is formed on the quantum structure non-alloy layer 25, a base electrode 13 is formed on the p-type GaAs base layer 4, and a collector electrode 12 is formed on the n-type GaAs subcollector layer 7. In the case of grounded emitter, a positive voltage is applied from the power source 15 to the collector electrode 12 and a base current is supplied as a signal input from the base electrode 13 to control the collector current as an output.
The emitter electrode 14, the base electrode 13, and the collector electrode 12 are all metal electrodes.

The quantum structure non-alloy layer 25, n-type In _x Ga _1-x As relatively small and is grown two-dimensionally the In composition x of the critical film thickness or less of the n-type In _x Ga _1-x As layer and the n-type GaAs layer thin films are alternately stacked to form a quantum well structure. By forming the quantum structure non-alloy layer 25 into a periodic quantum well structure, the film thickness can be controlled so as to achieve a desired in-plane resistance while suppressing the generation of dislocations.

  In the above embodiment, the example of the HBT has been described, but the present invention can also be applied to an FET or a HEMT.

Second embodiment [non-alloy layer using a GaAs layer]
Next, a case where an n-type GaAs layer is used instead of the quantum structure for the metal electrode contact layer (non-alloy layer) will be described.

  When n-type GaAs is used for the non-alloy layer, since the same material as the n-type GaAs emitter contact layer below the non-alloy layer is used, no defect is generated at the epitaxial layer interface. However, in this case, a device for performing high-concentration n-type doping is necessary.

When the metal electrode contact layer is composed of a non-alloy layer made of n-type GaAs, it is difficult to do n-type doping to 1 × 10 ¹⁹ [cm ⁻³ ] or more if Si is used as the n-type dopant. For this reason, when GaAs is used as a non-alloy layer, Se is used as a dopant, and the growth rate is suppressed to about one third (0.3 to 0.7 nm / sec) as compared with the conventional method in order to achieve a higher concentration doping. increase. Further, the supply amount ratio between the Group V material and the Group III material, the so-called V / III ratio, is increased to reduce the C concentration atmosphere that causes p-type conversion.

As described above, according to the present embodiment, since the quantum structure is used for the metal electrode contact layer, it becomes possible to deposit an InGaAs layer in which the generation of dislocations is suppressed, and the electrical characteristics in the semiconductor element. Loss can be suppressed.
In addition, when GaAs is used for the metal electrode contact layer, it is grown at a rate slower than the growth rate of GaAs of the same material below the metal electrode contact layer, so that high-concentration n-type doping is performed efficiently. Can do. For this reason, good ohmic contact with the metal electrode can be obtained. Furthermore, since the V / III ratio is increased, the C concentration atmosphere that causes p-type conversion can be reduced.

  The film thickness of the non-alloy layer affects the in-plane resistance characteristics of the semiconductor element. For this reason, the film thickness of the non-alloy layer can be freely changed, and must be used as one of parameters for easily changing the in-plane resistance value of the semiconductor element. In this regard, according to the present embodiment, since the non-alloy layer is formed by stacking a plurality of cycles, the film thickness of the non-alloy layer can be freely changed, and the film thickness of the non-alloy layer can be used as the above parameter. .

<Example 1>
An n-type GaAs subcollector layer (film thickness) is formed by metal organic vapor phase epitaxy (MOVPE method) on a 4 inch diameter substrate slightly inclined by 2 ° in the [110] direction from the (001) plane of a semi-insulating GaAs substrate. 500 to 800 nm, carrier concentration 3 to 5 × 10 ¹⁸ cm ⁻³ ), n-type GaAs collector layer (film thickness 600 to 1200 nm, carrier concentration 1 × 10 ¹⁶ cm ⁻³ ), n-type GaAs collector layer (collector depletion region) ) (Film thickness 600 to 1200 nm, carrier concentration 1 × 10 ¹⁶ cm ⁻³ ).
Further, the p-type GaAs base layer 4 (film thickness 80 to 100 nm, carrier concentration 1 to 4 × 10 ¹⁹ cm ⁻³ ), n-type InGaP emitter layer (film thickness 30 to 100 nm, carrier concentration 3 to 5 × 10 ¹⁷ cm ^−3). ), An n-type GaAs emitter contact layer (film thickness of 80 to 200 nm, carrier concentration of 3 to 5 × 10 ¹⁸ cm ⁻³ ) and a quantum structure non-alloy layer were laminated to produce an InGaP / GaAs HBT epitaxial wafer.

Here, in the quantum structure non-alloy layer 25, an n-type In _0.1 Ga _0.9 As well layer having an In composition x = 0.1 and a thickness of 20 nm and an n-type GaAs barrier layer having a thickness of 50 nm are alternately grown for five periods. A quantum well structure was used.

The raw materials used were arsine (AsH ₃ ) as the As raw material, trimethylgallium (TMG) and triethylgallium (TEG) as the Ga raw material, trimethylindium (TMI) as the In raw material, and phosphine (PH ₃ ) as the phosphorus raw material. Using. Si and Se were used as n-type carrier dopants, and disilane (Si ₂ H ₆ ) and hydrogen selenide (H ₂ Se) were used as the raw materials. Further, C was used as a dopant for the p-type carrier, and carbon tetrabromide (CBr ₄ ) was used as the raw material.

  As a result of measuring the above-described large area HBT epitaxial wafer (diameter 4 inches) of Example 1 with a transmission electron microscope (TEM), no occurrence of dislocation was confirmed between the emitter contact layer and the non-alloy layer. Moreover, in the photoluminescence (PL) measurement, since light emission from the non-alloy layer could be confirmed, it was also found that a good crystal was formed.

  Then, this HBT epitaxial wafer is processed, and as shown in FIG. 1, the emitter electrode 14 is formed on the quantum structure non-alloy layer 25, the base electrode 13 is formed on the GaAs base layer 4, and the subcollector layer 7 is formed. A collector electrode 12 was formed on each of the electrodes to produce a characteristic evaluation HBT. The emitter electrode 14 of this HBT and the quantum structure non-alloy layer 25 were in good ohmic contact. Further, the HTB characteristics such as basic characteristics and high frequency characteristics of the HBT were good.

<Comparative Example 1>
In Example 1, except that an n-type In _0.2 Ga _0.8 As well layer with an In composition x = 0.2 and a film thickness of 20 nm and a GaAs barrier layer 50 nm were alternately grown for five periods on the quantum structure non-alloy layer 25. The HBT epitaxial wafer and the HBT were manufactured under the same conditions as in Example 1.

  As for the HBT characteristics in the structure of Comparative Example 1, good results could not be obtained depending on the location. When observed by TEM, dislocations as shown in FIG. 5 were confirmed in several places. Furthermore, misfit dislocations were also confirmed by observation with a planar TEM. In PL measurement, although light emission from the non-alloy layer was confirmed, only an intensity of about 50% with respect to the light emission intensity observed in Example 1 was obtained.

  From this, even when the In composition x is increased from 0.1 to 0.2 even with the same film thickness (20 nm), the amount of lattice mismatch at the interface between the GaAs layer and the InGaAs layer increases and dislocations (defects) occur. It becomes easy to enter and it can be seen that good crystals cannot be obtained.

<Example 2>
In Example 1, an epitaxial wafer for HBT and an HBT were formed under the same conditions as in Example 1 except that In _0.2 Ga _0.8 As and 10 nm-thick In _0.2 Ga _0.8 As and GaAs layers 50 nm were alternately grown for five periods. Was made.

  The characteristics of the epitaxial for HBT in a large area in the structure of Example 2 were good. As a result of measurement by TEM, the occurrence of dislocation was not confirmed. In PL measurement, light emission from the non-alloy layer could be confirmed. Here, the in-plane sheet resistance showed a value about twice that in Example 1. That is, the results suggest that the in-plane resistance can be controlled in proportion to the film thickness.

<Example 3>
In Example 1, an HBT epitaxial wafer and an HBT were produced under the same conditions as in Example 1 except that n-type GaAs was used as the material of the non-alloy layer that is the metal electrode contact layer. The n-type dopant used at this time is Se. When the growth rate used for the growth of the GaAs layer is about 1.0 to 2.0 nm / sec, the carrier concentration doped in the GaAs layer is 1.0 to 1.5 × 10 ¹⁹ [ cm ^-3 ]. Furthermore, when this growth rate is suppressed to about one third of that of the conventional one and the growth rate is reduced to 0.3 to 0.7 nm / sec, the carrier concentration is 1.5 to 2.0 × 10 ¹⁹ [cm ^−3. ], An increase of about 1.5 to 2 times was observed.

<Comparative example 2>
In Example 3, the epitaxial wafer for HBT was grown under the same conditions as in Example 3 except that the growth rate of GaAs was about 1.0 to 2.0 nm / sec and the V / III ratio was 10 to 100. And HBT were prepared. At this time, the carrier concentration was 1.1 to 1.3 × 10 ¹⁹ [cm ⁻³ ], and no significant change was observed. The intent of Comparative Example 2 was to reduce the autodoping of C by increasing the V / III ratio to reduce the p-type carrier, but it was not possible to obtain the effect as expected. This is presumably because the C concentration taken into the crystal by growth is on the order of 2 to 3 orders of magnitude smaller than the n-type doping concentration, so that there was almost no influence.

As described above, according to the present embodiment, an n-type In _x Ga _1-x As (x = 0.1-1) layer or an n-type GaAs layer in which the occurrence of dislocation is suppressed is deposited. Loss of electrical characteristics in the device can be suppressed.

Hereinafter, preferred embodiments of the present invention will be additionally described.
A first aspect is an InGaP / GaAs semiconductor wafer having an n-type InGaP emitter layer, an n-type GaAs emitter contact layer, and a metal electrode contact layer for contacting the emitter electrode on an n-type GaAs substrate. The quantum structure is composed of an n-type In _x Ga _1-x As (x = 0.1-1) layer having a critical thickness or less and an n-type GaAs layer provided thereon. It is characterized by being configured by laminating a plurality of periods with one period as one period.

  According to a second aspect, in the first aspect, the metal electrode contact layer composed of the quantum structure is a non-alloy layer, and the quantum structure is any one of a quantum dot, a quantum wire, or a quantum well. It is characterized by.

According to a third aspect, in the first aspect, the metal electrode contact layer is composed of an n-type GaAs layer doped with Se at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more instead of the quantum structure. It is characterized by that.

  According to a fourth aspect, in the first to third aspects, the InGaP / GaAs semiconductor wafer is any one of a heterojunction bipolar transistor, a field effect transistor, and a high electron mobility transistor.

According to a fifth aspect of the present invention, there is provided a method of manufacturing an InGaP / GaAs semiconductor wafer having an n-type InGaP emitter layer, an n-type GaAs emitter contact layer, and a metal electrode contact layer for contacting the emitter electrode on an n-type GaAs substrate. The metal electrode contact layer is formed with a quantum structure, and the quantum structure includes an n-type In _x Ga _1-x As (x = 0.1-1) layer having a critical thickness or less and an n-type GaAs layer provided thereon. Is formed by laminating a plurality of periods.

  According to a sixth aspect, in the fifth aspect, the metal electrode contact layer composed of the quantum structure is a non-alloy layer, and the quantum structure is any one of a quantum dot, a quantum wire, or a quantum well. It is characterized by.

According to a seventh aspect, in the fifth aspect, the metal electrode contact layer is formed of an n-type GaAs layer doped with Se at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more, instead of forming the metal electrode contact layer with the quantum structure. The GaAs layer is grown later than when the GaAs layer under the metal electrode contact layer is grown.

  An eighth aspect is characterized in that, in the fifth to seventh aspects, the InGaP / GaAs semiconductor wafer is any of a heterojunction bipolar transistor, a field effect transistor, and a high electron mobility transistor.

It is sectional drawing which shows the structure of HBT which concerns on one Embodiment of this invention. It is sectional drawing of the non-alloy layer and GaAs emitter contact layer of InGaAs / GaAs quantum structure concerning one embodiment of the present invention. It is sectional drawing of the non-alloy layer and GaAs emitter contact layer of the InGaAs / GaAs quantum dot structure concerning the modification of one Embodiment of this invention. It is sectional drawing which shows the structure of the conventional HBT. It is a figure which shows the mode of the dislocation of an InGaAs / GaAs interface. It is an energy band figure of the conventional HBT.

Explanation of symbols

1 Non-alloy layer (n-type InGaAs)
2 Emitter contact layer (n-type GaAs)
3 Emitter layer (n-type InGaP)
4 Base layer (p-type GaAs)
5 Collector (collector depletion region) layer (n-type GaAs)
6 Collector layer (n-type GaAs)
7 Subcollector layer (n-type GaAs)
8 Electron 9 Lower end of conduction band 10 Upper end of valence band 11 Fermi level 12 Collector electrode 13 Base electrode 14 Emitter electrode 15 Power source 16 GaAs layer 17 In _x Ga _1-x As layer 18 Dislocation 19 GaAs layer (emitter contact layer)
20 n-type In _x Ga _{1 -x} As well layer 21 n-type GaAs barrier layer 22 GaAs layer (emitter contact layer)
23 Quantum dot 24 GaAs layer 25 Quantum structure non-alloy layer

Claims (12)

In a semiconductor device using a III-V compound semiconductor,
An emitter electrode and a metal electrode contact layer in contact with the emitter electrode;
A semiconductor device, wherein the metal electrode contact layer has a quantum structure. The semiconductor device according to claim 1,
The quantum structure is configured by laminating a plurality of periods, each including an In _x Ga _1-x As (x = 0.1-1) layer having a critical thickness or less and a GaAs layer provided thereon. A semiconductor device characterized by the above. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the metal electrode contact layer formed of the quantum structure is a non-alloy layer. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the quantum structure is one of a quantum dot, a quantum wire, or a quantum well. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the metal electrode contact layer is formed of an n-type GaAs layer doped with Se at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more instead of the quantum structure. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device is a heterojunction bipolar transistor, a field effect transistor, or a high electron mobility transistor. In a method for manufacturing a semiconductor device using a group III-V compound semiconductor having an emitter electrode and a metal electrode contact layer in contact with the emitter electrode,
A method of manufacturing a semiconductor device, wherein the metal electrode contact layer is formed with a quantum structure. In the manufacturing method of the semiconductor device according to claim 7,
The quantum structure is formed by laminating a plurality of periods, each including an In _x Ga _1-x As (x = 0.1-1) layer having a critical film thickness or less and a GaAs layer provided thereon. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 7 or 8,
The metal electrode contact layer comprised by the said quantum structure is a non-alloy layer, The manufacturing method of the semiconductor device characterized by the above-mentioned. In the manufacturing method of the semiconductor device in any one of Claims 7 thru | or 9,
The method of manufacturing a semiconductor device, wherein the quantum structure is one of a quantum dot, a quantum wire, or a quantum well. In the manufacturing method of the semiconductor device according to claim 7,
The metal electrode contact layer is formed of an n-type GaAs layer doped with Se at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more instead of forming the quantum structure.
A method of manufacturing a semiconductor device, wherein a growth rate of the GaAs layer is slower than a growth rate of a GaAs layer under the metal electrode contact layer. In the manufacturing method of the semiconductor device according to claim 7,
A method of manufacturing a semiconductor device, wherein the semiconductor device is a heterojunction bipolar transistor, a field effect transistor, or a high electron mobility transistor.

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