TWI495099B - Heterojunction bipolar transistor with improved current gain and a fabrication method thereof - Google Patents

Description

Heterojunction bipolar crystal structure with high current gain and its manufacturing method

The invention relates to a modified structure of a heterojunction bipolar transistor and a process method thereof, in particular to a component using a p-type doping buffer layer between a collector layer of a heterojunction bipolar transistor and a substrate A modified structure of a heterojunction bipolar transistor that achieves high current gain properties and a process method thereof.

High current gain Heterojunction Bipolar Transistor (HBT) has the advantages of high efficiency, high linearity, high power density and small area. It is often used in wireless communication as a microwave power amplifier, which is very important in the communication electronics market. One of the important components.

Figure 1 is a schematic cross-sectional view showing the structure of an epitaxial layer of a conventional heterojunction bipolar transistor. The epitaxial layer structure is formed on a substrate 101, and includes a primary collector layer 107, a collector layer 109, a base layer 111, an emitter layer 113, an emitter cover layer 115, and an emitter. Contact layer 117.

After the layered structure of the element is sequentially grown by epitaxy, the process of the base electrode 121, the collector electrode 119 and the emitter electrode 123 can be performed. First, a conventional electrode exposure and etching process technology can be used to define a base electrode contact region and a collector electrode contact region. By controlling the etching process, the etching process of the base electrode contact region can be terminated at the base layer 111. The etching process of the collector electrode contact region is etched to terminate in the sub-collector layer 107; the base electrode 121 is disposed in the base electrode contact region and forms an ohmic contact with the base layer 111; in the collector electrode contact region Set this The collector electrode 119 is in ohmic contact with the sub-collector layer 107. The emitter electrode 123 is disposed directly over the emitter contact layer 117 and forms an ohmic contact.

In the case of a conventional heterojunction bipolar transistor structure, achieving high current gain characteristics is not easy. It is generally believed that the current gain characteristics of the component are highly correlated with the crystal quality of the collector or subcollector. It is currently known that there are two major factors contributing to the current gain of an element. The first factor is the lattice dislocation defect in the substrate 101, which usually propagates up to the sub-collector during the epitaxy process, thereby affecting the component current gain of the heterojunction bipolar transistor. The second factor is the high concentration doping of the secondary collector layer. In general, in order to improve the element characteristics of the transistor, it is necessary to lower the resistivity of the collector electrode 119, usually by increasing the n-type doping concentration of the sub-collector layer 107 (usually the doping impurity is 矽Si), but As the doping concentration increases, the epitaxial defect density of the sub-collector layer 107 also increases, which in turn causes the current gain to decrease.

In order to solve the above first factor, the prior art has proposed a method for effectively suppressing the lattice misalignment defects of the substrate from extending upward to the element layer, thereby improving the current gain of the element. As shown in FIG. 2, it is a schematic cross-sectional view of an epitaxial layer structure of another prior art heterojunction bipolar transistor. This structure is substantially the same as the structure shown in FIG. 1, except that a buffer layer 103 is provided between the substrate 101 and the sub-collector layer 107. The material of the buffer layer 103 is oxygen-doped aluminum gallium arsenide (i-AlGaAs: O), thereby suppressing the lattice misalignment defect of the substrate 101 to the sub-collector layer of the upper layer element, thereby making the heterojunction double The polar crystal maintains a high current gain.

For the second factor described above, another prior art also proposes another element structure that can improve the problem of a decrease in component current gain due to heavy doping of the collector layer 107. As shown in Fig. 3, it is a schematic cross-sectional view of the epitaxial layer structure. The main structure is substantially the same as the structure shown in Fig. 1, except that the substrate 101 and the sub-set Between the pole layers 107, a single atom doped layer 105 is further disposed. The monoatomic doped layer 105 is a doped layer (also referred to as a δ-doped layer or a planar doping layer) having a thickness of only a single atomic layer, and the doping element is usually yttrium (Si). The defect of the collector layer 107 due to heavy doping is suppressed, and the transistor is maintained at a high current gain.

In order to simultaneously solve the above two factors affecting the current gain of the component, the present invention provides an improved structure of a heterojunction bipolar transistor and a process method thereof, which can not only inhibit the transfer of the lattice displacement defect of the substrate 101 to the component structure layer, but also The defects of the collector layer 107 due to heavy doping are suppressed. In addition to solving the above problems, the improved structure of the present invention can simultaneously reduce the resistivity of the collector electrode 119, thereby improving the current gain of the device and the reliability of the device characteristics.

The main object of the present invention is to provide a modified structure of a heterojunction bipolar transistor and a process method thereof, wherein a p-type doping buffer layer is added between the substrate and the sub-collector layer, thereby absorbing the sub-collector layer. During the epitaxial process, gallium (Ga) vacancies due to heavy doping of bismuth (Si) are suppressed, and lattice misalignment defects of the substrate are suppressed from being transmitted to the element layer. By selecting appropriate materials and doping elements constituting the p-type doping buffer layer and optimizing the doping concentration, the transistor structure of the desired characteristics can be adjusted, and the on-resistance can be greatly reduced, thereby further reducing the on-resistance. Improve the current gain of components and the reliability of component characteristics.

In order to achieve the above object, the present invention provides a modified structure of a heterojunction bipolar transistor, which comprises a substrate, a p-type doped buffer layer, a primary collector layer, a collector layer, and a base from bottom to top. a pole layer and an emitter layer; at one end of the base layer, a base electrode is disposed; and a collector electrode is disposed at one end of the collector layer; An emitter electrode is disposed on the pole layer.

The invention also provides a method for fabricating a modified structure of a heterojunction bipolar transistor, comprising the steps of: sequentially forming a p-type doped buffer layer, a primary collector layer, a collector layer, and a base on a substrate. a pole layer and an emitter layer; a base electrode contact region is defined on the emitter layer by exposure development, and the base electrode contact region is etched, and the etching process is controlled to terminate the etching process at the base a layer; a collector electrode contact region is defined by the exposure developing technique, and the collector electrode contact region is etched to terminate the etching process in the collector layer; at the base a base electrode is disposed on the base layer in the electrode contact region, and the base electrode is in ohmic contact with the base layer; and a collector is disposed on the sub-collector layer in the contact region of the collector electrode An electrode, and the collector electrode is in ohmic contact with the sub-collector; and an emitter electrode is disposed on the emitter layer to form an ohmic contact with the emitter layer.

In an implementation, in the above structure and method, an emitter cap layer is disposed between the emitter layer and the emitter electrode, and the emitter electrode is in ohmic contact with the emitter cap layer. In addition, an emitter contact layer may be disposed between the emitter layer and the emitter electrode, and the emitter electrode and the emitter contact layer may be in ohmic contact, and the emitter layer may be coupled to the emitter layer. An emitter cover layer is disposed between the contact layers.

In implementation, the semiconductor material structure constituting the p-type doping buffer layer may be Gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), indium aluminum phosphide (InAlP), indium gallium arsenide (InGaAsP) or aluminum gallium indium phosphide (AlGaInP).

In the implementation, the doping material constituting the p-type doping buffer layer may be carbon (C), zinc (Zn), magnesium (Mg), beryllium (Be), sulfur (S), antimony (Te), Or a combination of the above materials.

In the implementation, the preferred thickness of the p-type doped buffer layer is greater than 10 Å and less than 10,000 Å.

For a better understanding of the features and functions of the present invention, the embodiments are described in detail below with reference to the drawings.

4 is a schematic cross-sectional view showing an epitaxial layer structure of the heterojunction bipolar transistor improved structure of the present invention, comprising a substrate 201, a p-type doping buffer layer 203, a primary collector layer 207, and a collector layer. 209, a base layer 211, an emitter layer 213, a collector electrode 219, a base electrode 221, and an emitter electrode 223.

In the construction of the present invention, the substrate 201 can typically be a semi-insulating gallium arsenide (GaAs) substrate. The p-type doped buffer layer 203 is formed on the substrate 201 by an epitaxial growth technique. Conventional epitaxial growth techniques include Molecular Beam Epitaxy (MBE) technology or Metal-organic Chemical Vapor Deposition (MOCVD) technology. The p-type doped buffer layer material may be gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), indium phosphide (InAlP), indium gallium arsenide (InGaAsP) or Aluminum gallium indium phosphide (AlGaInP); and wherein the doping material of the p-type doping buffer layer is a combination of carbon (C), zinc (Zn), magnesium (Mg), bismuth (Be), sulfur (S), cerium (Te), or the like; and the thickness of the p-type doping buffer layer is More than 10 Å less than 10000 Å. After the p-type doping buffer layer 203 is formed, the epitaxial layer 207 can be grown by epitaxial growth. Usually, the collector layer 207 is made of n-type gallium arsenide (GaAs), and is usually doped with a high concentration of germanium (Si). The collector layer 209 is formed on the sub-collector layer 207. Usually, the collector layer 209 is also made of n-type gallium arsenide (GaAs), and is usually doped with germanium (Si). The base layer 211 is formed on the collector layer 209 and is composed of p-type gallium arsenide (GaAs), and the doping material is usually carbon (C) or other p-type dopant material. Finally, the epitaxial layer structure is formed on the base layer 211 by forming the emitter layer 213. The emitter layer 213 is composed of n-type indium gallium phosphide (InGaP), and the doping material is usually矽 (Si).

Figure 8 is a flow chart showing one embodiment of a process for improving the structure of the heterojunction bipolar transistor of the present invention. As shown in step A, the layered structure of the element is sequentially grown by the epitaxial growth technique, and then the steps of the base electrode, the collector electrode and the emitter electrode are performed as shown in steps B to F. First, a base electrode contact region can be defined on the emitter layer 213 by using a conventional exposure and development technique, and the emitter layer 213 located in the contact region of the base electrode is removed by a dry etching or wet chemical etching process. Etching process time or selecting a suitable solution in the wet etching process to achieve selective etching between the emitter and the base layer material, so that the etching terminates at the base layer 211; after the base electrode contact region is completed, Forming a collector electrode contact region by exposure development technology within the base electrode contact region; etching the base layer 211 and the collector layer 209 located in the collector electrode contact region, and etching by controlling the etching process Terminating in the secondary collector layer 207; providing a base electrode 221 in the base electrode contact region, and causing the base electrode 221 to form an ohmic contact with the base layer 211; A collector electrode 219 is disposed in the contact region of the electrode, and the collector electrode 219 is in ohmic contact with the collector layer 207; an emitter electrode 223 is disposed on the emitter layer 213, and the emitter electrode is disposed 223 forms an ohmic contact with the emitter layer 213.

Please refer to FIG. 5, which is a schematic cross-sectional view of another embodiment of the present invention. The main structure is substantially the same as that of the embodiment shown in FIG. 4. However, an emitter cover layer 215 is disposed between the emitter layer 213 and the emitter electrode 223. Generally, the emitter cover layer 215 is 矽. (Si) doped n-type gallium arsenide (GaAs) is preferably formed. The emitter cap layer 215 may also be an n-type aluminum gallium arsenide (AlGaAs) layer or a plurality of layers of n-type gallium arsenide layer/arsenic. A mixture of aluminum gallium (GaAs/AlGaAs) layers is formed; because of the arrangement of the emitter cap layer 215, an etching process is added to the base electrode contact region (step B of FIG. 8), and the etching is performed first. An emitter cover layer 215 in the base electrode contact region, and then an emitter layer 213 located in the contact region of the base electrode; an emitter electrode 223 is disposed on the emitter cap layer 215, and the emitter is disposed Electrode 223 forms an ohmic contact with the emitter cap layer 215.

Referring to FIG. 6 again, it is a schematic cross-sectional view of another embodiment of the present invention. The main structure is substantially the same as that of the embodiment shown in FIG. 4, except that an emitter contact layer 217 is disposed between the emitter layer 213 and the emitter electrode 223. Generally, the emitter contact layer 217 is n. Indium gallium arsenide (InGaAs), the doping material is preferably made of bismuth (Te) or bismuth (Si); etching the emitter layer 213 in the contact region of the base electrode (Fig. 8 Prior to step B), an etching process is added to etch the emitter contact layer 217; in this configuration, the emitter electrode 223 is in ohmic contact with the emitter contact layer 217.

Referring to FIG. 7, FIG. 7 is a schematic cross-sectional view showing another embodiment of the present invention. The main structure is substantially the same as the embodiment shown in Fig. 6, but An emitter cap layer 215 is disposed between the emitter layer 213 and the emitter contact layer 217. Generally, the emitter cap layer 215 is made of n-type gallium arsenide (GaAs), n-type aluminum gallium arsenide (AlGaAs), Or a mixture of n-type gallium arsenide/aluminum gallium arsenide (GaAs/AlGaAs), the doping material is preferably a material such as germanium (Si); when the base electrode contact region is formed, the etching is located at the An emitter etching process is performed between the emitter contact layer 217 in the contact region of the base electrode and the emitter layer 213 in the contact region of the base electrode for etching the emitter cover in the contact region of the base electrode. Layer 215.

In summary, the present invention can achieve the intended purpose, and provides a heterojunction bipolar transistor which uses a p-type doping buffer layer to improve current gain in a buffer layer, and greatly reduces its on-resistance. The amplification efficiency of the amplifier can be enhanced at the same time, and the current gain is increased. The present invention also provides a process method for producing good component reliability. It does have the value of industrial use, and patent applications are filed according to law.

The above description and drawings are merely illustrative of the embodiments of the present invention, and those of ordinary skill in the art can

101‧‧‧Substrate

103‧‧‧buffer layer

105‧‧‧monoatomic doped layer

107‧‧‧ times collector

109‧‧‧ Collector

111‧‧‧ base layer

113‧‧ ‧ emitter layer

115‧‧ ‧ emitter cover

117‧‧ ‧ emitter contact layer

119‧‧‧ Collector electrode

121‧‧‧ base electrode

123‧‧ ‧ emitter electrode

201‧‧‧Substrate

203‧‧‧p type doping buffer layer

207‧‧‧ times collector

209‧‧‧ Collector

211‧‧‧ base layer

213‧‧ ‧ emitter layer

215‧‧ ‧ emitter cover

217‧‧ ‧ emitter contact layer

219‧‧‧ Collector electrode

221‧‧‧ base electrode

223‧‧ ‧ emitter electrode

Figure 1 is a schematic cross-sectional view showing the structure of an epitaxial layer of a conventional heterojunction bipolar transistor.

Figure 2 is a schematic cross-sectional view showing the epitaxial layer structure of another prior art heterojunction bipolar transistor.

Fig. 3 is a schematic cross-sectional view showing the structure of an epitaxial layer of a heterojunction bipolar transistor of the prior art.

4 to 7 are schematic cross-sectional views showing the structure of the epitaxial layer of several embodiments of the heterojunction bipolar transistor modified structure of the present invention.

Figure 8 is a flow chart showing one embodiment of a process for improving the structure of a heterojunction bipolar transistor of the present invention.

201‧‧‧Substrate

203‧‧‧p type doping buffer layer

207‧‧‧ times collector

209‧‧‧ Collector

211‧‧‧ base layer

213‧‧ ‧ emitter layer

215‧‧ ‧ emitter cover

217‧‧ ‧ emitter contact layer

219‧‧‧ Collector electrode

221‧‧‧ base electrode

223‧‧ ‧ emitter electrode

Claims (15)

A heterojunction bipolar transistor structure comprising: a substrate; a p-type doped buffer layer formed on the substrate; a primary collector layer formed on the p-type doped buffer layer; a collector layer is formed on the sub-collector layer; a base layer is formed on the collector layer; an emitter layer is formed on the base layer; a collector electrode, Is disposed at one end of the collector layer; a base electrode is disposed at one end of the base layer; an emitter electrode is disposed on the emitter layer; wherein the p-type doped buffer layer The doping material is selected from the group consisting of carbon (C), zinc (Zn), magnesium (Mg), beryllium (Be), sulfur (S), tellurium (Te), and combinations thereof. Things. The heterojunction bipolar transistor structure according to claim 1, wherein the material constituting the p-type doping buffer layer is gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium phosphide. Gallium (InGaP), indium phosphide (InAlP), indium gallium arsenide (InGaAsP) or aluminum gallium indium phosphide (AlGaInP). The high current gain heterojunction bipolar transistor structure according to claim 1, wherein the p-type doping buffer layer has a thickness greater than 10 Å and less than 10000 Å. The heterojunction bipolar transistor structure of claim 1, wherein an emitter cover layer is disposed between the emitter layer and the emitter electrode. The heterojunction bipolar transistor structure of claim 4, wherein an emitter contact layer is disposed between the emitter cover layer and the emitter electrode. The heterojunction bipolar transistor structure of claim 1, wherein an emitter contact layer is disposed between the emitter layer and the emitter electrode. A method for fabricating a modified structure of a heterojunction bipolar transistor comprises the steps of: sequentially forming a p-type doped buffer layer, a primary collector layer, a collector layer, a base layer, and a substrate on a substrate An emitter layer; a base electrode contact region is defined by exposure development technology, and the base electrode contact region is etched, and the etching process is terminated to control the etching process to terminate the base layer; and the base electrode contact region is a collector electrode contact region is defined by exposure development technology, and the collector electrode contact region is etched, and the etching process is terminated by the etching process to terminate the etching in the collector layer; a collector electrode, and the collector electrode is in ohmic contact with the sub-collector; in the base electrode contact region, a base electrode is disposed on the base layer, and the base electrode is The base layer forms an ohmic contact; and on the emitter layer, an emitter electrode is disposed. The process of claim 7, wherein the material constituting the p-type doping buffer layer is gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), phosphorus. Indium aluminum (InAlP), indium gallium arsenide (InGaAsP) or aluminum gallium indium phosphide (AlGaInP). The process method of claim 7, wherein the p-type doping buffer The doping material of the layer is selected from the group consisting of carbon (C), zinc (Zn), magnesium (Mg), beryllium (Be), sulfur (S), tellurium (Te), and the foregoing materials. Composition. The process of claim 7, wherein the p-type doped buffer layer has a thickness greater than 10 Å and less than 10,000 Å. The process of claim 7, wherein the emitter electrode is in ohmic contact with the emitter layer. The process of claim 7, wherein an emitter cover layer is disposed between the emitter layer and the emitter electrode. The process of claim 12, wherein the emitter electrode is in ohmic contact with the emitter cap layer. The process of claim 12, wherein an emitter contact layer is further disposed between the emitter cover layer and the emitter electrode, and the emitter electrode layer and the emitter contact layer are formed. Ohmic contact. The process of claim 7, wherein an emitter contact layer is disposed between the emitter layer and the emitter electrode, and the emitter electrode layer and the emitter contact layer form an ohmic layer. contact.