JP2013074142A - Method for manufacturing epitaxial wafer for transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an epitaxial wafer for transistors capable of reducing a growth time to improve throughput.SOLUTION: A method for manufacturing an epitaxial wafer for transistors comprises the steps of: forming a high electron mobility transistor structure layer 3 including electron supply layers 6 and 10 and a channel layer 8 on a substrate 2; and forming a hetero-bipolar transistor structure layer 4 including a collector layer 14, a base layer 15, an emitter layer 16 and a non-alloy layer 18 on the high electron mobility transistor structure layer 3. The hetero-bipolar transistor structure layer 4 is grown at a constant growth temperature between 400°C or more and 600°C or less by a vapor phase growth method.

Description

  The present invention relates to a method for manufacturing an epitaxial wafer for a transistor, comprising: a step of forming a high electron mobility transistor structure layer on a substrate; and a step of forming a heterobipolar transistor structure layer on the high electron mobility transistor structure layer. Is.

  In power amplifiers for communication terminal equipment, hetero bipolar transistors (hereinafter referred to as HBT) and high electron mobility transistors (hereinafter referred to as HEMT) formed using compound semiconductors are used. It has been.

  First, a hetero bipolar transistor (HBT) will be described.

  The operation of the HBT is basically the same as that of a normal bipolar transistor (hereinafter referred to as BJT). In the npn-type BJT, the amount of electrons flowing from the emitter to the collector is controlled by the base current (hole current), thereby operating as a transistor. That is, the collector current increases by increasing the Hall current. However, if the hole current is further increased, holes leak from the base toward the emitter, and the current amplification factor of the transistor decreases.

  On the other hand, in an npn-type HBT configured using a semiconductor material having a large band gap for the emitter, a barrier is formed at the base-emitter interface, and holes can be prevented from leaking to the emitter. As a result, the HBT has an advantage that the collector current can be increased without reducing the current amplification factor.

A typical structure of HBT is shown in FIG. As shown in FIG. 4, the HBT 31 has a semi-insulating GaAs substrate 32 on which an n-type GaAs layer serving as a subcollector layer 33 is 500 nm, an n-type GaAs layer serving as a collector layer 34 is 700 nm, and a p-layer serving as a base layer 35. The n-type In _x Ga _1-x P layer (x = 0.48) serving as the emitter layer 36 is 40 nm, the n-type GaAs layer serving as the emitter contact layer 37 is 100 nm, and the graded non-alloy layer 38 The n-type In _x Ga _1-x As layer (x = 0 → 0.5) to be 50 nm and the n-type In _x Ga _1-x As layer (x = 0.5) to be the uniform composition non-alloy layer 39 are 50 nm. They are laminated in order.

  Next, a high electron mobility transistor (HEMT) will be described.

  The HEMT has an InGaAs layer as a channel layer and has an electron supply layer on both sides or one side of the channel layer. Heterojunction HEMTs can not only operate at high speed by taking advantage of the high-speed movement of electrons, but also can operate at high power and high efficiency in an ultrahigh frequency band such as a microwave band.

A typical structure of the HEMT is shown in FIG. As shown in FIG. 5, the HEMT 41 becomes an undoped GaAs layer serving as the buffer layer 43, an n-type Al _x Ga _1-x As layer serving as the electron supply layer 44, and a spacer layer 45 on the semi-insulating GaAs substrate 42. undoped Al _x Ga _1-x as layer, an undoped a channel layer 46 In _x Ga _1-x as layer, an undoped Al _x Ga _1-x as layer as the spacer layer 47, the electron supply layer 48 n-type Al _x A Ga _1-x As layer and an n-type GaAs layer serving as a cap layer 49 are sequentially stacked.

In FIG. 4, n ⁺ , n, and n ⁻ are used as the notation indicating the carrier concentration. These are examples of the carrier concentration. ¹⁸ or more, no mark 10 ¹⁷ units, - which is attached represents a 10 ¹⁴ or more 10 than ¹⁷ at a low carrier concentration. 4 and 5, n- means n-type, p- means p-type, and un- means undoped.

  These transistors have been mainly used for power amplifiers for transmitting and receiving mobile terminals, but in recent years, not only voice and text data but also large-capacity and diverse information such as moving images have been required to be transmitted and received at high speed. . For this reason, the power amplifier for transmission / reception, which is the component that consumes the largest amount of power in the portable terminal, is also required to have high performance, and it is required to operate at a low voltage and to reduce power consumption. These requirements can be met by increasing the efficiency of the power amplifier, but generally, when the amplifier is operated with high efficiency, there is a problem that distortion of the output signal becomes large. When the distortion of the output signal increases, there is a problem that radio waves leak to adjacent communication channels due to the distortion, the signals interfere with each other, and the transmission data has different values.

  Therefore, by using multiple HMTs with high current drive capability and HEMTs with low power consumption and good high frequency noise characteristics in one power amplifier module, distortion of the output signal can be suppressed and power consumption can be reduced, resulting in high amplitude. A power amplifier module that can obtain an output signal is used. For example, the power amplifier module 51 shown in FIG. 6 is configured to amplify the input signal by the driving HBT 52 and further amplify the amplified signal by the output HEMT 53 at the subsequent stage to produce an output signal.

  However, when the HBT 52 and the HEMT 53 are connected by wiring as in the power amplifier module 51 of FIG. 6, RC delay due to the wiring and heat generation of the elements become problems.

  Therefore, a transistor having a two-stage transistor structure (BI-FET structure) in which this wiring is eliminated, a HEMT is provided by epitaxial growth on a substrate, and an HBT is further provided on the HEMT is used (for example, Patent Document 1). reference).

JP 2006-228784 A

  However, when manufacturing an epitaxial wafer for a transistor having a BI-FET structure as described above, a plurality of epitaxial layers constituting the HBT are grown on the plurality of epitaxial layers constituting the HEMT. In order to change the growth temperature for each epitaxial layer when growing a plurality of epitaxial layers constituting the HBT, in addition to the time for forming the epitaxial layer, in order to stabilize the temperature and the time for changing the temperature This requires a separate time, and the total growth time becomes long and the throughput is lowered.

  Accordingly, an object of the present invention is to provide a method for manufacturing an epitaxial wafer for a transistor that can solve the above-described problems and can improve the throughput by shortening the growth time.

  The present invention was devised to achieve the above object, and includes a step of forming a high electron mobility transistor structure layer having an electron supply layer and a channel layer on a substrate, and the high electron mobility transistor structure layer. Forming a heterobipolar transistor structure layer having a collector layer, a base layer, an emitter layer, and a non-alloy layer thereon, wherein the heterobipolar transistor structure layer is formed by vapor deposition. Thus, the epitaxial wafer for a transistor is grown at a growth temperature of 400 ° C. or more and 600 ° C. or less and at a constant growth temperature.

  The electron supply layer may be an n-type AlGaAs layer doped with Si.

  The dopant of the electron supply layer may be selected from any of Si, Se, and Te.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the epitaxial wafer for transistors which can shorten a growth time and can improve a throughput can be provided.

It is a laminated structure figure of the epitaxial wafer for transistors manufactured with the manufacturing method of the epitaxial wafer for transistors concerning one embodiment of the present invention. It is a graph which shows the relationship between the growth time and substrate temperature (growth temperature) in this invention. It is a graph which shows the relationship between the growth time and substrate temperature (growth temperature) in a prior art. It is a laminated structure figure of HBT. It is a laminated structure figure of HEMT. It is a circuit diagram of the conventional power amplifier module.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a stacked structure diagram of a transistor epitaxial wafer manufactured by the method for manufacturing a transistor epitaxial wafer according to the present embodiment.

  As shown in FIG. 1, a transistor epitaxial wafer 1 has a high electron mobility transistor structure layer (hereinafter referred to as a HEMT structure layer) 3 formed on a GaAs substrate 2, and a heterobipolar transistor structure layer on the HEMT structure layer 3. (Hereinafter referred to as an HBT structure layer) 4 is formed (BI-FET structure). In FIG. 1, n- means n-type, p- means p-type, and un- means undoped.

When manufacturing the epitaxial wafer 1 for transistors, first, an undoped Al _x Ga _1-x As layer (x = 0.28) to be the buffer layer 5 is epitaxially grown on the semi-insulating GaAs substrate 2 by 500 nm. The n-type Al _x Ga _1-x As layer (x = 0.3) serving as the electron supply layer 6 is 30 nm, and the undoped Al _x Ga _1-x As layer (x = 0.3) serving as the spacer layer 7 is 10 nm. The undoped In _x Ga _1-x As layer (x = 0.18) serving as the channel layer 8 is 15 nm, the undoped Al _x Ga _1-x As layer (x = 0.3) serving as the spacer layer 9 is 10 nm, electrons The HEMT structure layer 3 is formed by sequentially stacking an n-type Al _x Ga _1-x As layer (x = 0.48) to be the supply layer 10 and an undoped GaAs layer to be the Schottky layer 11 in order of 30 nm. To do. In the present embodiment, the HEMT structure layer 3 is grown by vapor phase epitaxy (MOVPE (Metal Organic Vapor Phase Epitaxy) method) under conditions of a growth temperature of 600 ° C. or more and 750 ° C. or less and a V / III ratio of 150 or less. In the present specification, the growth temperature means the substrate temperature of the GaAs substrate 2 during growth.

  The electron supply layers 6 and 10 of the HEMT structure layer 3 are made of Si δ-doped layers. That is, the electron supply layers 6 and 10 are made of an n-type AlGaAs layer doped with Si. Note that the δ-doped layer is a region where a dopant (Si in this case) is locally contained at a high concentration, and does not exist as a layer having a reduced scale as shown in FIG. That is, in FIG. 1, the scale of each layer is changed for convenience, and the structure of the transistor epitaxial wafer 1 is schematically shown. Although the electron supply layers 6 and 10 are n-type AlGaAs layers here, they may be n-type InGaP layers. Moreover, although Si was used as the dopant, the dopant of the electron supply layers 6 and 10 may be selected from any of Si, Se, and Te.

On the HEMT structure layer 3 (between the HEMT structure layer 3 and the HBT structure layer 4), an n-type In _x Ga _1-x P layer (x = 0.48) is laminated to 10 nm by epitaxial growth to form an etching stopper layer. (Stopper layer) 12 is formed. In the present embodiment, the etching stopper layer 12 made of InGaP in which the As mixing concentration is controlled at the same or lower growth temperature than the HEMT structure layer 3 is formed.

After that, on the etching stopper layer 12, by epitaxial growth, the n-type GaAs layer to be the subcollector layer 13 is 500 nm, the n-type GaAs layer to be the collector layer 14 is 700 nm, the p-type GaAs layer to be the base layer 15 is 120 nm, the emitter An n-type In _x Ga _1-x P layer (x = 0.48) to be the layer 16 is sequentially stacked to 40 nm, an n-type GaAs layer to be the ballast layer 17 is sequentially stacked to 100 nm, and a non-alloy layer 18 is stacked on the ballast layer 17. Thus, the HBT structure layer 4 is formed.

The non-alloy layer 18 includes a graded non-alloy layer 19 made of n-type In _x Ga _1-x As, doped with Se or Te as an n-type impurity, and changed in composition in the growth direction, and a graded non-alloy layer 19. And a uniform composition non-alloy layer 20 made of n-type In _x Ga _1-x As and having a constant In composition ratio of 0.3 to 0.6.

In the present embodiment, the graded non-alloy layer 19 is configured so that the In composition ratio gradually changes from 0 to the same In composition ratio as the uniform composition non-alloy layer 20 as the distance from the ballast layer 17 increases. The carbon in the graded non-alloy layer 19 is adjusted by appropriately adjusting the substrate temperature (growth temperature) and the temperature of the heater for heating the GaAs substrate 2 to adjust the gradient of the In composition ratio and the amount of auto-doped carbon. 50 nm so that the n-type impurity concentration is in the range of 1.0 × 10 ¹⁸ cm ^{−3 to} 5.0 × 10 ¹⁹ cm ⁻³ so that the concentration is 3.0 × 10 ¹⁸ cm ⁻³ or less. N-type In _x Ga _1-x As layers (x = 0 → 0.5) were grown.

In the present embodiment, the uniform composition non-alloy layer 20 is made constant at an In composition ratio of 0.5, and the amount of auto-doped carbon is adjusted similarly to the graded non-alloy layer 19. The n-type impurity concentration is 1.0 × 10 ¹⁹ cm ⁻³ or more and 5.0 × 10 ¹⁹ cm ⁻³ or less so that the carbon concentration is lower than the SIMS analysis lower limit (1.0 × 10 ¹⁶ cm ⁻³ ) A 50 nm n-type In _x Ga _1-x As layer (x = 0.5) was grown so as to be in the range.

  In the method for manufacturing an epitaxial wafer for transistors according to the present embodiment, the HBT structure layer 4 is grown at a growth temperature of 400 ° C. or more and 600 ° C. or less by a vapor phase growth method (MOVPE method) at a constant growth temperature. I tried to do it.

  By growing the HBT structure layer 4 at a constant growth temperature, as shown in FIG. 2, the growth temperature (= substrate temperature) is changed after the HEMT structure layer 3 is grown and then the HBT structure layer 4 is grown. It is possible to shorten the time for changing the temperature and the time for stabilizing the temperature only once before starting. Therefore, it is possible to shorten the growth time in the entire transistor epitaxial wafer 1 (that is, the time required for manufacturing the transistor epitaxial wafer 1).

  On the other hand, as shown in FIG. 3, when the growth temperature (= substrate temperature) is changed for each epitaxial layer and the HBT structure layer 4 is grown, the temperature is changed every time the growth temperature is changed. Time and time for stabilizing the temperature are required, and the total growth time becomes longer.

  As shown in FIG. 2, the growth temperature of the HEMT structure layer 3 is 650 ° C., the growth temperature of the HBT structure layer 4 is 500 ° C. (invention), and the growth temperature of the HEMT structure layer 3 as shown in FIG. The sub-collector layer 13 is grown at 700 ° C., the collector layer 14 is grown at 650 ° C., the base layer 15 is grown at 500 ° C., the emitter layer 16 and the ballast layer 17 are grown at 600 ° C., and the non-alloy layer is grown at 450 ° C. The properties of the grown HBT were measured for both (prior art). The measurement results are shown in Table 1.

  As shown in Table 1, there is almost no difference in the characteristics such as current gain β between the present invention and the prior art, and it can be seen that the transistor epitaxial wafer 1 having good characteristics can be obtained even when the growth temperature is constant. .

  As described above, in the method for manufacturing an epitaxial wafer for a transistor according to the present embodiment, the HBT structure layer 4 is grown at a growth temperature of 400 ° C. or more and 600 ° C. or less by a vapor deposition method at a constant growth temperature. doing.

  Conventionally, since the growth temperature was changed for each epitaxial layer to grow the HBT structure layer, a time for changing the temperature and a time for stabilizing the temperature were required. By growing the structural layer 4 at a constant growth temperature, the time for changing the temperature and the time for stabilizing the temperature can be reduced, the total growth time can be shortened, and the throughput can be improved. It becomes.

In the present invention, the transistor epitaxial wafer 1 having a BI-FET structure is manufactured by growing the HBT structure layer 4 on the HEMT structure layer 3, so that the obtained transistor epitaxial wafer 1 is formed into an element. Thus, when used as a power amplifier for transmission and reception, a transistor element that operates at a low voltage, suppresses distortion of an output signal, reduces power consumption, and has high mobility can be realized. Specifically, in this embodiment, the base resistance is 180 Ω / sq and the current gain is 70 (1 kA / cm ² ), the mobility is 5000 cm ² / V · s, the sheet carrier concentration is 2.1 × 10 ¹² cm ^{−. 2.} A transistor element operating with a pinch-off voltage of −0.5 V could be obtained.

  The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

  For example, in the above embodiment, the semi-insulating GaAs substrate 2 is used as the substrate, but the present invention can also be applied to Si substrates and InP substrates.

  The present invention can also be applied to the case where a single HBT is manufactured by forming only the HBT structure layer 4 on the substrate.

1 Epitaxial wafer for transistor 2 GaAs substrate (substrate)
3 HEMT structure layer (high electron mobility transistor structure layer)
4 HBT structure layer (heterobipolar transistor structure layer)
5 Buffer layers 6, 10 Electron supply layers 7, 9 Spacer layer 8 Channel layer 11 Schottky layer 12 Etching stopper layer 13 Subcollector layer 14 Collector layer 15 Base layer 16 Emitter layer 17 Ballast layer 18 Non-alloy layer 19 Graded non-alloy layer 20 Uniform composition non-alloy layer

Claims (3)

Forming a high electron mobility transistor structure layer having an electron supply layer and a channel layer on a substrate;
Forming a heterobipolar transistor structure layer having a collector layer, a base layer, an emitter layer and a non-alloy layer on the high electron mobility transistor structure layer;
In a method of manufacturing an epitaxial wafer for a transistor having
A method for producing an epitaxial wafer for a transistor, wherein the heterobipolar transistor structure layer is grown at a constant growth temperature by a vapor deposition method at a growth temperature of 400 ° C. or higher and 600 ° C. or lower. The method for producing an epitaxial wafer for a transistor according to claim 1, wherein the electron supply layer comprises an n-type AlGaAs layer doped with Si. The method for manufacturing an epitaxial wafer for a transistor according to claim 1, wherein the dopant of the electron supply layer is selected from Si, Se, and Te.