JP2004228137A - Hetero junction bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hetero junction bipolar transistor with reduced offset voltage. <P>SOLUTION: In the hetero junction bipolar transistor, an InGaP layer 10 is provided between a collector layer 4 and a base layer 5, so that a hetero barrier is formed between the collector layer 4 and the base layer 5 to reduce the offset voltage. Further, an In mixed crystal ratio of the InGaP layer 10 inserted into the collector layer 4 ranges within 0.52 to 0.60, whereby lattice matching of the InGaP layer 10 with the InGaAs base layer 5 is ensured. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to heterojunction bipolar transistors.
[0002]
[Prior art]
A heterojunction bipolar transistor (hereinafter, referred to as “HBT”) using a III-V compound semiconductor includes an InGaP / GaAs-based HBT using InGaP, which is a wide band gap semiconductor, as an emitter, and GaAs as layers other than the emitter. It has been developed (for example, see Patent Document 1).
[0003]
In this InGaP / GaAs-based HBT, if InGaAs is used for the base layer and the collector layer of the HBT, InGaAs has high electron mobility, which is advantageous for high-speed operation. In addition, since InGaAs has a smaller energy gap than GaAs, the turn-on voltage can be reduced.
[0004]
Since InGaAs has a different lattice constant from GaAs, it is desirable that the In mixed crystal ratio be 0.2 or less for high-speed operation and low turn-on voltage. Further, a metamorphic HBT epitaxial wafer provided with a graded layer in which the mixed crystal ratio of each composition of In, Ga, and As is gradually changed from GaAs to InGaAs as shown in FIG.
[0005]
FIG. 2 is a structural view of an epitaxial wafer used for a conventional heterojunction bipolar transistor.
[0006]
The metamorphic HBT epitaxial wafer shown in FIG. 1 has an In composition gradient InGaAs buffer layer 2, an InGaAs subcollector layer 3, an InGaAs collector layer 4, an InGaAs base layer 5, an InGaP emitter layer 6, and an InGaAs emitter contact layer on a GaAs substrate 1. 7 and an InGaAs non-alloy layer 8 are sequentially formed (for example, refer to Japanese Patent Application No. 2002-72359).
[0007]
[Patent Document 1]
JP-A-2002-50630
[Problems to be solved by the invention]
The use of InGaAs for the base layer can reduce the turn-on voltage which is the ON voltage of the device, which is an advantage of the metamorphic HBT. On the other hand, the offset voltage of the HBT using the conventional metamorphic HBT epitaxial wafer is reduced. (Collector-emitter voltage when the collector current is zero) was high. Since the offset voltage is the lower limit voltage of the operation of the device, it is desirable that the offset voltage be lower.
[0009]
Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a heterojunction bipolar transistor having a reduced offset voltage.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the invention of claim 1 provides a laminated structure in which a buffer layer, a subcollector layer, a collector layer, a base layer, an emitter layer, an emitter contact layer, and a non-alloy contact layer are formed in order from the substrate side. The InGaP / InGaAs heterojunction bipolar transistor using the compound semiconductor provided has an InGaP layer or an AlGaAs layer between a collector layer and a base layer.
[0011]
According to a second aspect of the present invention, in addition to the configuration of the first aspect, the substrate is made of GaAs, the buffer layer, the subcollector layer, the collector layer, the base layer, and the emitter contact layer are made of InGaAs, and the emitter layer is made of the InGaP layer. It is preferable that the In mixed crystal ratio of the InGaAs layer is 0.2 or less.
[0012]
According to a third aspect of the present invention, in addition to the configuration of the first or second aspect, it is preferable that the In composition ratio of the InGaP layer inserted into the collector layer be in the range of 0.52 to 0.60.
[0013]
According to a fourth aspect of the present invention, in addition to the configuration according to any one of the first to third aspects, the buffer layer, the subcollector layer, the collector layer, the base layer, the emitter layer, the emitter contact layer, and the non-alloy contact layer are made of an organic metal. It is preferably formed by a phase growth method.
[0014]
According to the present invention, since the heterojunction bipolar transistor has the InGaP layer between the collector layer and the base layer, a hetero barrier is formed between the collector layer and the base layer, and the offset voltage is reduced. According to the present invention, the InGaP layer inserted into the collector layer has an In mixed crystal ratio in the range of 0.52 to 0.60, whereby lattice matching with the InGaAs base can be achieved.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0016]
FIG. 1 is a structural diagram showing an embodiment of an epitaxial wafer used for a heterojunction bipolar transistor of the present invention.
[0017]
The epitaxial wafer shown in FIG. 1 has an In composition gradient InGaAs buffer layer 2, an InGaAs subcollector layer 3, an InGaAs collector layer 4, an InGaP collector layer 10, an InGaAs base layer 5, an InGaAs emitter layer 6, and an InGaAs emitter layer on a GaAs substrate 1. The contact layer 7 and the InGaAs non-alloy layer 8 are sequentially formed.
[0018]
The HBT having such a structure reduces the offset voltage by providing the InGaP layer 10 on a part of the InGaAs collector layer 4 in a metamorphic HBT epitaxial wafer.
[0019]
In the HBT, when the discontinuous amounts of conduction band energy between the base layer 5 and the emitter layer 6 and between the base layer 5 and the collector layer 4 are ΔEc1 and ΔEc2, respectively, the difference between ΔEc1 and ΔEc2 is an offset voltage. Is the cause. Therefore, a part of the collector layer 4 near the interface with the base layer is formed as the InGaP collector layer 10, and the offset voltage can be reduced by providing a hetero barrier between the base layer 5 and the collector layer 4.
[0020]
In order to lattice match with the InGaAs base layer 5, the In mixed crystal ratio of the InGaP layer 10 inserted into the collector layer 4 is preferably in the range of 0.52 to 0.60.
[0021]
The offset voltage can be reduced by partially forming InGaP near the base interface of the collector layer of the HBT and providing a hetero barrier between the base layer and the collector layer.
[0022]
Comparing the offset voltages of the HBT having the structure shown in FIG. 2 and the HBT having the structure shown in FIG. 1, the offset voltage of the HBT having the conventional structure shown in FIG. 2 was between 115 mV and 120 mV. On the other hand, the offset voltage of the HBT of the structure of the present invention shown in FIG. 1 was as low as 95 mV to 100 mV.
[0023]
In this embodiment, the case where the wide band gap material inserted into the collector layer is InGaP has been described. However, the present invention is not limited to this, and AlGaAs capable of lattice matching with GaAs may be used. .
[0024]
【The invention's effect】
In short, according to the present invention, it is possible to provide a heterojunction bipolar transistor having a reduced offset voltage.
[Brief description of the drawings]
FIG. 1 is a structural diagram showing one embodiment of an epitaxial wafer used for a heterojunction bipolar transistor of the present invention.
FIG. 2 is a structural view of an epitaxial wafer used for a conventional heterojunction bipolar transistor.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 In composition gradient InGaAs buffer layer 3 InGaAs subcollector layer 4 InGaAs collector layer 5 InGaAs base layer 6 InGaP emitter layer 7 InGaAs emitter contact layer 8 InGaAs non-alloy layer 10 InGaP collector layer

Claims (4)

In the order from the substrate side, an InGaP / InGaAs-based heterojunction bipolar transistor made of a compound semiconductor having a laminated structure in which a buffer layer, a subcollector layer, a collector layer, a base layer, an emitter layer, an emitter contact layer, and a non-alloy contact layer are formed, A heterojunction bipolar transistor having an InGaP layer or an AlGaAs layer between the collector layer and the base layer. The substrate is made of GaAs, the buffer layer, the sub-collector layer, the collector layer, the base layer and the emitter contact layer are made of InGaAs, the emitter layer is made of InGaP layer, and the In alloy ratio of the InGaAs layer is made of InGaAs. The heterojunction bipolar transistor according to claim 1, wherein is 0.2 or less. 3. The heterojunction bipolar transistor according to claim 1, wherein the InGaP layer inserted into the collector layer has an In mixed crystal ratio of 0.52 to 0.60. 4. The method according to claim 1, wherein the buffer layer, the sub-collector layer, the collector layer, the base layer, the emitter layer, the emitter contact layer, and the non-alloy contact layer are formed by metal organic chemical vapor deposition. A heterojunction bipolar transistor as described in claim 1.

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