JP2002359249A - Compound semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely prevent electron blocking effect in a double heterojunction bipolar transistor. SOLUTION: A method for manufacturing a compound semiconductor device comprises a step of forming a delta-doped layer 112, having impurity concentration higher than that of a collector layer 103 on a region of about 10 nm or smaller, from a heterojunction interface to a set-back layer 104 of a collector layer 103, having a band gap larger than that of a base layer 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a compound semiconductor device, and more particularly to a heterojunction bipolar transistor operating at high speed.

[0002]

2. Description of the Related Art In a heterojunction bipolar transistor (hereinafter, referred to as an HBT), a semiconductor material having a band gap larger than that of a base layer is used for an emitter layer. By using the junction, the emitter injection efficiency (the ratio of the injection current into the base layer to the total emitter current) is increased. As a result, the base layer can be made thinner by increasing the impurity concentration of the base layer, so that the HBT becomes a device capable of high-speed operation.

An HBT using a heterojunction not only for the junction between the emitter layer and the base layer but also for the junction between the base layer and the collector layer is called a double heterojunction bipolar transistor (hereinafter referred to as DHBT). ing. D
In the HBT, since the collector breakdown voltage can be increased and the collector-emitter offset voltage can be reduced as compared with the HBT in which the junction between the base layer and the collector layer is a homojunction, there is an advantage that the operating characteristics under a low voltage can be improved. There is.

However, in the DHBT, since a semiconductor material having a band gap larger than that of the base layer is used for the collector layer, an energy barrier is formed in a conduction band at a heterojunction interface between the collector layer and the base layer. . This energy barrier hinders electron transfer,
In the DHBT, an electron blocking effect occurs in that the current gain decreases and the transistor characteristics deteriorate. On the other hand, as one of the conventional techniques for suppressing the electron blocking effect, a technique of lowering the height of an energy barrier generated at a heterojunction interface by interposing a setback layer between a base layer and a collector layer. It has been known.

In this specification, the term "heterojunction interface" means an interface between a semiconductor layer having a relatively narrow gap and a semiconductor layer having a relatively wide gap. In a DHBT that is not formed, the junction interface between the base layer and the collector layer becomes a hetero junction interface. For example, in a DHBT provided with a setback layer made of the same material as the base layer, for example, the junction interface between the setback layer and the collector layer Becomes a heterojunction interface.

FIG. 3 is a cross-sectional view of a conventional compound semiconductor device, specifically, a DHBT having a setback layer.

As shown in FIG. 3, a buffer layer 11 composed of a GaAs layer, a subcollector layer 12 composed of an n-type GaAs layer, and an n-type InGaP layer are formed on a semiconductor substrate 10 composed of a semi-insulating GaAs substrate. Collector layer 1 consisting of
3. Setback layer 1 made of undoped GaAs layer
4. a base layer 15 made of a p-type GaAs layer;
An emitter layer 16 composed of an nGaP layer, a contact layer 17 composed of an n-type GaAs layer, and an emitter cap layer 18 composed of an n-type InGaAs layer are sequentially laminated. Here, the material of the setback layer 14 is the collector layer 1
GaAs having a smaller band gap than the material No. 3 (InGaP), that is, the same material as the base layer 15 is used. The collector layer 13 in the sub-collector layer 12
The collector electrode 19 is formed on a region where no is formed, the base electrode 20 is formed on a region of the base layer 15 where the emitter layer 16 is not formed, and the collector electrode 19 is formed on the emitter cap layer 18. Emitter electrode 21
Are formed.

FIG. 4 is an energy band diagram of the DHBT shown in FIG.

As shown in FIG. 4, the respective band gaps of the emitter layer 16 and the collector layer 13 are different from those of the base layer 1.
5 is larger than the band gap. The setback layer 1 is provided between the base layer 15 and the collector layer 13.
4, the height of the energy barrier generated at the heterojunction interface is reduced, so that electrons can easily move from the base layer 15 to the collector layer 13.

[0010]

However, in the DHBT shown in FIG. 3, that is, in the conventional compound semiconductor device, the height of the energy barrier viewed from the electrons can be reduced to some extent by the setback layer 14,
There is a problem that the electron blocking effect cannot be completely prevented.

In view of the above, an object of the present invention is to make it possible to reliably prevent an electron blocking effect in a double heterojunction bipolar transistor.

[0012]

In order to achieve the above object, a first compound semiconductor device according to the present invention comprises an emitter layer, a base layer in contact with the emitter layer and made of the first compound semiconductor, and Assume that the compound semiconductor device includes a collector layer made of a second compound semiconductor that is in contact with the base layer and has a larger band gap than the first compound semiconductor, and is within about 10 nm from a heterojunction interface between the collector layer and the base layer. , A delta-doped layer having an impurity concentration higher than that of the collector layer is formed.

According to the first compound semiconductor device, since the delta-doped layer is provided near the heterojunction interface with the base layer in the collector layer, the thickness of the energy barrier generated at the heterojunction interface is reduced and the energy barrier is reduced. Electrons easily pass through the barrier. For this reason, the movement of the electrons injected from the base layer into the collector layer can be suppressed from being hindered by the energy barrier, so that the electron blocking effect can be reliably prevented. Accordingly, the current gain is improved and the transistor characteristics are improved, so that, for example, a highly efficient double heterojunction bipolar transistor suitable for high-speed operation can be realized.

In order to achieve the above object, a second compound semiconductor device according to the present invention comprises an emitter layer, a base layer in contact with the emitter layer and made of the first compound semiconductor,
Assume that the compound semiconductor device includes a collector layer made of a second compound semiconductor that is in contact with the base layer and has a band gap larger than that of the first compound semiconductor. The collector layer is formed at a heterojunction interface between the collector layer and the base layer. A delta-doped layer having a higher impurity concentration than the delta-doped layer is formed.

According to the second compound semiconductor device, since the delta-doped layer is provided at the heterojunction interface between the collector layer and the base layer, the height of the energy barrier generated at the heterojunction interface is reduced to reduce the energy barrier. Pass easily. For this reason, the movement of the electrons injected from the base layer into the collector layer can be prevented from being hindered by the energy barrier, so that the electron blocking effect can be reliably prevented. Accordingly, the current gain is improved and the transistor characteristics are improved, so that, for example, a highly efficient double heterojunction bipolar transistor suitable for high-speed operation can be realized.

According to a third compound semiconductor device of the present invention,
A compound comprising: an emitter layer; a base layer in contact with the emitter layer and made of a first compound semiconductor; and a collector layer in contact with the base layer and made of a second compound semiconductor having a larger band gap than the first compound semiconductor. Assuming a semiconductor device, the semiconductor device further comprises a setback layer made of a third compound semiconductor having a band gap smaller than that of the second compound semiconductor and provided between the collector layer and the base layer; A delta-doped layer having an impurity concentration higher than that of the collector layer is formed in a region within about 10 nm from the heterojunction interface with the layer.

According to the third compound semiconductor device, the setback layer is provided between the collector layer and the base layer, and the delta doped layer is provided near the heterojunction interface between the collector layer and the setback layer. Therefore, the height of the energy barrier generated at the heterojunction interface is reduced, and the thickness is reduced, so that electrons can easily pass through the energy barrier. For this reason, the movement of the electrons injected from the base layer into the collector layer can be prevented from being hindered by the energy barrier, so that the electron blocking effect can be reliably prevented. Accordingly, the current gain is improved and the transistor characteristics are improved, so that, for example, a highly efficient double heterojunction bipolar transistor suitable for high-speed operation can be realized.

According to a fourth compound semiconductor device of the present invention,
A compound comprising: an emitter layer; a base layer in contact with the emitter layer and made of a first compound semiconductor; and a collector layer in contact with the base layer and made of a second compound semiconductor having a larger band gap than the first compound semiconductor. Assuming a semiconductor device, the semiconductor device further includes a setback layer made of a third compound semiconductor, which is provided between the collector layer and the base layer and has a band gap smaller than that of the second compound semiconductor. A delta-doped layer having a higher impurity concentration than the collector layer is formed at a heterojunction interface with the layer.

According to the fourth compound semiconductor device, the setback layer is provided between the collector layer and the base layer, and the delta-doped layer is provided at the heterojunction interface between the collector layer and the setback layer. As compared with the case where only the set-back layer is provided, the height of the energy barrier generated at the heterojunction interface is further reduced, and electrons easily pass through the energy barrier. For this reason, the movement of the electrons injected from the base layer into the collector layer can be prevented from being hindered by the energy barrier, so that the electron blocking effect can be reliably prevented. Accordingly, the current gain is improved and the transistor characteristics are improved, so that, for example, a highly efficient double heterojunction bipolar transistor suitable for high-speed operation can be realized.

In the first to fourth compound semiconductor devices,
The collector layer preferably includes a semiconductor layer made of InGaP, InP, or GaAs.

In this manner, a double heterojunction bipolar transistor can be reliably realized.

The method for manufacturing a compound semiconductor device according to the present invention is based on any one of the first to fourth compound semiconductor devices according to the present invention, and is used for epitaxially growing a semiconductor layer serving as a collector layer. Forming a delta-doped layer by interrupting the epitaxial growth and introducing at least one atomic layer of impurities into the semiconductor layer.

According to the method of manufacturing the compound semiconductor device of the present invention, the distance between the base layer and the collector layer is reduced as compared with the case where the electron blocking effect is prevented by continuously changing the impurity concentration of the collector layer. The capacity can be reduced. In addition, since the amount of impurities added to the collector layer as a delta-doped layer can be accurately controlled with good reproducibility without depending on epitaxial growth conditions, stable transistor characteristics can be obtained.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a compound semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a compound semiconductor device according to this embodiment, specifically, a DHBT type compound semiconductor device.

As shown in FIG. 1, for example, semi-insulating Ga
On a semiconductor substrate 100 made of an As substrate, for example, a buffer layer 101 made of a GaAs layer having a thickness of 250 nm, for example, an n-type buffer layer having a thickness of 250 nm (impurity concentration = 2 × 10 ¹⁸ c
m ⁻³ ) GaAs layer, for example, a 400 nm-thick n-type (impurity concentration = 1 × 10 ¹⁷ c)
m ⁻³ ) InGaP collector layer 103, for example, a 20 nm thick undoped GaAs layer setback layer 104, for example, 850 nm thick p-type (impurity concentration = 1.2 × 10 ¹⁹ cm ⁻³ ) Base layer 105 made of a GaAs layer having a thickness of, for example, 250 nm and an n-type (impurity concentration = 1 × 10 ¹⁷ cm ⁻³ ) emitter layer 106 made of an InGaP layer, for example, an n-type emitter layer having a thickness of 250 nm (impurity concentration = 2 × A contact layer 107 made of a GaAs layer of 10 ¹⁸ cm ^-3 , for example, an n-type (impurity concentration = 2
The emitter cap layer 108 of an InGaAs layer of (× 10 ¹⁸ cm ⁻³ ) is sequentially laminated. Here, as the material of the setback layer 104, GaAs having a smaller band gap than the material of the collector layer 103 (InGaP)
s, that is, the same material as that of the base layer 105 is used.
The collector layer 103 in the sub-collector layer 102
The collector electrode 109 is formed on the region where no is formed, and the emitter layer 10 in the base layer 105 is formed.
A base electrode 110 is formed on a region where no 6 is formed, and an emitter electrode 111 is formed on an emitter cap layer 108.

This embodiment is characterized in that the collector layer 103 is located at 5
An extremely thin delta-doped layer 112 having an impurity concentration (n-type) higher than that of the collector layer 103 is provided in a region at a distance of about nm. Here, the delta doped layer 11
2 can be formed, for example, by interrupting the epitaxial growth when the InGaP layer serving as the collector layer 103 is epitaxially grown and introducing an impurity of about one atomic layer, for example, Si into the InGaP layer.
More specifically, the InGaP layer serving as the collector layer 103 is formed by MOCVD (metal organic chemical vapor deposit).
ion), TMI (trimethylindium) and TMG (trimethylgallium) as group III element supply gas and PH ₃ as group V element supply gas.
(Phosphine) is introduced onto the heated substrate. At this time, during the epitaxial growth of the InGaP layer, II
The introduction of the group I element supply gas is stopped, and the group V element supply gas and Si ₂ H ₆ (disilane) as the impurity element supply gas are stopped.
Is introduced on the substrate, so that only Si is deposited on the substrate. After that, by introducing the group III element supply gas again, the epitaxial growth of the InGaP layer is restarted. Since about one atomic layer of Si atoms introduced into the InGaP layer diffuses in the subsequent steps, the thickness of the delta-doped layer 112 is
It becomes thicker than the atomic layer.

FIG. 2 is an energy band diagram of the DHBT shown in FIG.

As shown in FIG. 2, the band gap of each of the emitter layer 106 and the collector layer 103 is larger than the band gap of the base layer 105. Further, since the energy of the conduction band in the collector layer 103 is reduced by the delta-doped layer 112, the thickness of the energy barrier generated at the heterojunction interface between the setback layer 104 and the collector layer 103 is reduced. It is easy to move toward the collector layer 103. Further, the base layer 105 and the collector layer 10
As a result, the height of the energy barrier generated at the heterojunction interface is reduced, so that electrons can move more easily from the base layer 105 to the collector layer 103. .

As described above, according to this embodiment, since the delta-doped layer 112 is provided near the heterojunction interface with the base layer 105 in the collector layer 103, the thickness of the energy barrier generated at the heterojunction interface is increased. Becomes thinner. Therefore, when electrons are injected from the emitter layer 106 to the collector layer 103 via the base layer 105, the electrons can easily pass through the energy barrier at the heterojunction interface, so that the electron blocking effect can be reliably prevented. Therefore, the current gain is improved and the transistor characteristics are improved, so that a highly efficient DHBT suitable for high-speed operation can be realized.

Further, according to the present embodiment, the base layer 10
Since the setback layer 104 is provided between the layer 5 and the collector layer 103, the electron blocking effect can be more reliably prevented.

Further, according to the present embodiment, in order to prevent the electron blocking effect by using the delta-doped layer 112, for example, the case where the electron blocking effect is to be prevented by changing the impurity concentration of the collector layer 103 continuously. In comparison, the base layer 105 and the collector layer 1
03 can be reduced. The collector layer 10
Since the epitaxial growth is interrupted during the epitaxial growth of No. 3 and the delta-doped layer 112 is formed by introducing about one atomic layer of impurities into the collector layer 103, the amount of impurities added to the collector layer 103 depends on the epitaxial growth conditions. Since it can be controlled with good reproducibility and precision without performing, stable transistor characteristics can be obtained.

In this embodiment, the method of forming the delta doped layer 112 and the region where the delta doped layer 112 is formed in the collector layer 103 are different from those of the delta doped layer 112.
There is no particular limitation as long as the thickness of the energy barrier at the heterojunction interface can be reduced. However, in the formation region of the delta doped layer 112, the collector layer 103
Alternatively, although there is a slight difference depending on a semiconductor material used for the setback layer 104 or an impurity concentration of the collector layer 103, the collector layer 103 may be a region within about 10 nm from a heterojunction interface with the setback layer 104. preferable. By doing so, the thickness of the energy barrier at the heterojunction interface can be made thin enough to allow tunneling of electrons. At this time, the number of delta-doped layers 112 is not particularly limited. When the delta-doped layer is provided in the collector layer 103 in a region of about 20 nm or more from the heterojunction interface with the setback layer 104, the distance from the heterojunction interface to the delta-doped layer becomes larger than the wavelength of the electron wave. For,
The effect of facilitating electron tunneling by reducing the thickness of the energy barrier at the heterojunction interface is hardly obtained.

In this embodiment, the delta-doped layer 112 is provided near the heterojunction interface between the collector layer 103 and the set-back layer 104. Instead, the delta-doped layer 112 is set back with the collector layer 103. It may be provided at the heterojunction interface itself with the layer 104. In this case, the height of the energy barrier generated at the heterojunction interface is further reduced as compared with the case where only the setback layer 104 is provided, so that electrons can easily pass through the energy barrier.

In the present embodiment, the base layer 10
Although the setback layer 104 is provided between the base layer 105 and the collector layer 103, the base layer 105 and the collector layer 103 may be directly hetero-juncted without providing the setback layer 104. In this case, the region where the delta doped layer 112 is formed is a region within about 10 nm from the heterojunction interface between the collector layer 103 and the base layer 105 or the heterojunction interface between the collector layer 103 and the base layer 105 itself. Is preferred.

In the present embodiment, the same GaAs as the material of the base layer 105 is used as the material of the setback layer 104, but the material of the setback layer 104 is
The material is not particularly limited as long as the material has a smaller band gap than the material of the collector layer 103. The conductivity type of the setback layer 104 may be undoped or n-type.

In the present embodiment, the collector layer 1
03 and GaAs as the material of the base layer 105 while using InGaP as the material of the emitter layer 106. In other words, InGaP is used as the structure of the DHBT.
Although the / GaAs / InGaP structure was used, the structure of the DHBT is not particularly limited as long as the band gaps of the collector layer and the emitter layer are larger than the band gaps of the base layer. For example, InP / InGaAs / In
A P structure or the like may be used.

In this embodiment, the collector layer 1
Although a single layer structure of an InGaP layer was used as 03, a single layer structure such as an InP layer or a GaAs layer, or a stacked structure of at least two layers of an InGaP layer, an InP layer, and a GaAs layer, etc. May be used. For example, when a GaAs layer is formed as the collector layer 103 by MOCVD, TMG may be used as a group III element supply gas and AsH ₃ (arsine) may be used as a group V element supply gas. In addition, for example, InP
When the layer is formed by the MOCVD method, TMI is used as a group III element supply gas, and PH _{3 is used} as a group V element supply gas.
May be used.

[0039]

According to the present invention, the energy barrier generated at the heterojunction interface between the collector layer and the base layer or the setback layer can be reduced by using the delta-doped layer. It is possible to suppress the transfer of electrons to be inhibited by the energy barrier. For this reason, the electron blocking effect can be reliably prevented, whereby the current gain is improved and the transistor characteristics are improved. For example, a highly efficient double heterojunction bipolar transistor suitable for high-speed operation can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a compound semiconductor device according to an embodiment of the present invention.

FIG. 2 is an energy band diagram of the compound semiconductor device according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional compound semiconductor device.

FIG. 4 is an energy band diagram of a conventional compound semiconductor device.

[Explanation of symbols]

 Reference Signs List 100 semiconductor substrate 101 buffer layer 102 sub-collector layer 103 collector layer 104 set-back layer 105 base layer 106 emitter layer 107 contact layer 108 emitter cap layer 109 collector electrode 110 base electrode 111 emitter electrode 112 delta-doped layer

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takeshi Tanaka 1006 Kadoma, Kadoma, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. 5F003 AP05 BA01 BA92 BB04 BC01 BC02 BC04 BE04 BE90 BF06 BG03 BG06 BM03 BP21 BP32

Claims (6)

[Claims] 1. An emitter layer, a base layer in contact with the emitter layer and made of a first compound semiconductor, and a second compound semiconductor in contact with the base layer and having a larger band gap than the first compound semiconductor. A delta-doped layer having an impurity concentration higher than that of the collector layer in a region within about 10 nm from a heterojunction interface with the base layer in the collector layer. A compound semiconductor device characterized by the above-mentioned. 2. An emitter layer, a base layer in contact with the emitter layer and made of a first compound semiconductor, and a second compound semiconductor in contact with the base layer and having a band gap larger than that of the first compound semiconductor. A compound semiconductor device comprising: a collector layer; and a heterojunction interface between the collector layer and the base layer,
A compound semiconductor device, wherein a delta-doped layer having a higher impurity concentration than the collector layer is formed. 3. An emitter layer, a base layer in contact with the emitter layer and made of a first compound semiconductor, and a second compound semiconductor in contact with the base layer and having a larger band gap than the first compound semiconductor. And a collector layer provided between the collector layer and the base layer and having a band gap smaller than that of the second compound semiconductor. A compound semiconductor, further comprising a back layer, wherein a delta-doped layer having a higher impurity concentration than the collector layer is formed in a region of the collector layer within about 10 nm from a heterojunction interface with the set back layer. apparatus. 4. An emitter layer, a base layer in contact with the emitter layer and made of a first compound semiconductor, and a second compound semiconductor in contact with the base layer and having a larger band gap than the first compound semiconductor. And a collector layer provided between the collector layer and the base layer and having a band gap smaller than that of the second compound semiconductor. A compound semiconductor device further comprising a back layer, wherein a delta-doped layer having a higher impurity concentration than the collector layer is formed at a heterojunction interface between the collector layer and the set back layer. 5. The collector layer is made of InGaP, InP.
The compound semiconductor device according to any one of claims 1 to 4, further comprising a semiconductor layer made of GaAs. 6. The method of manufacturing a compound semiconductor device according to claim 1, wherein the epitaxial growth is interrupted when the semiconductor layer serving as the collector layer is epitaxially grown. Forming a delta-doped layer by introducing at least one atomic layer of impurities into the compound semiconductor device.