JP2000323491A - Heterojunction bipolar transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device structure of a heterojunction bipolar transistor and a manufacturing method thereof which is capable of operating with high reliability and high device characteristics. SOLUTION: As for the heterojunction bipolar transistor having a III-V compd. semiconductor-made n-type collector layer 12, a p-type base layer 13, and an n-type emitter layer 14 having a wider in bit band than that of the base layer 13 on a semiconductor substrate 10, the base layer 13 is doped with impurities composed of atoms other than those in groups III or V, one impurity having a larger atomic radius and the other having a atomic radius smaller than that of atoms constituting the base layer 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a heterojunction bipolar transistor and a method of manufacturing the same, and more particularly to a heterojunction bipolar transistor for high reliability operation and a method of manufacturing the same.

[0002]

2. Description of the Related Art Heterojunction bipolar transistors (hereinafter referred to as HBTs) using III-V compound semiconductors have excellent high-frequency characteristics and high current driving capability, and have been used for high-frequency devices and mobile communication devices and optical communication systems. Promising applications for output devices are already in practical use. For practical use, improvement of reliability is important, and research on reliability has been actively conducted in HBTs.

[0003] Deterioration of reliability in the HBT is manifested by a phenomenon that a current amplification factor is reduced during a high-temperature energization test, and an increase in a base current is often observed. As a cause of this, the diffusion of the p-type dopant in the base layer, an increase in recombination current on the base surface, and the formation of defects in the base layer, etc.
Conceivable. In recent years, therefore, hetero-guard rings have been used to convert the base dopant from beryllium Be, which is easily diffused, to carbon C, which has a small diffusion coefficient, or to extend the emitter end to the base surface in a shelf shape to reduce the exposure of the base surface. Is generally provided.

[0004] Although the reliability of the HBT has been considerably improved by such measures, when a large current such as that used in a power device is applied, the element is also deteriorated.

The main cause of this is not the diffusion of impurities, but as described in the following literature, since the base layer is heavily doped with impurities, strains are introduced into the base layer due to differences in atomic radii. Defects, such as dislocations,
It is thought to be the recombination center (eye, di, e, M 1995 technical digest, p. 811;
T. Henderson: IEDM 1995, Technical Digest p81
1; T. Henderson).

For example, in a GaAs base layer, Be or C is used as a p-type dopant, but these have a smaller atomic radius than Ga or As, and accordingly have a smaller lattice. In order to alleviate this distortion, JP-A-05-299432 or JP-A-06-037105
A method of adding a group III-V element having an atomic radius larger than that of Ga or As to a base layer has been attempted.

FIG. 6 schematically shows the structure of a heterojunction bipolar transistor formed by the above-described conventional method. On a semi-insulating GaAs substrate 50, a buffer layer 51, a sub-collector layer (n-GaAs) 56, and a collector layer (n
-GaAs) 52, base layer (p-GaAs) 53, emitter layer (n-AlG
aAs or n-InGaP) 54, emitter cap layer (n ⁺ -GaA)
s) 55 are sequentially formed, and the emitter cap layer (n ⁺ -GaAs)
On top of the emitter electrode (WSi) 62 is a collector layer (n-
GaAs) 52, a collector electrode (Ni / AuGe / Au alloy) 60
However, on the base layer (p-GaAs) 53, a base electrode (Ti / Pt /
Au) 61 are formed respectively.

Here, the base layer (p-GaAs) 53 contains Ga or
In and Sb having an atomic radius larger than that of As are added, thereby relaxing strain.

[0009]

SUMMARY OF THE INVENTION In the aforementioned base layer,
The method of adding In or Sb, whose atomic radius is larger than that of Ga or As,
Although effective in terms of lattice relaxation, In and Sb are III-V
When it is added to GaAs because it is an atom constituting a group III compound semiconductor, InAs or GaSb is partially formed.

[0010] These compounds have a smaller forbidden band width than GaAs, and the band structure of GaAs itself changes. Therefore, ON
A problem arises in that the voltage changes, the band gap with the collector side increases, and the electron traveling characteristics deteriorate.

An object of the present invention is to provide a heterojunction bipolar transistor which maintains high reliability and does not deteriorate device characteristics in view of the above problems.

[0012]

According to the present invention, there is provided an n-type collector layer comprising a III-V compound semiconductor film, a p-type base layer, and an n-type having a larger forbidden band width than the p-type base layer. In the heterojunction bipolar transistor having the emitter layer, the p-type dopant of the p-type base layer is an impurity composed of an atom that does not correspond to any of Group III or V, and constitutes the p-type base layer. The present invention relates to a heterojunction bipolar transistor characterized in that an impurity having a larger atomic radius and an impurity having a smaller atomic radius are doped than atoms.

In the heterojunction bipolar transistor, a subcollector layer doped with an n-type impurity at a concentration of 1 × 10 ¹⁸ cm ⁻³ or more is formed between the n-type collector layer and the semiconductor substrate. Preferably, a collector electrode is formed on the sub-collector layer.

Further, in the hetero-junction bipolar transistor, a compound semiconductor having a smaller forbidden band width than the emitter layer and doped with n-type impurities of 1 × 10 ¹⁸ cm ^-3 or more is formed on the n-type emitter layer. Preferably, an emitter cap layer is provided, and an emitter electrode is formed on the emitter cap layer.

Further, according to the present invention, there is provided a semiconductor device comprising a III-V
What is claimed is: 1. A method for manufacturing a heterojunction bipolar transistor, comprising a step of sequentially epitaxially growing an n-type collector layer, a p-type base layer, and an n-type emitter layer having a larger bandgap than the p-type base layer using a group III compound semiconductor, The present invention relates to a method for manufacturing a heterojunction bipolar transistor, characterized in that in the step of growing the p-type base layer, an impurity having a larger atomic radius and an impurity having a smaller atomic radius than the atoms constituting the p-type base layer are doped.

According to the present invention, taking a GaAs base layer as an example, the difference in lattice constant is offset by adding a combination of impurities having a larger atomic radius and smaller impurities than Ga or As as a p-type dopant. , Can reduce distortion. Therefore, crystal defects due to strain do not occur, and high-reliability operation becomes possible.

Moreover, since these impurities do not constitute the III-V group compound semiconductor, they do not significantly affect the band structure of GaAs. In addition, since both impurities act as p-type dopants, the device characteristics do not deteriorate.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the above objects, features and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The present invention is not limited to the following embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

FIG. 1 is a sectional view showing the configuration of one embodiment of the heterojunction bipolar transistor of the present invention.

In FIG. 1, on a semi-insulating GaAs substrate 10,
Buffer layer 11 (100 nm) made of i-GaAs or i-AlGaAs
Is formed, and 5 × 10 ¹⁷ c
An m- ³ doped n-GaAs collector layer 12 (1000 nm) is formed. C (atomic radius: 0.77Å) 2 on the collector layer 12
A p-GaAs base layer 13 (80 nm) doped with × 10 ¹⁹ cm ⁻³ and Mg (atomic radius: 1.40 °) 2 × 10 ¹⁹ cm ⁻³ is formed.
The atomic radii of Ga and As are 1.26 ° and 1.18 °, respectively, and Mg is doped into the base layer 13 as an impurity having a larger atomic radius than the atoms constituting the base layer 13, and C is doped as an impurity having a smaller atomic radius. ing.

Here, the doping ratio of the impurity having a large atomic radius to the impurity having a small atomic radius is, in the above example, an impurity having a large atomic radius: an impurity having a small atomic radius = 1: 1. Can be determined as appropriate. In the normal case, impurities having a large atomic radius: impurities having a small atomic radius = 30: 70 to 70:30
Is appropriate.

It is also possible to combine a plurality of impurities having a large atomic radius with a large impurity and a plurality of impurities having a small atomic radius.

The base layer on 13, Si of 3 × 10 ¹⁷ cm ^-3 doped n-AlGaAs or n-InGaP emitter layer 14 (100n
m) is formed. On the emitter layer 14, n ⁺ − doped with Si at a high concentration (1 × 10 ¹⁸ cm ⁻³ or more) has a smaller forbidden band width than the emitter layer 14 in order to form an emitter electrode.
A GaAs emitter cap layer 15 (100 nm) is formed. S
The concentration of i is preferably 1 × 10 ¹⁸ cm ⁻³ or more.

Furthermore, a collector electrode 20 made of a Ni / AuGe / Au alloy on the collector layer 12, a base electrode 21 made of a Ti / Pt / Au alloy on the base layer 13, and an emitter electrode 22 made of WSi on the emitter cap layer 15. Are formed respectively.

The heterojunction bipolar transistor shown in FIG. 1 was prepared by changing the collector voltage to 3 V and the collector current density to 2 × 10 ⁴ A /
When a reliability test was performed under the conditions of cm ² and a junction temperature of 200 ° C., the device characteristics did not change for a continuous 1000 hours. In addition, the base resistance shows a low value of 50Ω, and the highest oscillation frequency (fmax) is 200GHz as a high frequency characteristic.
The above is shown.

As described above, by doping the base layer with an impurity having a larger atomic radius and an impurity having a smaller atomic radius than the atoms constituting the layer, the strain due to the difference in the lattice constant is alleviated. High reliability was obtained. Also, the doped impurities are III-V
Since it is not an element constituting a group III compound semiconductor, doping does not change the ON voltage or deteriorate the traveling characteristics of electrons.

In addition to the layer structure of the hetero-junction bipolar transistor shown in FIG. 1, a sub-collector layer heavily doped with n-type impurities can be provided between the semiconductor substrate and the collector layer.

FIG. 2 is a sectional view showing the structure of a heterojunction bipolar transistor provided with a subcollector layer. This figure is exactly the same as FIG. 1 except that an n-GaAs subcollector layer 16 doped with 1 × 10 ¹⁸ cm ⁻³ or more of Si is provided under the collector layer, and a collector electrode 20 is provided on the subcollector layer 16. It has a layer structure of, but by adopting such a structure,
The collector resistance can be reduced, and the device characteristics can be further improved.

It is also possible to further reduce the emitter resistance of the heterojunction bipolar transistor of FIG. The structure shown in FIG. 3 is used for such a purpose.
1 × Si as well as n ⁺ -GaAs as emitter cap layer
An n ⁺ -InGaAs layer 17 doped with 10 ¹⁸ cm ⁻³ or more is provided. The other layer configuration is exactly the same as the structure of FIG. InGaAs has a narrower bandgap than GaAs and can be doped at a high concentration. By adopting such a layer structure, the emitter resistance can be further reduced and the device characteristics can be improved. Also, a non-alloy ohmic with the emitter electrode can be taken.

In the above embodiment, GaAs, InGa
As, AlGaAs, InGaP film thickness, doping concentration, composition,
It is arbitrary as long as it is suitable for the purpose of the present structure.

Although a combination of Si and C and Mg is used as the n-type impurity, for example, Se and Sn can be used as the n-type impurity, and C and Zn can be used as the p-type impurities. There is also a combination of Be and Mg, and any one that meets the gist of the present invention can be used.

Further, not only GaAs but also Si may be used as the substrate.

Also, any alloy used for the electrode can be used as long as it is suitable for the purpose.

Next, a method for manufacturing a heterojunction bipolar transistor of the present invention will be described in detail with reference to examples.

A method of manufacturing a heterojunction bipolar transistor according to the present invention will be described with reference to FIGS. In the figure, a buffer layer 11 (100 nm) made of i-GaAs and a Si layer of 5 × 10 ¹⁷ cm ^{−3 are} formed on a semi-insulating GaAs substrate 10 at a substrate temperature of 600 ° C. using molecular beam epitaxy (MBE). A doped n-GaAs collector layer 12 (1000 nm) is grown.

Subsequently, Be: 2 × 10 ¹⁹ cm ⁻³ and Mg: 2 × 10 ¹⁹ cm
P-GaAs base layer 13 (80 nm) while simultaneously doping ^-3
Grow. Further, n doped with 3 × 10 ¹⁷ cm ^{−3 of} Si
-AlGaAs emitter layer 14 (100 nm), n ⁺ -GaAs emitter cap layer 15 (100 nm) doped with 5 × 10 ¹⁸ cm ⁻³ or more of Si,
Growth is performed in this order (FIG. 4A).

Next, an emitter electrode 22 made of WSi is formed by sputtering, masked with a photoresist (PR) 23, and processed by dry etching. Further, the n ⁺ -GaAs emitter cap layer 15 and the n-AlGaAs emitter layer 14 are etched using wet etching. At this time, the emitter layer is
(Fig. 4 (b)).

Next, mask with a photoresist (PR) 24,
Unnecessary base layer is wet-etched to form collector layer 12
Is exposed (FIG. 4 (c)).

Next, only the base electrode is opened, and the emitter layer 14 in this opening is removed by etching.
Expose 13. The exposed portion of the base layer 13 is coated with Ti
A base electrode 21 made of a / Pt / Au alloy is formed by lift-off (FIG. 5 (d)).

Finally, a PR mask is applied, a collector electrode portion is opened, and a collector electrode 20 made of a Ni / AuGe / Au alloy is formed by lift-off to complete the device (FIG. 5).
(e)).

It is to be noted that 1 × 10 ¹⁸ cm ⁻³ of Si is formed under the collector layer 12.
The sub-collector layer doped above is grown, and 1 × 10 ¹⁸ Si is formed on the n ⁺ -GaAs layer 15 as an emitter cap layer.
When the n ⁺ -InGaAs layer 17 doped with cm ⁻³ or more is grown, the contact resistance is reduced, and the device characteristics can be further improved.

In the present manufacturing method, if the growth conditions, the composition of each layer, the film thickness, the doping concentration, the type of n-type impurities, the combination of p-type impurities, and the alloys used for the electrodes are suitable for the purpose. Everything is optional.

In the process, dry etching may be used instead of wet etching. Especially when etching the emitter cap layer, AlGaAs / GaA
The use of s selective etching facilitates emitter mesa formation.

Another method of manufacturing the heterojunction bipolar transistor of the present invention will be described with reference to FIG.
Regarding the method of manufacturing the heterojunction bipolar transistor of the present invention, as a growth method, metal organic chemical vapor deposition (MOV)
The method is the same as the method shown in FIG.

On a semi-insulating GaAs substrate 10, first, trimethylgallium (TMG) and arsine (AsH ₃ ) were used to form a substrate at a temperature of 600 ° C.
The buffer layer 31 (100 nm) made of i-GaAs, Si is 5 × 10 ¹⁷
A cm ^{- 3} doped n-GaAs collector layer 32 (1000 nm) is grown. Silane (SiH ₄ ) is used as the Si dopant gas.

Subsequently, C: 2 × 10 ¹⁹ cm ^-3 and Zn: 2 × 10
While simultaneously doping the ¹⁹ cm ^-3 p-GaAs base layer 33 (8
0 nm). C and Zn dopant gases are CBr ₄ and Z
It is nH _2.

Further, nI doped with 3 × 10 ¹⁷ cm ^{−3 of} Si
nGaP emitter layer 34 (100 nm) is
Growth using I), TMG, phosphine (PH ₃ ).

Next, an n ⁺ -GaAs emitter cap layer 35 (100 nm) doped with Si at 5 × 10 ¹⁸ cm ⁻³ or more is grown.

In the steps after the step of forming the emitter cap layer, a collector electrode 40, a base electrode 41, and an emitter electrode 43 were formed in the same manner as in Example 1 to fabricate a heterojunction bipolar transistor.

[0051]

As described above, according to the present invention,
In the heterojunction bipolar transistor, the difference in lattice constant was canceled out by doping in combination with an impurity having a larger atomic radius and an impurity having a smaller atomic radius than the atoms constituting the base layer, and the strain could be reduced.
Therefore, no crystal defects due to strain are generated, and high-reliability operation without deterioration of device characteristics is enabled.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the configuration of an embodiment of a heterojunction bipolar transistor of the present invention.

FIG. 2 is a sectional view showing the configuration of an embodiment of a heterojunction bipolar transistor of the present invention.

FIG. 3 is a sectional view showing the configuration of an embodiment of the heterojunction bipolar transistor of the present invention.

FIG. 4 is a process cross-sectional view (first half process) showing one embodiment of a method for manufacturing a hetero junction bipolar transistor of the present invention;
It is.

5 is a process cross-sectional view (second half of the process performed after FIG. 4) illustrating the embodiment of the method for manufacturing a heterojunction bipolar transistor of the present invention;

FIG. 6 is a sectional view showing the configuration of an embodiment of the heterojunction bipolar transistor of the present invention.

FIG. 7 is a sectional view showing the structure of a conventional heterojunction bipolar transistor.

[Explanation of symbols]

10 Semi-insulating GaAs substrate 11 Buffer layer (i-GaAs or i-AlGaAs) 12 Collector layer (n-GaAs) 13 Base layer (p-GaAs) 14 Emitter layer (n-AlGaA or n-InGaP) 15 Emitter cap layer (N ⁺ -GaAs) 16 Sub-collector layer (n-GaAs) 17 Emitter cap layer (n ⁺ -InGaAs) 20 Collector electrode (Ni / AuGe / Au alloy) 21 Base electrode (Ti / Pt / Au) 22 Emitter electrode ( WSi) 23 Photoresist 31 Buffer layer (i-GaAs or i-AlGaAs) 32 Collector layer (n-GaAs) 33 Base layer (p-GaAs) 34 Emitter layer (n-AlGaA or n-InGaP) 40 Collector electrode (Ni / AuGe / Au alloy) 41 Base electrode (Ti / Pt / Au) 42 Emitter electrode (WSi) 50 Semi-insulating GaAs substrate 51 Buffer layer (i-GaAs or i-AlGaAs) 52 Collector layer (n-GaAs) 53 Base Layer (p-GaAs) 54 Emitter layer (n-AlGaA or n-InGaP) 55 Emitter cap layer (n ⁺ -GaAs) 56 Subcollector layer (n-GaAs) 60 Collector electrode (Ni / AuGe / Au alloy) 61 Base electrode (Ti / Pt / Au) 62 Emitter electrode (WSi)

Claims (6)

[Claims] 1. A hetero-junction bipolar transistor having an n-type collector layer made of a group III-V compound semiconductor film, a p-type base layer, and an n-type emitter layer having a larger forbidden band width than the p-type base layer on a semiconductor substrate. Wherein the p-type dopant of the p-type base layer is an impurity composed of an atom that does not fall into any of Group III or V, and has a larger atomic radius than the atoms constituting the p-type base layer. A hetero-junction bipolar transistor characterized by being doped with impurities and small impurities. 2. A subcollector layer doped with an n-type impurity at a concentration of 1 × 10 ¹⁸ cm ⁻³ or more is formed between the n-type collector layer and the semiconductor substrate, and a collector is formed on the sub-collector layer. The heterojunction bipolar transistor according to claim 1, wherein an electrode is formed. 3. An emitter cap layer formed on the n-type emitter layer and formed of a compound semiconductor having a smaller forbidden band width than the emitter layer and doped with n-type impurities of 1 × 10 ¹⁸ cm ⁻³ or more. 3. The heterojunction bipolar transistor according to claim 1, wherein an emitter electrode is formed on the emitter cap layer. 4. A step of sequentially epitaxially growing an n-type collector layer, a p-type base layer, and an n-type emitter layer having a larger forbidden band width than the p-type base layer on a semiconductor substrate using a III-V compound semiconductor. Wherein the step of growing the p-type base layer comprises doping an impurity having a larger atomic radius and a smaller impurity than the atoms constituting the p-type base layer in the step of growing the p-type base layer. Of manufacturing a heterojunction bipolar transistor. 5. The method according to claim 1, further comprising the step of epitaxially growing a subcollector layer doped with an n-type impurity at a concentration of 1 × 10 ¹⁸ cm ⁻³ or more between the semiconductor substrate and the n-type collector layer. A method for manufacturing a heterojunction bipolar transistor according to claim 4. 6. The method according to claim 1, further comprising the step of epitaxially growing an emitter cap layer on the n-type emitter layer, the emitter cap layer having a smaller bandgap than the emitter layer and doped with an n-type impurity at a concentration of 1 × 10 ¹⁸ cm ⁻³ or more. 6. The method for manufacturing a heterojunction bipolar transistor according to claim 4 or 5, wherein