JP2001247399A - METHOD FOR PRODUCING HIGH-RESISTANCE GaN CRYSTAL LAYER - Google Patents
METHOD FOR PRODUCING HIGH-RESISTANCE GaN CRYSTAL LAYERInfo
- Publication number
- JP2001247399A JP2001247399A JP2000058829A JP2000058829A JP2001247399A JP 2001247399 A JP2001247399 A JP 2001247399A JP 2000058829 A JP2000058829 A JP 2000058829A JP 2000058829 A JP2000058829 A JP 2000058829A JP 2001247399 A JP2001247399 A JP 2001247399A
- Authority
- JP
- Japan
- Prior art keywords
- gan crystal
- crystal layer
- doped
- resistance
- gan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000013078 crystal Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910052725 zinc Inorganic materials 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000001257 hydrogen Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 17
- 230000005669 field effect Effects 0.000 abstract description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- DIIIISSCIXVANO-UHFFFAOYSA-N 1,2-Dimethylhydrazine Chemical compound CNNC DIIIISSCIXVANO-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 102100021943 C-C motif chemokine 2 Human genes 0.000 description 1
- 101710112287 DNA-directed RNA polymerases I and III subunit RPAC2 Proteins 0.000 description 1
- 101000897480 Homo sapiens C-C motif chemokine 2 Proteins 0.000 description 1
- 101710183183 Probable DNA-directed RNA polymerases I and III subunit RPAC2 Proteins 0.000 description 1
- 102100034616 Protein POLR1D, isoform 2 Human genes 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 238000009739 binding Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は高抵抗ＧａＮ結晶層
の製造方法に関し、更に詳しくは、ＧａＮ系材料を用い
たＭＥＳ（金属−半導体）型の電界効果トランジスタ
（ＦＥＴ）の製造時に適用して好適な高抵抗ＧａＮ結晶
層の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a high-resistance GaN crystal layer, and more particularly to a method of manufacturing a metal-semiconductor (MES) type field effect transistor (FET) using a GaN-based material. The present invention relates to a suitable method for manufacturing a high-resistance GaN crystal layer.
【０００２】[0002]
【従来の技術】最近、化合物半導体材料を用いたＭＥＳ
型ＦＥＴの開発研究が盛んに進められている。その場
合、用いる化合物半導体としては、通常、ＧａＡｓ系の
材料が主流になっていて、一般に、次のようにして製造
される。まず、半絶縁性のＧａＮ単結晶基板の上に、例
えばＭＯＣＶＤ法により、半絶縁性のアンドープのＧａ
Ａｓから成るバッファ層を成膜し、更にその上に、例え
ばＴＭＧ（トリメチルガリウム）またはＴＭＡ（トリメ
チルアルミニウム）とアルシン（ＡｓＨ3）を用い、ま
たｎ型ドーパントとしてシランガスを用いてｎ型のＡｌ
ＧａＡｓ結晶層を活性層として成膜しＦＥＴ層構造を形
成する。2. Description of the Related Art Recently, a MES using a compound semiconductor material has been developed.
Research on the development of type FETs has been actively pursued. In this case, as a compound semiconductor to be used, a GaAs-based material is usually mainly used, and is generally manufactured as follows. First, a semi-insulating undoped Ga is deposited on a semi-insulating GaN single crystal substrate by, for example, MOCVD.
Forming a buffer layer made of As, further thereon, for example, TMG (trimethyl gallium) or TMA using (trimethyl aluminum) and arsine (AsH 3), also of the n-type by using a silane gas as an n-type dopant Al
An FET layer structure is formed by forming a GaAs crystal layer as an active layer.
【０００３】ついで、このｎ型ＡｌＧａＡｓ層の上に、
例えばプラズマＣＶＤ法でＳｉＯ2などを堆積させたの
ち、そこにフォトリソグラフィーと化学エッチング処理
などを組み合わせて、ソース電極、ドレイン電極、およ
びゲート電極を形成するためのパターニングを行い、ソ
ース電極とドレイン電極の形成箇所には例えばＡｕＧｅ
／Ｎｉを蒸着し、またゲート電極の形成箇所にはＡｌを
蒸着して目的とするＦＥＴが製造される。Then, on this n-type AlGaAs layer,
For example, after depositing SiO 2 or the like by a plasma CVD method, patterning for forming a source electrode, a drain electrode, and a gate electrode is performed by combining photolithography and chemical etching, and the like. Is formed, for example, by AuGe
/ Ni is vapor-deposited, and Al is vapor-deposited on the portion where the gate electrode is to be formed, whereby the target FET is manufactured.
【０００４】ところで、ＧａＮ系材料を用いたＦＥＴ
は、高温特性が良好であって、４００℃近い温度環境下
においても熱暴走することなく動作するということが知
られている。このＧａＮ系ＦＥＴを製造する場合、Ｇａ
Ｎ系材料では、ＧａＡｓ結晶の場合のように大口径の単
結晶基板を製造することが困難であるため、単結晶基板
の上に所定のＧａＮ系結晶をエピタキシャル成長させて
所望するＦＥＴ層構造を形成することができない。By the way, FETs using GaN-based materials
Is known to have good high-temperature characteristics and operate without thermal runaway even in a temperature environment close to 400 ° C. When manufacturing this GaN-based FET, Ga
Since it is difficult to manufacture a large-diameter single-crystal substrate as in the case of a GaAs crystal with an N-based material, a desired GaN-based crystal is epitaxially grown on the single-crystal substrate to form a desired FET layer structure. Can not do it.
【０００５】そのため、ＧａＮ系のＦＥＴを製造する際
には、基板としてサファイア，ＳｉＣ，ＧａＡｓなどの
異種類の材料から成る基板を用い、その上に例えばＭＯ
ＣＶＤ法で、一旦、アンドープのＧａＮ結晶層を成膜
し、ついでその上にｎ型のＧａＮ結晶層を活性層として
成膜し、全体のＦＥＴ層構造を形成している。上記した
ＦＥＴ層構造を有するＧａＮ系ＦＥＴが動作するために
は、ｎ型活性層の下に位置するアンドープのＧａＮ結晶
層は高抵抗になっていることが必要である。Therefore, when manufacturing a GaN-based FET, a substrate made of a different kind of material such as sapphire, SiC, or GaAs is used as a substrate, and for example, an MO
An undoped GaN crystal layer is formed once by the CVD method, and then an n-type GaN crystal layer is formed thereon as an active layer to form an entire FET layer structure. In order for the GaN-based FET having the above-described FET layer structure to operate, the undoped GaN crystal layer located below the n-type active layer needs to have high resistance.
【０００６】しかしながら、上記したＦＥＴ層構造を形
成するとき、アンドープのＧａＮ結晶中には窒素空孔に
基づく欠陥が多数存在し、この欠陥がｎ型のキャリアと
して働くため、一般に、ｎ型で低抵抗化してしまうとい
う問題が生ずる。このように、従来は、ＭＯＣＶＤ法で
ＧａＮ系ＦＥＴを製造する場合、活性層の下に位置する
アンドープＧａＮ結晶層を高抵抗化する技術は確立され
ていないのが現状である。However, when the above-described FET layer structure is formed, a large number of defects based on nitrogen vacancies exist in the undoped GaN crystal, and these defects serve as n-type carriers. There is a problem that the resistance is increased. As described above, conventionally, when manufacturing a GaN-based FET by the MOCVD method, a technique for increasing the resistance of the undoped GaN crystal layer located below the active layer has not been established at present.
【０００７】[0007]
【発明が解決しようとする課題】本発明はＧａＮ系材料
でＦＥＴ層構造を形成するときの上記した問題を解決
し、ＧａＮ系ＦＥＴの製造に適用して有効な高抵抗Ｇａ
Ｎ結晶層の製造方法の提供を目的とする。SUMMARY OF THE INVENTION The present invention solves the above-mentioned problem when forming an FET layer structure with a GaN-based material, and provides a high-resistance Ga that is effective when applied to the manufacture of GaN-based FETs.
An object is to provide a method for manufacturing an N crystal layer.
【０００８】[0008]
【課題を解決するための手段】上記した目的を達成する
ために、本発明においては、ＧａＮ結晶をエピタキシャ
ル成長させる際に、Ｃ，Ｍｇ，Ｚｎの群から選ばれる少
なくとも１種のｐ型不純物をドーピングすることを特徴
とする高抵抗ＧａＮ結晶層の製造方法が提供される。In order to achieve the above object, according to the present invention, at the time of epitaxially growing a GaN crystal, at least one p-type impurity selected from the group consisting of C, Mg and Zn is doped. A method for manufacturing a high-resistance GaN crystal layer is provided.
【０００９】具体的には、ＧａＮ結晶をエピタキシャル
成長させる際に、温度６００℃以上の水素雰囲気中でＭ
ｇまたはＺｎをドーピングする高抵抗ＧａＮ結晶層の製
造方法や、ＧａＮ結晶をエピタキシャル成長させる際
に、ＭｇまたはＺｎを１×１０ 17cm-3以上の濃度でドー
ピングしたのち、更にＣを１×１０18cm-3以上の濃度で
ドーピングする高抵抗ＧａＮ結晶層の製造方法が提供さ
れる。Specifically, a GaN crystal is epitaxially
At the time of growth, M
Production of high-resistance GaN crystal layer doped with g or Zn
Manufacturing method and epitaxial growth of GaN crystal
And 1 × 10 Mg or Zn 17cm-3Dough at above concentration
After pinging, further add C to 1 × 1018cm-3With the above concentration
Provided is a method of manufacturing a high-resistance GaN crystal layer to be doped
It is.
【００１０】[0010]
【発明の実施の形態】ＧａＮ結晶には窒素空孔などが多
数存在していて、それがｎ型不純物と同様の働きをする
ために、無添加のＧａＮ結晶は通常のｎ型導電性を示
す。この導電性を打ち消すために、本発明方法では、エ
ピタキシャル成長法でＧａＮ結晶層を成膜する際に、そ
こに、Ｃ，Ｍｇ，Ｚｎの１種または２種以上から成るｐ
型不純物を予めドーピングしておき、そのｐ型不純物に
より、上記欠陥に基づくｎ型の残留キャリアを打ち消
す。もって当該ＧａＮ結晶層のｎ型化を抑制してその高
抵抗化が図られる。すなわち、形成されたＦＥＴ層構造
において、ｎ型の活性層の下に位置するＧａＮ結晶層は
高抵抗になっている。BEST MODE FOR CARRYING OUT THE INVENTION A GaN crystal has a large number of nitrogen vacancies and the like, and acts like an n-type impurity. Therefore, an undoped GaN crystal exhibits normal n-type conductivity. . In order to cancel this conductivity, according to the method of the present invention, when a GaN crystal layer is formed by an epitaxial growth method, a p-type layer composed of one or more of C, Mg and Zn is formed thereon.
A type impurity is previously doped, and the n-type residual carrier based on the defect is canceled by the p-type impurity. As a result, the GaN crystal layer is prevented from becoming n-type, and its resistance is increased. That is, in the formed FET layer structure, the GaN crystal layer located under the n-type active layer has a high resistance.
【００１１】具体的には、次のような態様が実施され
る。第１の態様はＭｇまたはＺｎを用いた場合であっ
て、この場合には、ＧａＮ結晶層の成膜を高温のＨ2雰
囲気中で行い、そのときに、ＭｇまたはＺｎをドーピン
グする。この過程で、ＭｇまたはＺｎはＨと結合し、そ
の結果、成膜されたＧａＮ結晶層は電気的に不活性とな
る。すなわち、高抵抗化する。このときの温度は６００
℃以上に設定される。６００℃より低い温度の場合は、
上記した結合反応が充分に進行しないからである。この
ような状態にあるＧａＮ結晶層の上にｎ型の活性層を成
膜しても、当該ＧａＮ結晶層がｎ型化して低抵抗化する
ことは起こりづらくなる。Specifically, the following embodiment is implemented. The first embodiment is a case where Mg or Zn is used. In this case, the GaN crystal layer is formed in a high-temperature H 2 atmosphere, and at that time, Mg or Zn is doped. In this process, Mg or Zn bonds with H, and as a result, the formed GaN crystal layer becomes electrically inactive. That is, the resistance is increased. The temperature at this time is 600
Set to ℃ or higher. For temperatures below 600 ° C,
This is because the above-described binding reaction does not proceed sufficiently. Even if an n-type active layer is formed on the GaN crystal layer in such a state, it is unlikely that the GaN crystal layer becomes n-type and has low resistance.
【００１２】第２の態様はＣを用いた場合であって、こ
の場合には、ＧａＮ結晶層の成膜時にＭｇまたはＺｎを
ドーピングして成膜されるＧａＮ結晶層におけるキャリ
ア濃度を低減し、その状態で更に高濃度のＣをドーピン
グする。ドーピングされたＣはＧａＮ結晶層中に深い準
位を形成するのでＧａＮ結晶層は高抵抗化する。この場
合、ＧａＮ結晶層のキャリア濃度を補償するためにドー
ピングする上記ＭｇまたはＺｎの濃度は１×１０17cm―
3以上に設定される。濃度がこれより高くなると、Ｇａ
Ｎ結晶層はｐ型傾向を示しはじめるからである。また、
Ｃのドーピング濃度は１×１０18cm―3以上に設定され
る。濃度がこれより低くなると、ＧａＮ結晶層中の準位
は浅くなって、高抵抗化の実現が困難になるからであ
る。The second mode is a case where C is used. In this case, the carrier concentration in the GaN crystal layer formed by doping Mg or Zn during the formation of the GaN crystal layer is reduced, In this state, a higher concentration of C is doped. Since the doped C forms a deep level in the GaN crystal layer, the resistance of the GaN crystal layer is increased. In this case, the concentration of Mg or Zn doped to compensate for the carrier concentration of the GaN crystal layer is 1 × 10 17 cm −
Set to 3 or more. At higher concentrations, Ga
This is because the N crystal layer starts to show a p-type tendency. Also,
The doping concentration of C is set to 1 × 10 18 cm −3 or more. If the concentration is lower than this, the level in the GaN crystal layer becomes shallow, and it is difficult to realize high resistance.
【００１３】[0013]
【実施例】本発明の実施例を、ＧａＮ系ＦＥＴの製造に
適用した事例として以下に説明する。まず、図１で示し
たように、例えばサファイアから成る半絶縁性基板１の
上に、ＭＢＥ法で、ジメチルヒドラジン（３×１０-6To
rr），金属Ｇａ（５×１０-7Torr），金属Ｍｇ（１×１
０-8Torr）、およびＨ2（５×１０-8Torr）を用い、成
長温度６４０℃で厚み２nmのＧａＮ結晶層をバッファ層
２Ａとして成膜し、更にその上に、厚み１μｍのＭｇド
ープＧａＮ結晶層（Ｍｇのドーピング濃度：１×１０17
cm-3）２Ｂを成膜した。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below as an example applied to the manufacture of a GaN-based FET. First, as shown in FIG. 1, a dimethylhydrazine (3 × 10 −6 To
rr), metal Ga (5 × 10 −7 Torr), metal Mg (1 × 1
0 -8 Torr) and H 2 (5 × 10 -8 Torr), a GaN crystal layer having a thickness of 2 nm is formed as a buffer layer 2A at a growth temperature of 640 ° C., and a 1 μm thick Mg-doped layer is further formed thereon. GaN crystal layer (Mg doping concentration: 1 × 10 17
cm -3 ) 2B was deposited.
【００１４】ついで、ＭｇドープＧａＮ結晶層２Ｂにジ
メチルヒドラジン（３×１０-6Torr）を照射しながら温
度６４０℃で１０分間保持した。更に、金属Ｇａ（８×
１０-7Torr）とアンモニア（５×１０-5Torr）を用い、
またｎ型ドーパントとしてＳｉ（１×１０-9Torr）を用
い、成長温度８５０℃でＭｇドープＧａＮ結晶層２Ｂの
上に厚み３０nmのｎ型のＳｉドープＧａＮ結晶層３を成
膜した。このときにｎ型キャリア濃度が２×１０17cm-3
になることは、事前にホール測定で確認してある。Then, the Mg-doped GaN crystal layer 2B was maintained at a temperature of 640 ° C. for 10 minutes while being irradiated with dimethylhydrazine (3 × 10 −6 Torr). Furthermore, metal Ga (8 ×
10 -7 Torr) and ammonia (5 × 10 -5 Torr)
Using Si (1 × 10 −9 Torr) as an n-type dopant, a 30-nm thick n-type Si-doped GaN crystal layer 3 was formed on the Mg-doped GaN crystal layer 2B at a growth temperature of 850 ° C. At this time, the n-type carrier concentration is 2 × 10 17 cm −3.
Has been confirmed in advance by Hall measurement.
【００１５】ついで、ＳｉドープＧａＮ結晶層３の全面
にＳｉＯ2膜を成膜し、更にその上にフォトレジストを
塗布したのちパターニングし、ついでフッ酸を用いてＳ
ｉＯ 2膜に部分的に窓あけを行った。そして、エレクト
ロサイクロトロンレゾナンス（ＥＣＲ）プラズマ装置を
用い、メタン，アルゴン，水素の混合ガスをプラズマ化
したエッチングガスを前記した窓あけ部分に照射して当
該部分にＭｇドープＧａＮ結晶層２Ｂの表面が表出する
までのエッチング処理を行ったのち、残りのＳｉＯ2膜
の全体をエッチング除去した。Next, the entire surface of the Si-doped GaN crystal layer 3
SiOTwoA film is formed, and a photoresist is further formed on it.
After applying, patterning is performed, and then S
iO TwoThe membrane was partially windowed. And the elect
Cyclotron Resonance (ECR) plasma equipment
Use to convert a mixed gas of methane, argon, and hydrogen into plasma
Irradiated the etched gas into the window opening
The surface of the Mg-doped GaN crystal layer 2B appears at this portion.
After the etching process up toTwofilm
Was removed by etching.
【００１６】ついで、ＳｉドープＧａＮ結晶層３の上
に、フォトレジストを用いてソース電極とドレイン電極
の形成箇所をパターニングしたのち、その形成箇所にＴ
ｉ／Ａｌを真空蒸着してソース電極とドレイン電極を形
成し、それ以外の部分のＴｉ／Ａｌはリフトオフした。
更に、フォトレジストを用いてゲート電極の形成箇所を
パターニングし、その形成箇所にＴｉ／Ｐｔを真空蒸着
してゲート電極を形成し、それ以外のＴｉ／Ｐｔをリフ
トオフすることにより、図３で示したＦＥＴを製造し
た。Next, after forming a source electrode and a drain electrode on the Si-doped GaN crystal layer 3 by using a photoresist, patterning is performed.
i / Al was vacuum-deposited to form a source electrode and a drain electrode, and other portions of Ti / Al were lifted off.
Further, a portion where the gate electrode is to be formed is patterned by using a photoresist, Ti / Pt is vacuum-deposited on the portion where the gate electrode is formed, and a gate electrode is formed, and other Ti / Pt is lifted off, as shown in FIG. Manufactured FETs.
【００１７】このＦＥＴの電気的特性の評価を行った。
ソース電極とドレイン電極間のコンタクト抵抗は１×１
０-6Ω・cm2であり、両電極はオーミック接触している
ことが確認された。また、ゲート電極は整流特性を示
し、そのときの立ち上がり電圧は１.１Ｖであった。更
に、ＦＥＴの飽和特性も良好であった。The electrical characteristics of this FET were evaluated.
Contact resistance between source electrode and drain electrode is 1 × 1
0 −6 Ω · cm 2 , and it was confirmed that both electrodes were in ohmic contact. The gate electrode exhibited rectification characteristics, and the rising voltage at that time was 1.1 V. Further, the saturation characteristics of the FET were also good.
【００１８】このようなことから、本発明方法を適用し
て成膜したバッファ層２ＡとＭｇドープＧａＮ結晶層は
いずれも高抵抗であることを確認することができる。な
お、上記実施例では、ＧａＮ結晶層の成膜時における窒
素源としてはジメチルヒドラジンとアンモニア、Ｇａ源
としては金属Ｇａを用いたが、プラズマ窒素，ラジカル
窒素を用いることもでき、またＧａ源としてはＴＥＧや
ＴＭＧを用いることもできる。From the above, it can be confirmed that both the buffer layer 2A and the Mg-doped GaN crystal layer formed by applying the method of the present invention have high resistance. In the above embodiment, dimethylhydrazine and ammonia were used as the nitrogen source when the GaN crystal layer was formed, and metal Ga was used as the Ga source. However, plasma nitrogen and radical nitrogen can also be used. May use TEG or TMG.
【００１９】更に、上記実施例では、エピタキシャル成
長法としてＭＢＥ法を採用したが、ＭＯＣＶＤ法でも同
様の結果を得ることができた。なお、上記実施例のＭｇ
ドープＧａＮ結晶層２Ｂのキャリア濃度は１×１０15cm
-3以下であった。そして、Ｍｇをドーピングしないとき
に成膜されるアンドープＧａＮ結晶層のキャリア濃度は
１×１０17cm-3であった。Further, in the above embodiment, the MBE method was employed as the epitaxial growth method, but the same result could be obtained by the MOCVD method. Note that the Mg in the above embodiment
The carrier concentration of the doped GaN crystal layer 2B is 1 × 10 15 cm
-3 or less. The carrier concentration of the undoped GaN crystal layer formed when not doped with Mg was 1 × 10 17 cm −3 .
【００２０】すなわち、Ｍｇを１×１０17cm-3の濃度で
ドーピングすることにより、上記アンドープＧａＮ結晶
層のキャリアは打ち消されている。そこで、このＭｇド
ープＧａＮ結晶層２Ｂ（キャリア濃度：１×１０15cm-3
以下）に更にＣを１×１０18cm-3ドーピングしてＦＥＴ
層構造を形成し、それを用いて実施例と同様にＦＥＴを
製造し、その電気的特性を評価したところ、上記した実
施例の場合と同様の結果が得られた。That is, by doping Mg at a concentration of 1 × 10 17 cm −3 , the carriers of the undoped GaN crystal layer are canceled. Therefore, the Mg-doped GaN crystal layer 2B (carrier concentration: 1 × 10 15 cm −3)
FET) doped with C at 1 × 10 18 cm -3
A layer structure was formed, and a FET was manufactured using the layer structure in the same manner as in the example. The electrical characteristics of the FET were evaluated. As a result, the same result as in the above example was obtained.
【００２１】[0021]
【発明の効果】以上の説明で明らかなように、本発明方
法によれば、高抵抗のＧａＮ結晶層を製造することがで
きる。そして、本発明を適用することにより、高温動作
が可能なＧａＮ系のＦＥＴを製造することができるの
で、その工業的価値は大である。As is apparent from the above description, according to the method of the present invention, a high-resistance GaN crystal layer can be manufactured. By applying the present invention, a GaN-based FET capable of operating at a high temperature can be manufactured, so that its industrial value is great.
【図１】本発明方法で、基板の上に高抵抗のＧａＮ結晶
層を成膜した状態を示す断面図である。FIG. 1 is a cross-sectional view showing a state in which a high-resistance GaN crystal layer is formed on a substrate by the method of the present invention.
【図２】本発明による高抵抗ＧａＮ結晶層の上にＳｉド
ープＧａＮ結晶層を成膜した状態を示す断面図である。FIG. 2 is a cross-sectional view showing a state in which a Si-doped GaN crystal layer is formed on a high-resistance GaN crystal layer according to the present invention.
【図３】ＧａＮ系ＦＥＴの断面構造を示す断面図であ
る。FIG. 3 is a cross-sectional view illustrating a cross-sectional structure of a GaN-based FET.
１ 半絶縁性基板（サファイア） ２Ａ バッファ層 ２Ｂ ＭｇドープＧａＮ結晶層 ３ ＳｉドープＧａＮ結晶層 Reference Signs List 1 semi-insulating substrate (sapphire) 2A buffer layer 2B Mg-doped GaN crystal layer 3 Si-doped GaN crystal layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/812 Ｆターム(参考） 4G077 AA03 BE15 DA05 EB01 EB02 ED06 EF01 EF03 HA06 SA04 5F045 AA04 AA05 AB14 AC08 AC09 AC19 AD10 AD12 AE05 AE07 AF04 AF09 BB16 CA06 DA53 DA59 DA66 5F102 GB01 GC01 GD01 GJ10 GK04 GL04 GS01 GT03 HC01 HC11 HC16 5F103 AA05 DD01 GG01 HH03 HH04 JJ01 KK01 KK07 KK10 LL08 RR05 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI Theme coat ゛ (Reference) H01L 29/812 F-term (Reference) 4G077 AA03 BE15 DA05 EB01 EB02 ED06 EF01 EF03 HA06 SA04 5F045 AA04 AA05 AB14 AC08 AC09 AC19 AD10 AD12 AE05 AE07 AF04 AF09 BB16 CA06 DA53 DA59 DA66 5F102 GB01 GC01 GD01 GJ10 GK04 GL04 GS01 GT03 HC01 HC11 HC16 5F103 AA05 DD01 GG01 HH03 HH04 JJ01 KK01 KK07 KK10 LL08 RR05
Claims (3)
際に、Ｃ，Ｍｇ，Ｚｎの群から選ばれる少なくとも１種
のｐ型不純物をドーピングすることを特徴とする高抵抗
ＧａＮ結晶層の製造方法。1. A method for manufacturing a high-resistance GaN crystal layer, comprising doping at least one type of p-type impurity selected from the group consisting of C, Mg, and Zn when epitaxially growing a GaN crystal.
際に、温度６００℃以上の水素雰囲気中でＭｇまたはＺ
ｎをドーピングする請求項１の高抵抗ＧａＮ結晶層の製
造方法。2. When epitaxially growing a GaN crystal, Mg or Z in a hydrogen atmosphere at a temperature of 600 ° C. or higher.
The method for producing a high-resistance GaN crystal layer according to claim 1, wherein n is doped.
際に、ＭｇまたはＺｎを１×１０17cm-3以上の濃度でド
ーピングしたのち、更にＣを１×１０18cm-3以上の濃度
でドーピングする請求項１の高抵抗ＧａＮ結晶層の製造
方法。3. When epitaxially growing a GaN crystal, after doping Mg or Zn at a concentration of 1 × 10 17 cm −3 or more, C is further doped at a concentration of 1 × 10 18 cm −3 or more. 1. A method for manufacturing a high-resistance GaN crystal layer.
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| JP2000058829A JP4429459B2 (en) | 2000-03-03 | 2000-03-03 | Method for producing high-resistance GaN crystal layer |
| US09/770,526 US20010015437A1 (en) | 2000-01-25 | 2001-01-25 | GaN field-effect transistor, inverter device, and production processes therefor |
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|---|---|---|---|
| JP2000058829A JP4429459B2 (en) | 2000-03-03 | 2000-03-03 | Method for producing high-resistance GaN crystal layer |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPWO2003098708A1 (en) * | 2001-06-06 | 2005-09-22 | アンモノ・スプウカ・ジ・オグラニチョノン・オドポヴィエドニアウノシツィオンＡＭＭＯＮＯ Ｓｐ．ｚｏ．ｏ． | Phosphor single crystal substrate, manufacturing method thereof, and nitride semiconductor device using the same |
| JP2006135274A (en) * | 2004-10-06 | 2006-05-25 | New Japan Radio Co Ltd | Nitride semiconductor device and its manufacturing method |
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