JP3439111B2 - High mobility transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high mobility transistor (HEMT) made of a GaN compound semiconductor,
More specifically, it relates to a HEMT having a novel structure which can be operated under high voltage application.

[0002]

2. Description of the Related Art A HEMT is expected as a material for a high-power microwave device, for example, and is currently manufactured by using a GaAs compound semiconductor. For example, an i-type GaAs layer and an n-type GaA are formed on a semi-insulating substrate.
l _x As _1-x layers are sequentially deposited, and the n-type GaAl _x
There is known a structure in which a source electrode and a drain electrode are loaded on an As _1-x layer, and a gate electrode is loaded via an insulating layer made of, for example, SiO ₂ .

In the case of HEMT having this structure, x = 0.25
Looking at the energy band diagram for, n-type GaAl
The hetero barrier (ΔEc) at the heterojunction interface between the _0.25 As _0.75 layer and the i-type GaAs layer is about _0.26 eV, and in the thermal equilibrium state, a two-dimensional electron gas layer is formed at the junction interface. ing. Then, by applying a reverse bias voltage having a predetermined value between the source electrode and the drain electrode and applying a forward bias voltage between the source electrode and the gate electrode, the n-type GaAl _x As _{1 -x} layer is separated from the n-type GaAl _x As _{1 -x} layer. Electrons are supplied to the i-type GaAs layer located therebelow, and the supplied electrons form a two-dimensional electron gas layer at the junction interface, and the electrons are rapidly confined to the drain electrode while being confined in the gas layer. To realize HEMT operation. In that case, the higher the electric field strength immediately below the gate voltage, the higher the effect of confining electrons in the two-dimensional electron gas layer, and thus the higher-speed operation becomes easier to realize.

However, in the case of GaAs HEMT, the discontinuous band at the heterojunction interface is 0.26 eV.
Since the dielectric breakdown electric field value is about 3 × 10 ⁵ V / cm, a high voltage is applied to the gate electrode to form a high electric field directly under the gate electrode. There is a difficulty in achieving high speed operation. For the purpose of addressing such a problem, trial manufacture of a HEMT using a GaN-based compound semiconductor has recently been conducted.

This means that the heterobarrier (ΔEc) at the heterojunction interface between GaAl _x N _1-x and GaN is about 0.67e.
V has a discontinuous band that is about 2.6 times higher than that of GaAs system, and its dielectric breakdown electric field value is 2 × 10.
^Since it is ⁶ V / cm, which is an order of magnitude larger than that of the GaAs system, it is possible to enhance the effect of confining electrons in the two-dimensional electron gas layer, and theoretically, the electron concentration is 10 This is because it can be doubled.

As the GaN HEMT, for example, the following one is manufactured by using the MOCVD method.
That is, first, on a semi-insulating sapphire substrate, Al
An N buffer layer is deposited. Then, using trimethylgallium as a Ga source and ammonia as an N source, the above A
An i-type GaN layer is formed on the 1N buffer layer, and an n-type AlGaN layer is formed on the i-type GaN layer using trimethylaluminum as an Al source. And this n
After performing conventional photolithography and etching on the type AlGaN layer, a gate electrode, a source electrode, and a drain electrode are loaded at predetermined locations.

In the case of this GaN-based HEMT, i-type GaN
Layer and n-type AlGaN layer heterojunction interface, specifically i
A two-dimensional electron gas layer is formed on the uppermost layer of the n-type GaN layer.
Realize the action. At this time, in order to realize high electron mobility, it is necessary that impurities and crystal defects are not present as much as possible in the i-type GaN layer.

[0008]

However, in the case of the above-mentioned GaN-based HEMT, it is possible to apply a higher voltage than that of the GaAs-based HEMT, but with respect to the recent situation where further high speed operation is required. Is not necessarily one that exhibits sufficient electron mobility. It is an object of the present invention to solve the above-mentioned problems in the conventional GaN-based HEMT and to provide a GaN-based HEMT having a novel structure having high withstand voltage.

[0009]

In order to achieve the above object, in the present invention, the lower i-type semiconductor layer and the concentration of the n-type dopant are 2 × 10 ¹⁷ to 1 on the semi-insulating substrate.
A laminated structure is formed by laminating an n-type semiconductor layer of × 10 ¹⁸ cm ⁻³ and an upper i-type semiconductor layer in this order, and each of the semiconductor layers is made of a GaN-based compound semiconductor, and the upper portion is formed. A gate electrode is loaded on the i-type semiconductor layer via an insulating layer, and a source electrode is placed on the upper i-type semiconductor layer via a conductive n-type semiconductor layer made of a GaN-based compound semiconductor. There is provided a high mobility transistor, characterized in that it is loaded with a drain electrode and a drain electrode, respectively.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The HEMT of the present invention will be described below.
A detailed description will be given based on FIG. 1 showing the basic structure. In the HEMT of the present invention, a laminated structure A composed of a buffer layer 2, a lower i-type semiconductor layer 3, an n-type semiconductor layer 4, and an upper i-type semiconductor layer 5 is formed on a semi-insulating substrate 1, and an upper i-type is formed. On the semiconductor layer 5, a gate electrode G is loaded via an insulating layer 6, and a source electrode S and a drain electrode D are loaded via low resistance n-type semiconductor layers 7a and 7b, respectively. ing.

Here, the source electrode S and the drain electrode G
Are loaded on the upper i-type semiconductor layer 5 via the low-resistance n-type semiconductor layers 7a and 7b, respectively, so that the upper i-type semiconductor layer 5 functioning as an electron channel, the source electrode S, and the drain electrode are formed. Ohmic contact can be realized between the two, which enables high electron mobility. Layered structure A of the HEMT of the present invention, by applying the MOCVD method or MOMBE method such as a known epitaxial growth method with respect to GaN-based compound semiconductor, forming a semiconductor layer having a predetermined composition on a semi-insulating substrate 1 It can be manufactured by carrying out.

Here, it is originally preferable that the semi-insulating substrate 1 is made of a material that is lattice-matched with each semiconductor layer to be formed thereon, but with respect to the GaN-based substrate, this is the case. Since such a material does not exist, a substrate of a conventionally used material, for example, a semi-insulating material such as sapphire or Si single crystal may be used. A GaN layer is selected as the buffer layer 2.

Lower i-type semiconductor layer 3 and upper i-type semiconductor layer 5
Examples of the GaN-based compound semiconductor forming
Type GaN, i type In GaN, i type GaNAs, i type Ga
NP, i-type InGaNAs, i-type InGaNP, etc. can be mentioned. Of these, i-type GaN is preferable. As the material of the upper i-type semiconductor layer 5, it is preferable to use one having a smaller bandgap energy than the material of the lower i-type semiconductor layer 3. This is because a current easily flows and the function as a channel can be improved.

Examples of the GaN-based compound semiconductor forming the n-type semiconductor layer 4 include n-type AlGaN and n-type Ga.
N, nAlInGaN etc. can be mentioned. Of these, n-type AlGaN is preferable. When the n-type semiconductor layer 4 is composed of n-type Al _x Ga _1-x N , the heterobarrier (ΔEc) at the heterojunction interface with the upper i-type semiconductor layer 5 should be increased as x becomes larger. Therefore, the effect of confining electrons in the two-dimensional electron gas layer 5a can be enhanced. However, when x becomes larger than 0.5, Al _x Ga _1-x N starts to show an insulating property, so x
It is necessary to regulate the value to 0.5 or less to ensure conductivity.

Examples of the n-type dopant used when forming the n-type semiconductor layer 4 include metal Si and disilane (MO).
The case of manufacturing by applying the CVD method) and the like can be mentioned. The concentration of the n-type dopant in the n-type semiconductor layer 4 is set to be lower than the concentration in the conductive n-type semiconductor layers 7a and 7b described later. For example, when the n-type dopant is Si, 2 × 10 ¹⁷ to ^{Make it} about 1 × 10 ¹⁸ cm ^-3 .

Examples of the material forming the insulating layer 6 include i-type AlGaN and i-type AInGaN, and may be insulating diamond.
Of these, i-type AlGaN is preferable. Conductivity n
As the GaN-based compound semiconductor forming the type semiconductor layers 7a and 7b, the same material as that of the n-type semiconductor layer 4 may be used, and among them, n-type GaN is preferable. However, in order to realize ohmic contact between the upper i-type semiconductor layer 5 and the source electrode S and the drain electrode G, good conductivity is imparted by increasing the doping amount of the n-type dopant, for example. When the n-type dopant is, for example, Si, the doping is performed so that the concentration is about 8 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

As the conductive n-type semiconductor layer, if the band gap energy is smaller than that of the conductive n-type GaN, for example, n-type GaNAs, n-type GaNP, n-type G.
It is also possible to use aInNAs, n-type InGaNP, or the like. Finally, the material forming the gate electrode G can be, for example, Au / Pt, and the material forming the gate electrode G can be, for example, Ti / Al.

Since the HEMT having this structure has the insulating layer 6 interposed between the gate electrode G and the upper i-type semiconductor layer 5, it can be operated at a high voltage. Therefore, if a voltage VG is applied to the gate electrode G, for example, the gate electrode G
Below, as shown in the energy band diagram of Fig. 2,
In the upper i-type semiconductor layer 5, the effect of confining electrons in the two-dimensional electron gas layer 5a formed at the heterojunction interface with the n-type semiconductor layer 4 is enhanced, and high-speed movement of electrons is realized.

[0019]

EXAMPLE A MOMB of the HEMT having the laminated structure shown in FIG.
It was produced by the method E as follows. First, the semi-insulating
On the Si single crystal substrate 1, metal Ga (5 ×
10 ^-7Torr), dimethylhydrazine (5 × 1) as N source
0^-FiveEpitaxial growth at a growth temperature of 640 ° C using Torr)
Growth is performed and a GaN buffer layer 2 having a thickness of 50Å is formed.
It was

Then, the N source was changed to ammonia (5 × 10 ^-5 To
rr), the growth temperature is raised to 850 ° C. to perform epitaxial growth, and the i-type GaN layer 3 having a thickness of 5000 Å is formed.
Was deposited. The carrier concentration at this time is 5 × 10.
^The film forming conditions were set so as to be ¹⁶ cm ⁻³ or less. Then,
Metal Al (2 × 10 ^-7 Torr) is supplied, and metal Si (2 × 10 ^-9 Torr) is supplied as an n-type dopant, and epitaxial growth is continued at a growth temperature of 850 ° C. to obtain an n-type with a thickness of 500 Å. The AlGaN layer 4 was formed. At this time,
The film forming conditions were set so that the carrier concentration was 1 × 10 ¹⁸ cm ⁻³ .

The supply of metal Al and metal Si was cut off, and metal G
a (5 × 10 ^-7 Torr), ammonia (5 × 10 ^-5 Torr)
Was used for epitaxial growth at a growth temperature of 850 ° C., and an i-type GaN layer 5 having a thickness of 2500 Å was formed to form a laminated structure A. At this time, the carrier concentration is 5 × 10 ^16.
The film forming conditions were set so as to be cm ⁻³ or less. And next, metal Ga (5 × 10 ⁻⁷ Torr), ammonia (5 × 1
0 ^-5 Torr), a metal Si (2 × 10 as n-type dopant
^-9 Torr) is used to perform epitaxial growth at a growth temperature of 850 ° C., and an n-thickness of 500 Å is formed on the above laminated structure A.
A type GaN layer was formed. At this time, the carrier concentration is 3 ×
The film forming conditions were set so as to be 10 ¹⁸ cm ⁻³ . Note that this layer functions as the conductive n-type semiconductor layers 7a and 7b in FIG.

Then, the above n-type Ga is formed by plasma CVD.
After forming a SiO ₂ film on the entire surface of the N layer and patterning it with a photoresist, dry etching is performed by using a mixed gas of hydrogen, argon and methane as plasma as an etchant to load the source electrode and the drain electrode. The SiO ₂ film on the other part is removed leaving the part and i-type Ga
The surface of the N layer 5 was exposed.

After that, a SiO ₂ film is formed on the entire surface by plasma CVD, patterned with a photoresist, and then a portion including a portion where a gate electrode is to be loaded is removed by etching. Ga (5 × 10 ⁻⁷ Torr), ammonia (5 × 1
0 ^-5 Torr) and metallic Al (2 x 10 ^-7 Torr) were selectively grown at a growth temperature of 850 ° C to obtain i-type A with a thickness of 500 Å.
An lGaN layer was formed. Note that this layer functions as the insulating layer 6 in FIG.

Then, the SiO ₂ film is removed by etching with hydrofluoric acid, and the entire surface of the SiO ₂ film is again etched by the plasma CVD method.
An n-type GaN layer is formed by forming a film, masking the portions where the gate electrode should be loaded, opening the portions where the source electrode and the drain electrode should be loaded, and depositing Ti / Al in the openings and lifting off. Source electrode S on 7a, 7b
And the drain electrode G.

Finally, the masking is removed by etching, the underlying SiO ₂ film is opened, and the portions of the source electrode S and the drain electrode G are masked with the SiO ₂ film.
Au / Pt is vapor-deposited on the opening and lifted off. As a result, the gate electrode G is loaded on the i-type AlGaN layer 6. In this HEMT, the contact resistance between the source electrode S, the drain electrode D and the i-type GaN layer 5 is 1 × 10 ^−6.
Ω / cm ² , which was a sufficiently small value.

The mobility of this HEMT is 77K and 70
The value was as high as 00 cm ² / V · sec, and the Schottky gate withstand voltage exceeded 500 V and showed good characteristics. Further, a transistor characteristic was obtained in which the source / drain current (Ids) was 50 mA and the drain voltage was saturated at 2V.

[0027]

As is apparent from the above description, the GaN-based HEMT of the present invention does not cause a failure even if the gate voltage is increased to 500 V, and the conventional GaN-based HEMT is not used.
It can operate at higher speed than This is because the insulating structure is provided between the gate electrode and the channel layer, and the layer structure below the gate electrode is made into an ini structure, so that an electron confinement effect is obtained at the junction interface between the upper i-type semiconductor layer and the n-type semiconductor layer. This is an effect brought about by the fact that the two-dimensional electron gas layer excellent in is formed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a layer structure of a HEMT of the present invention.

FIG. 2 is an energy band diagram in the vicinity of an upper i-type semiconductor layer in the layer structure of the present invention.

[Explanation of symbols]

1 semi-insulating substrate 2 buffer layer (GaN layer) 3 lower i-type semiconductor layer (i-type GaN layer) 4 n-type semiconductor layer (Si-doped n-type AlGaN)
Layer) 5 upper i-type semiconductor layer (i-type GaN layer) 5a two-dimensional electron gas layer 6 insulating layer (i-type AlGaN layer) 7a, 7b conductive n-type semiconductor layer (Si-doped n-type Ga)
(N layer)

Claims (2)

(57) [Claims] 1. A semi-insulating substrate having a lower i-type semiconductor layer and an n-type dopant concentration of 2 × 10 ¹⁷ to 1 × 10 ¹⁸ cm 2.
N-type semiconductor layer of ^-3, and a top i-type semiconductor layer laminated structure formed by laminating in this order is formed, the both semiconductor layers are made of GaN-based compound semiconductor, and the upper i-type semiconductor layer A gate electrode is loaded on the upper part of the gate electrode via an insulating layer, and Ga is formed on the upper i-type semiconductor layer.
A high-mobility transistor characterized in that a source electrode and a drain electrode are respectively loaded through a conductive n-type semiconductor layer made of an N-based compound semiconductor. 2. The lower i-type semiconductor layer and the upper i-type semiconductor layer are made of i-type GaN, and the n-type semiconductor layer is n-type Al.
The high mobility transistor according to claim 1, wherein the high mobility transistor is made of GaN, the insulating layer is made of i-type AlGaN, and the conductive n-type semiconductor layer is made of n-type GaN.