JP4169553B2 - Resonant tunnel device and semiconductor integrated circuit using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a resonant tunnel element and a semiconductor integrated circuit using the same, and more particularly to a resonant tunnel element formed using a GaAs-based material and a semiconductor integrated circuit using the same.
[0002]
[Prior art]
A resonant tunneling diode (RTD) has a barrier structure in which a well layer made of a semiconductor is sandwiched between potential barrier layers formed so as to be thin enough to cause resonant tunneling of electrons on both sides. is doing. RTDs are expected to be applied to ultra high-speed digital circuits because they have negative differential resistance characteristics and high-speed switching characteristics. Further, by using such a resonant tunneling element structure, it is possible to realize an effective and functional element for circuit integration, such as a resonant tunneling hot electron transistor (RHET).
[0003]
For digital circuit applications operating at 40 Gbps, the peak current density of the RTD is 1 × 10 ^Five A / cm ² A degree is necessary. Moreover, even at high peak current densities above room temperature, a peak current / valley current ratio (P / V ratio), which is a characteristic characteristic of RTD, is required to be about 5 to 10. At present, a monostable bistable transition logic gate in which an InP-based RTD using InGaAs as a well layer and AlAs as a barrier layer is combined with an InP-based transistor (for example, High Electron Mobility Transistor; HEMT, Heterojunction Bipolar Transistor; HBT) MOnostable-BIstable transition logic element (MOBILE) is widely used.
[0004]
FIG. 6 is a diagram showing a circuit configuration example of MOBILE.
The MOBILE shown in FIG. 6 is configured by connecting two RTDs 1 and RTD2 in series, and connecting an HEMT to the RTD2 in parallel. In the parallel element of RTD2 and HEMT, there is a current flowing through RTD2 and a current flowing through HEMT, and the current flowing between terminals A and B can be controlled by the gate voltage (Vg) of HEMT.
[0005]
FIG. 7 is a diagram showing current-voltage characteristics in a parallel element of RTD and HEMT. In the MOBILE shown in FIG. 6, the current I (RTD2 + HEMT) flowing through the parallel element of RTD2 and HEMT shows a negative differential resistance characteristic, and the current value changes with a change in VMT of HEMT. By utilizing such a feature, it becomes possible to perform a latch operation based on a difference in magnitude between the current I (RTD2 + HEMT) of the RTD2 and HEMT parallel elements and the current I (RTD1) of the RTD1.
[0006]
FIG. 8 is a load curve diagram of MOBILE, where (a) shows that I (RTD2 + HEMT) is larger than I (RTD1), and (b) shows that I (RTD2 + HEMT) is smaller than I (RTD1). Shows the case. However, in FIG. 8, the parallel element of RTD2 and HEMT is indicated as “RTD2 + HEMT”.
[0007]
When I (RTD2 + HEMT)> I (RTD1) in the relationship between I (RTD2 + HEMT) and the applied voltage V and in the relationship between I (RTD1) and the applied voltage V, MOBILE is shown in FIG. ) As shown in the lower voltage value V _L It will be latched by. On the other hand, when I (RTD2 + HEMT) <I (RTD1), MOBILE has a high voltage value V as shown in FIG. _H It will be latched by. Using such MOBILE, a return zero DFF circuit can be realized.
[0008]
Incidentally, the InP-based transistor has a problem that its withstand voltage is relatively lower than that of the GaAs-based transistor, and a margin in circuit design becomes narrow. On the other hand, in the return zero DFF circuit using MOBILE, the RTD current density is 1 × 10 5. ^Five A / cm ² If so, the current gain cutoff frequency f of the transistor to be combined _t May be about 100 GHz. That is, this is a value that can be realized by a GaAs HEMT or HBT. In forming an integrated circuit, if HEMT or HBT is made of GaAs and a high-performance RTD with a high current density can be formed, it is advantageous in terms of breakdown voltage and further in terms of cost.
[0009]
However, for example, in a GaAs / AlGaAs-based RTD in which the well layer is made of GaAs and the barrier layer is made of AlGaAs, or the barrier layer is made of AlAs, a 1 × 10 ^Four A / cm ² It becomes difficult to obtain a high P / V ratio of 5 or less at a high current density exceeding 1.
[0010]
FIG. 9 is a diagram showing an example of an energy band structure of a GaAs / AlAs RTD.
The GaAs / AlAs RTD has a double barrier structure in which both sides of a GaAs well layer are sandwiched between AlAs barrier layers and a GaAs spacer layer is formed outside the AlAs. In the case of an RTD having such a structure, as shown in FIG. 9, the difference ΔEc (Γ−Γ) between the Γ points of the conduction band energies Ec of GaAs and AlAs is as large as about 1 eV. However, the AlAs barrier layer is an indirect transition semiconductor, and its X point is arranged at an energy position slightly higher than about 0.2 eV with respect to Ec of GaAs. Therefore, the thermal excitation current flowing through the point X becomes a surplus current, and as a result, the valley current increases and the P / V ratio becomes low.
[0011]
In order to deal with such problems, conventionally, when the RTD is formed using a GaAs-based material, the well layer is often replaced with GaAs and InGaAs, or the spacer layer is also configured with InGaAs. For example, see Patent Document 1.) This is to increase the energy difference ΔEc (Γ−X) between the InGaAs Γ point of the well layer and the AlAs X point of the barrier layer.
[0012]
[Patent Document 1]
JP 2002-1111012 (paragraph number [0021])
[0013]
[Problems to be solved by the invention]
However, when the well layer or the spacer layer is changed from GaAs to InGaAs, the lattice constants of GaAs and InGaAs do not match, so that the film thickness is a critical film thickness at which dislocation does not occur (for example, 25 nm to 50 nm with an In composition of 0.2). There was a problem that it was necessary to make it thin.
[0014]
Even when the well layer or the spacer layer is replaced with InGaAs, the energy difference ΔEc (Γ−X) between the InGaAs Γ point and the AlAs X point cannot actually be increased so much. Currently.
[0015]
FIG. 10 is a diagram showing an RTD energy band structure using InGaAs for the well layer, and FIG. 11 is a diagram showing an RTD energy band structure using InGaAs for the well layer and the spacer layer.
[0016]
First, when InGaAs is used for the well layer and the In composition ratio is 0.2, as shown in FIG. _0.2 Ga _0.8 The energy difference ΔEc (Γ−X) between the As Γ point and the AlAs X point increases by about 0.12 eV, and is about 0.32 eV in total. That is, even if the well layer is changed from GaAs to InGaAs, the energy difference ΔEc (Γ−X) between the Γ point of InGaAs and the X point of AlAs is not so large.
[0017]
In well ratio and spacer layer both have In composition ratio of 0.2 _0.2 Ga _0.8 When As is used, as shown in FIG. _0.2 Ga _0.8 The energy difference ΔEc (Γ−Γ) between the Γ point of As and the Γ point of AlAs increases to about 1.12 eV. But In _0.2 Ga _0.8 The energy difference ΔEc (Γ−X) between the Γ point of As and the X point of AlAs is about 0.32 eV in total as in the case shown in FIG.
[0018]
In order to further increase the energy difference ΔEc (Γ−X) between the Γ point of InGaAs used for the well layer or the spacer layer and the X point of AlAs, it is necessary to further increase the In composition of InGaAs. However, the increase in In composition further increases the deviation of the lattice constant, which makes it necessary to further reduce the critical film thickness, which makes crystal growth very difficult.
[0019]
Thus, further breakthrough is required for the formation of resonant tunneling elements such as RTD and RHET or the integration of these resonant tunneling elements and GaAs transistors.
[0020]
The present invention has been made in view of these points, and provides a resonant tunneling element such as RTD or RHET that suppresses a thermal excitation current and realizes a high P / V ratio, and a semiconductor integrated circuit using the resonant tunneling element. For the purpose.
[0021]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a resonant tunneling element that can be realized by the configuration example shown in FIG. The resonant tunnel element of the present invention includes a spacer layer made of a first semiconductor, a barrier layer that becomes a barrier against carriers in the spacer layer, and a well layer made of a second semiconductor sandwiched between the barrier layers. In the resonant tunneling device having a barrier structure including: the first semiconductor or the second semiconductor is Lattice matched to GaAs It is GaInNAs.
[0022]
As such a resonant tunneling element, the RTD 10 illustrated in FIG. 1 is realized. Double barrier structure 13 in RTD 10 is Ga _0.9 In _0.1 N _0.02 As _0.98 The well layer 13a, the first and second AlAs barrier layers 13b and 13c sandwiching the well layer 13 from both sides, and the first and second GaAs sandwiching the first and second AlAs barrier layers 13b and 13c from the outside. _0.9 In _0.1 N _0.02 As _0.98 It is composed of spacer layers 13d and 13e.
[0023]
Ga _0.9 In _0.1 N _0.02 As _0.98 Well layer 13a and first and second Ga _0.9 In _0.1 N _0.02 As _0.98 Ga used for the spacer layers 13d and 13e _0.9 In _0.1 N _0.02 As _0.98 Is lattice matched to GaAs. Further, the energy difference ΔEc (Γ−Γ) at the Γ point with GaAs is larger than the energy difference ΔEc (Γ−Γ) at the Γ point between InGaAs and GaAs, and the energy difference ΔEc (Γ with the X point in AlAs). -X) is also large. Therefore, in the first and second AlAs barrier layers 13b and 13c, the thermal excitation current flowing through the point X is suppressed.
[0024]
The present invention also provides a semiconductor integrated circuit using the resonant tunneling device having such a configuration. For well layers and spacer layers Lattice matched to GaAs By realizing a resonant tunneling element that can suppress thermal excitation current using GaInNAs, it is possible to integrate with a semiconductor device such as a GaAs transistor, and to form a semiconductor integrated circuit at low cost.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating an exemplary configuration of a main part of an RTD.
[0026]
The RTD 10 includes an n-GaAs contact layer 11 and a first n-Ga. _1-x In _x N _y As _1-y Graded layer 12, double barrier structure 13, second n-Ga _1-x In _x N _y As _1-y Graded layer 14, n ⁺ -In _x Ga _1-x The As contact layer 15 has a structure in which layers are sequentially stacked. n-GaAs contact layer 11 and n ⁺ -In _x Ga _1-x On the As contact layer 15, a lower electrode 16 and an upper electrode 17, which are ohmic electrodes in which Ti / Pt / Au or the like are laminated, are formed from each contact layer side. A passivation film 18 made of SiON or the like is formed on the exposed surface of each layer constituting the RTD 10.
[0027]
The RTD 10 double barrier structure 13 is made of Ga. _0.9 In _0.1 N _0.02 As _0.98 The well layer 13a, the first and second AlAs barrier layers 13b and 13c sandwiching the well layer 13 from both sides, and the first and second GaAs sandwiching the first and second AlAs barrier layers 13b and 13c from the outside. _0.9 In _0.1 N _0.02 As _0.98 It is composed of spacer layers 13d and 13e. The first and second AlAs barrier layers 13b and 13c are formed of the first and second GaAs. _0.9 In _0.1 N _0.02 As _0.98 It serves as a barrier against carriers in the spacer layer. This barrier layer is generally made of Al. _x Ga _1-x As (Al composition ratio x = 0 to 1) can be used.
[0028]
In this double barrier structure 13, Ga _0.9 In _0.1 N _0.02 As _0.98 The well layer 13a is 5 nm thick, the first and second AlAs barrier layers 13b and 13c are both 1.4 nm thick, and the first and second GaAs. _0.9 In _0.1 N _0.02 As _0.98 The spacer layers 13d and 13e are each formed with a film thickness of 20 nm.
[0029]
In such an RTD 10, the n-GaAs contact layer 11 has a film thickness of 100 nm and an impurity concentration of 5 × 10. ¹⁸ cm ^-3 It is formed with.
First and second n-Ga _1-x In _x N _y As _1-y Graded layers 12 and 14 both have a film thickness of 50 nm and an impurity concentration of 1 × 10. ¹⁸ cm ^-3 It is formed with. Here, the first n-Ga _1-x In _x N _y As _1-y The graded layer 12 is formed by gradually changing the In composition ratio x from 0 to 0.1 and the N composition ratio y from 0 to 0.02 from the lower side toward the upper side. . On the other hand, the second n-Ga _1-x In _x N _y As _1-y The graded layer 14 is formed by gradually changing the In composition ratio x from 0.1 to 0 and the N composition ratio y from 0.02 to 0 from the lower side toward the upper side. .
[0030]
n ⁺ -In _x Ga _1-x The As contact layer 15 has a film thickness of 100 nm and an impurity concentration of 1 × 10. ¹⁹ cm ^-3 It is formed with. This n ⁺ -In _x Ga _1-x The As contact layer 15 is formed by gradually changing the In composition ratio x from 0 to 0.7 from the lower side toward the upper side.
[0031]
For forming each layer of the RTD 10, for example, a metal organic vapor phase epitaxy (MOVPE) method can be used. In this case, triethylgallium, trimethylaluminum, trimethylindium, dimethylhydrazine, arsine, and disilane are used as raw materials.
[0032]
For example, Ga in the double barrier structure 13 _0.9 In _0.1 N _0.02 As _0.98 Well layer 13a and first and second Ga _0.9 In _0.1 N _0.02 As _0.98 The spacer layers 13d and 13e are formed using triethylgallium, trimethylindium, dimethylhydrazine, and arsine as raw materials. And each raw material made into a gaseous state is mixed so that it may become a predetermined composition ratio, the amount of introduction | transduction to a chamber is adjusted, 1st n-Ga _1-x In _x N _y As _1-y On the graded layer 12 or on the first and second AlAs barrier layers 13b and 13c, Ga _0.9 In _0.1 N _0.02 As _0.98 Form.
[0033]
In the formation of each layer, the n-GaAs contact layer 11 and n ⁺ -In _x Ga _1-x Formation of each layer other than the As contact layer 15 is performed under conditions where the substrate temperature is about 550 ° C. to about 700 ° C., preferably about 650 ° C. to about 700 ° C. This is because if the growth temperature is low, decomposition of the organic metal gas that is a raw material is difficult to occur, so that the crystal growth efficiency is lowered.If the growth temperature is high, crystallinity is deteriorated due to aggregation due to heat. To get.
[0034]
On the other hand, n-GaAs contact layer 11 and n ⁺ -In _x Ga _1-x The As contact layer 15 is formed under conditions where the substrate temperature is about 510 ° C. to about 520 ° C., preferably about 510 ° C. The temperature lower than the formation temperature of other layers (about 550 ° C. to about 700 ° C.) is set to 10 impurities such as Si. ¹⁹ This is because it is suitable for doping at a high concentration at a level and to prevent deterioration of crystallinity.
[0035]
After the formation of each layer, the RTD 10 formation region is patterned by photolithography, and H _Three PO _Four / H ₂ O ₂ A diode mesa is formed by system wet etching. Thereafter, a passivation film 18 such as SiON is formed on the surface of the diode mesa. Finally, a part of the passivation film 18 is removed by etching, and the lower electrode 16, n is formed on the surface of the n-GaAs contact layer 11. ⁺ -In _x Ga _1-x An upper electrode 17 is formed on the surface of the As contact layer 15 to form a main part of the RTD 10.
[0036]
In addition to the MOVPE method, each layer of the RTD 10 can be formed by a molecular beam epitaxy (MBE) method, a chemical beam epitaxy (CBE) method, or the like.
[0037]
Here, the double barrier structure 13 of the RTD 10 will be described in more detail with reference to FIGS. 2 and 3.
FIG. 2 is a diagram showing the relationship between the energy gap and the lattice constant of a compound semiconductor.
[0038]
A compound semiconductor changes its energy gap and lattice constant depending on its composition. In general, when N is added to a compound semiconductor, the lattice constant is decreased to change the energy gap, and In and Sb tend to increase the lattice constant to reduce the energy gap.
[0039]
For example, when N is added to GaAs, the lattice constant of GaNAs becomes smaller than that of GaAs. If In is added to compensate for this, the energy gap can be changed while lattice-matching GaInNAs to GaAs.
[0040]
GaInNAs has been reported as a material capable of making the energy gap smaller than that of GaAs within the range where the lattice constant coincides with GaAs by controlling its In composition and N composition ("M. Kondow et al.," Jpn. J. Appl. Phys. 35 (1996) 1273 ”).
[0041]
FIG. 3 is a diagram showing an example of the energy band structure in the double barrier structure.
Ga used for the well layer and the spacer layer in the double barrier structure 13 shown in FIG. _0.9 In _0.1 N _0.02 As _0.98 Takes a band offset that increases ΔEc with respect to GaAs.
[0042]
Ga lattice-matched with GaAs _0.9 In _0.1 N _0.02 As _0.98 Then, as shown in FIG. 3, the energy difference ΔEc (Γ−Γ) between the Γ point and the GaAs Γ point is about 0.45 eV. This value is the same as In or well layer or spacer layer. _0.2 Ga _0.8 When As is used, the energy difference ΔEc (Γ−Γ) between the Γ point and the GaAs Γ point is about 0.12 eV, which is very large.
[0043]
Therefore, Ga _0.9 In _0.1 N _0.02 As _0.98 The energy difference ΔEc (Γ−Γ) between the Γ point of AlAs and the Γ point of AlAs is about 1.45 eV, whereas the energy difference ΔEc (Γ−Γ) between the Γ point of GaAs and the Γ point of AlAs is about 1 eV. Becomes a larger value. Furthermore, since the energy difference ΔEc (Γ−X) between the Γ point of GaAs and the X point of AlAs is about 0.2 eV, Ga _0.9 In _0.1 N _0.02 As _0.98 The energy difference ΔEc (Γ−X) between the Γ point of AlAs and the X point of AlAs is about 0.65 eV.
[0044]
That is, in the double barrier structure 13 shown in FIG. _0.9 In _0.1 N _0.02 As _0.98 Well layer 13a or first and second Ga _0.9 In _0.1 N _0.02 As _0.98 The energy difference ΔEc (Γ−X) between the Γ point of the spacer layers 13d and 13e and the X point of the first and second AlAs barrier layers 13b and 13c is about 0.65 eV. This is In _0.2 Ga _0.8 The size of the conventional RTD having the double barrier structure of As / AlAs is about 0.32 eV, which is about twice as large. As a result, the thermal excitation current can be suppressed, and as a result, a large P / V ratio can be realized in the RTD 10.
[0045]
Furthermore, GaInNAs serving as a well layer or a spacer layer is lattice-matched with GaAs, unlike InGaAs, so that the film thickness is not limited during the formation. Further, when GaInNAs is used, since the well layer is usually formed with a very thin film thickness of about 5 nm, the In composition can be further increased without lattice matching with GaAs.
[0046]
When this GaInNAs is used for a well layer or a spacer layer, In _0.2 Ga _0.8 In order to obtain an energy difference ΔEc of about 0.12 eV that is an energy difference ΔEc (Γ−Γ) of Γ point with GaAs obtained when As is used, the lattice matching condition with GaAs is used. Therefore, it is necessary that at least the In composition is 3% and the N composition is 0.8%. That is, In _0.2 Ga _0.8 If the effect is to be improved as compared with the case where As is used, it is desirable that the GaInNAs is 3% or more of the In composition and 0.8% or more of the N composition.
[0047]
On the other hand, under the lattice matching conditions with GaAs, the energy difference ΔEc (Γ−Γ) between GaInNAs and InGaAs with 20% In composition and 7% N composition and GaAs point is Γ (Γ−Γ). −Γ) which is about 0.35 eV. Therefore, it is desirable that the GaInNAs to be used has an In composition of 20% or less and an N composition of 7% or less.
[0048]
In addition, when an AlGaAs barrier layer is formed instead of the AlAs barrier layer, the energy of the X point of AlGaAs coincides with the Γ point when the Al composition is around 0.5. _0.5 Ga _0.5 In the combination of the As barrier layer and the GaAs spacer layer, the energy difference ΔEc (Γ−Γ) at each Γ point is as small as about 0.4 eV. But Al _0.5 Ga _0.5 When a GaInNAs spacer layer is combined with the As barrier layer, the energy difference ΔEc (Γ−Γ) at each Γ point can be increased to about 0.85 eV.
[0049]
As described above, GaInNAs can be suitably used for the RTD 10, particularly the double barrier structure portion 13, and can form the RTD 10 that realizes a large P / V ratio by suppressing the thermal excitation current. This makes it possible to form an integrated circuit combined with a GaAs transistor having a high breakdown voltage at a low cost.
[0050]
In the above description, the case where GaInNAs is used for the RTD is described. However, it is also possible to form the RTD using GaNASSb or GaInNAsSb having a composition in which all or part of the In is replaced with Sb.
[0051]
As shown in FIG. 2, Sb has a tendency to increase the lattice constant and reduce the energy gap, as in In, and the tendency to increase the lattice constant is stronger than that of In. Therefore, N is added to GaAs, and Sb is added to compensate for the lattice constant of GaNAs, which is reduced by this. As a result, the energy gap of GANASSb can be changed while lattice-matching with GaAs. GaInNAsSb obtained by the simultaneous addition of In and Sb can lattice match with GaAs and contain N at a higher concentration. Thus, similarly to GaInNAs, GaNASSb and GaInNAsSb can increase the energy difference ΔEc (Γ−X) between the Γ point and the X point of AlAs.
[0052]
The configuration and formation method of the RTD when GaNAsSb or GaInNAsSb is used are the same as those of the RTD 10 using GaInNAs shown in FIG.
[0053]
For example, an RTD using GaNAsSb includes an n-GaAs contact layer, a first n-GaNAsSb graded layer, a double barrier structure, a second n-GaNAsSb graded layer, n ⁺ -In _x Ga _1-x The As contact layer has a structure in which layers are sequentially stacked. n-GaAs contact layer and n ⁺ -In _x Ga _1-x On the As contact layer, a lower electrode and an upper electrode are formed as ohmic electrodes, respectively, and a passivation film is formed on a surface exposed portion of each layer of the RTD.
[0054]
The RTD double barrier structure includes a GaNAsSb well layer (film thickness 5 nm), first and second AlAs barrier layers (film thickness 1.4 nm each) sandwiching the well layer from both sides, and the first and second layers. The first and second GaNASSb spacer layers (thickness 20 nm each) sandwiching the AlAs barrier layer from the outside. The first and second AlAs barrier layers serve as a barrier against carriers in the first and second GaNAsSb spacer layers, and the barrier layers generally include Al _x Ga _1-x As (Al composition ratio x = 0 to 1) can be used.
[0055]
The first and second n-GaNAsSb graded layers have a film thickness of 50 nm and an impurity concentration of 1 × 10. ¹⁸ cm ^-3 Formed with. n-GaAs contact layer and n ⁺ -In _x Ga _1-x The As contact layer can have the same structure as described in the description of FIG.
[0056]
The RTD having such a structure can be formed by MOVPE using triethylgallium, trimethylaluminum, trimethylindium, dimethylhydrazine, arsine, disilane as a raw material and trimethylantimony.
[0057]
In forming each layer, an n-GaAs contact layer and n ⁺ -In _x Ga _1-x Formation of each layer other than the As contact layer is performed under conditions where the substrate temperature is about 550 ° C. to about 700 ° C., preferably about 650 ° C. to about 700 ° C. This takes into account the decrease in crystal growth efficiency due to the low growth temperature and the deterioration of crystallinity due to the high growth temperature. On the other hand, the n-GaAs contact layer and n ⁺ -In _x Ga _1-x The As contact layer is formed under conditions where the substrate temperature is about 510 ° C. to about 520 ° C., preferably about 510 ° C. This is in consideration of high concentration doping of impurities and prevention of deterioration of crystallinity.
[0058]
After forming each layer, photolithography, H _Three PO _Four / H ₂ O ₂ A diode mesa is formed by system wet etching, and then an ohmic electrode and a passivation film are formed.
[0059]
The RTD formation using GaInNAsSb is similar to this, and In may be added during the formation.
In addition, in forming each layer of RTD using GaNASSb or GaInNAsSb, in addition to the MOVPE method, an MBE method, a CBE method, or the like can be used.
[0060]
Next, RHET, which is a resonant tunnel element having a double barrier structure similar to RTD, will be described.
FIG. 4 is a diagram illustrating a configuration example of a main part of the RHET.
[0061]
The RHET 20 includes n-GaAs contact layers 21 and 22, a GaAs barrier layer 23, and n-Ga. _1-x In _x N _y As _1-y Graded base layer 24, double barrier structure 25, n-Ga _1-x In _x N _y As _1-y Graded layer 26, n ⁺ -In _x Ga _1-x The As contact layer 27 has a stacked structure. n-GaAs contact layer 21, n-Ga _1-x In _x N _y As _1-y Graded base layer 24, n ⁺ -In _x Ga _1-x On the As contact layer 27, a collector electrode 28, a base electrode 29, and an emitter electrode 30 are formed as ohmic electrodes, respectively. A passivation film 31 is formed on the exposed surface of each layer of the RHET 20.
[0062]
The double barrier structure 25 of the RHET 20 is made of Ga _0.9 In _0.1 N _0.02 As _0.98 A well layer 25a, first and second AlAs barrier layers 25b and 25c sandwiching the well layer 25a from both sides, and first and second GaAs sandwiching the first and second AlAs barrier layers 25b and 25c from the outside. _0.9 In _0.1 N _0.02 As _0.98 It is composed of spacer layers 25d and 25e. The first and second AlAs barrier layers 25b and 25c are formed of the first and second Ga _0.9 In _0.1 N _0.02 As _0.98 It becomes a barrier against carriers in the spacer layers 25d and 25e, and the barrier layer is generally made of Al. _x Ga _1-x As (Al composition ratio x = 0 to 1) can be used.
[0063]
In this double barrier structure 25, Ga _0.9 In _0.1 N _0.02 As _0.98 The well layer 25a has a thickness of 5 nm, and the first and second AlAs barrier layers 25b and 25c both have a thickness of 1.4 nm. _0.9 In _0.1 N _0.02 As _0.98 The spacer layers 25d and 25e are each formed with a film thickness of 20 nm.
[0064]
The n-GaAs contact layers 21 and 22 have a film thickness of 100 nm and an impurity concentration of 5 × 10 5. ¹⁸ cm ^-3 It is formed with.
The GaAs barrier layer 23 is formed with a film thickness of 300 nm. The barrier layer is generally made of Al. _z Ga _1-z As (Al composition ratio z = 0 to 1) can be used. Furthermore, this barrier layer includes Ga _0.9 In _0.1 N _0.02 As _0.98 It is also possible to use GaInNAs having a smaller In composition and N composition than the spacer layer.
[0065]
n-Ga _1-x In _x N _y As _1-y The graded base layer 24 has a film thickness of 100 nm and an impurity concentration of 5 × 10. ¹⁸ cm ^-3 It is formed with. n-Ga _1-x In _x N _y As _1-y The graded base layer 24 is formed by gradually changing the In composition ratio x from 0 to 0.1 and the N composition ratio y from 0 to 0.02 from the lower side to the upper side. Yes.
[0066]
n-Ga _1-x In _x N _y As _1-y The graded layer 26 has a film thickness of 50 nm and an impurity concentration of 1 × 10. ¹⁸ cm ^-3 It is formed with. n-Ga _1-x In _x N _y As _1-y The graded layer 26 is formed by gradually changing the In composition ratio x from 0.1 to 0 and the N composition ratio y from 0.02 to 0 from the lower side toward the upper side. .
[0067]
n ⁺ -In _x Ga _1-x The As contact layer 27 has a film thickness of 100 nm and an impurity concentration of 1 × 10. ¹⁹ cm ^-3 It is formed with. n ⁺ -In _x Ga _1-x The As contact layer 27 is formed by gradually changing the In composition ratio x from 0 to 0.7 from the lower side toward the upper side.
[0068]
Such RHET 20 is formed by MOVPE using triethylgallium, trimethylaluminum, trimethylindium, dimethylhydrazine, arsine, and disilane as raw materials.
[0069]
In the formation of each layer, n-GaAs contact layers 21, 22 and n ⁺ -In _x Ga _1-x Formation of each layer other than the As contact layer 27 is performed under conditions where the substrate temperature is about 550 ° C. to about 700 ° C., preferably about 650 ° C. to about 700 ° C. This takes into account the decrease in crystal growth efficiency due to the low growth temperature and the deterioration of crystallinity due to the high growth temperature. On the other hand, n-GaAs contact layers 21, 22 and n ⁺ -In _x Ga _1-x The As contact layer 27 is formed at a substrate temperature of about 510 ° C. to about 520 ° C., preferably about 510 ° C. This is in consideration of high concentration doping of impurities and prevention of deterioration of crystallinity.
[0070]
After the formation of each layer, first, patterning is performed by photolithography, and n-Ga. _1-x In _x N _y As _1-y H to graded base layer 24 surface _Three PO _Four / H ₂ O ₂ System wet etching is performed to form an emitter mesa. Further, patterning is performed by photolithography, and the surface of the n-GaAs contact layer 21 is H. _Three PO _Four / H ₂ O ₂ System wet etching is performed to form a base mesa. Thereafter, a passivation film 18 such as SiON is formed on the surface of the diode mesa. Finally, a part of the passivation film 18 is removed by etching, and the collector electrode 28 and n-Ga are formed on the n-GaAs contact layer 21. _1-x In _x N _y As _1-y On the graded base layer 24, a base electrode 29, n ⁺ -In _x Ga _1-x Emitter electrodes 30 are formed on the As contact layer 27, and the main part of the RHET 20 is formed.
[0071]
In this way, the double barrier structure 25 of RHET 20 has Ga _0.9 In _0.1 N _0.02 As _0.98 Can be used to form RHET having a high P / V ratio.
In addition, formation of each layer of RHET20 can also use MBE method, CBE method, etc. other than MOVPE method.
[0072]
Next, a semiconductor integrated circuit in which the RTD is integrated with a semiconductor device such as a GaAs transistor will be described.
FIG. 5 is a diagram illustrating a configuration example of a part of a semiconductor integrated circuit including an RTD and a HEMT.
[0073]
The semiconductor integrated circuit 40 has an RTD 50 and a HEMT 70 formed on a GaAs substrate 41.
In the RTD 50, the GaAs buffer layer 51, In _0.2 Ga _0.8 As channel layer 52, n-Al _0.3 Ga _0.7 As electron supply layer 53, In _0.49 Ga _0.51 A P etch stopper layer 54 is sequentially laminated. Furthermore, in RTD50, this In _0.49 Ga _0.51 On the P etch stopper layer 54, an n-GaAs contact layer 55, a first n-Ga. _1-x In _x N _y As _1-y Graded layer 56, double barrier structure 57, second n-Ga _1-x In _x N _y As _1-y Graded layer 58, n ⁺ -In _x Ga _1-x As contact layers 59 are sequentially stacked. n-GaAs contact layer 55 and n ⁺ -In _x Ga _1-x On the As contact layer 59, a lower electrode 60 and an upper electrode 61 are formed as ohmic electrodes, respectively. A passivation film 62 is formed on the exposed surface of each layer of the RTD 50.
[0074]
The RTD 50 double barrier structure 57 is made of Ga. _0.9 In _0.1 N _0.02 As _0.98 The well layer 57a, the first and second AlAs barrier layers 57b and 57c sandwiching the well from both sides, and the first and second GaAs sandwiching the first and second AlAs barrier layers 57b and 57c from the outside. _0.9 In _0.1 N _0.02 As _0.98 The spacer layers 57d and 57e are configured. The first and second AlAs barrier layers 57b and 57c are formed of the first and second GaAs. _0.9 In _0.1 N _0.02 As _0.98 It becomes a barrier against the carriers in the spacer layers 57d and 57e, and this barrier layer is generally made of Al. _x Ga _1-x As (Al composition ratio x = 0 to 1) can be used.
[0075]
In the HEMT 70, a GaAs buffer layer 51, In _0.2 Ga _0.8 As channel layer 52, n-Al _0.3 Ga _0.7 As electron supply layer 53, In _0.49 Ga _0.51 A P etch stopper layer 54 is sequentially laminated. Furthermore, in HEMT70, this In _0.49 Ga _0.51 An n-GaAs contact layer 55 is separately formed on the P etch stopper layer 54, and a gate electrode 71 is formed therebetween. A source electrode 72 and a drain electrode 73 are formed on the n-GaAs contact layer 55 formed separately. A passivation film 62 is formed on the exposed surface of each layer of the HEMT 70 and the surface of the gate electrode 71.
[0076]
The semiconductor integrated circuit 40 including the RTD 50 and the HEMT 70 is formed by MOVPE using phosphine in addition to triethylgallium, trimethylaluminum, trimethylindium, dimethylhydrazine, arsine, and disilane as raw materials.
[0077]
Here, the GaAs buffer layer 51 in the RTD 50 and the HEMT 70 is formed on the GaAs substrate 41 with a film thickness of 300 nm. In _0.2 Ga _0.8 The As channel layer 52 is formed on the GaAs buffer layer 51 with a film thickness of 15 nm. n-Al _0.3 Ga _0.7 The As electron supply layer 53 has a film thickness of 20 nm and an impurity concentration of 2 × 10. ¹⁸ cm ^-3 Formed of In _0.49 Ga _0.51 The P etch stopper layer 54 is formed with a film thickness of 6 nm. The n-GaAs contact layer 55 has a film thickness of 50 nm and an impurity concentration of 5 × 10. ¹⁸ cm ^-3 Formed with.
[0078]
In the double barrier structure 57 of the RTD 50, Ga _0.9 In _0.1 N _0.02 As _0.98 The well layer 57a has a thickness of 5 nm, the first and second AlAs barrier layers 57b and 57c have a thickness of 1.4 nm, and the first and second GaAs. _0.9 In _0.1 N _0.02 As _0.98 The spacer layers 57d and 57e are each formed with a film thickness of 20 nm.
[0079]
Further, the first n-Ga in the RTD 50 _1-x In _x N _y As _1-y The graded layer 56 has a film thickness of 50 nm and an impurity concentration of 5 × 10. ¹⁸ cm ^-3 Formed with. First n-Ga _1-x In _x N _y As _1-y The graded layer 56 is formed by gradually changing the In composition ratio x from 0 to 0.1 and the N composition ratio y from 0 to 0.02 from the lower side toward the upper side.
[0080]
Second n-Ga _1-x In _x N _y As _1-y The graded layer 58 has a film thickness of 50 nm and an impurity concentration of 1 × 10. ¹⁸ cm ^-3 Formed with. Second n-Ga _1-x In _x N _y As _1-y The graded layer 58 is formed by gradually changing the In composition ratio x from 0.1 to 0 and the N composition ratio y from 0.02 to 0 from the lower side toward the upper side.
[0081]
n ⁺ -In _x Ga _1-x The As contact layer 59 has a thickness of 100 nm and an impurity concentration of 1 × 10. ¹⁹ cm ^-3 Formed with. n ⁺ -In _x Ga _1-x The As contact layer 59 is formed by gradually changing the In composition ratio x from 0 to 0.7 from the lower side toward the upper side.
[0082]
In forming each layer of the RTD 50 and the HEMT 70, n ⁺ -In _x Ga _1-x Formation of each layer other than the As contact layer 59 is performed under conditions where the substrate temperature is about 550 ° C. to about 700 ° C., preferably about 650 ° C. to about 700 ° C. This takes into account the decrease in crystal growth efficiency due to the low growth temperature and the deterioration of crystallinity due to the high growth temperature. On the other hand, n ⁺ -In _x Ga _1-x The As contact layer 59 is formed at a substrate temperature of about 510 ° C. to about 520 ° C., preferably about 510 ° C. This is in consideration of high concentration doping of impurities and prevention of deterioration of crystallinity.
[0083]
After the formation of each layer, patterning is performed by photolithography, and the surface of the n-GaAs contact layer 55 is H. _Three PO _Four / H ₂ O ₂ System wet etching is performed to form a diode mesa. Furthermore, since the RTD 50 side and the HEMT 70 side are isolated, part of the surface of the GaAs substrate 41 is also H _Three PO _Four / H ₂ O ₂ System wet etching is performed. In the case of a GaAs-based device, this isolation can be performed by oxygen implantation instead of etching.
[0084]
Next, on the n-GaAs contact layer 55 on the RTD 50 side, n ⁺ -In _x Ga _1-x A lower electrode 60 and an upper electrode 61 are formed on the As contact layer 59, and a source electrode 72 and a drain electrode 73 are formed on the n-GaAs contact layer 55 on the HEMT 70 side.
[0085]
After the formation of these electrodes, electron beam lithography and H _Three PO _Four / H ₂ O ₂ The n-GaAs contact layer 55 on the HEMT 70 side is separated by system wet etching to form a gate recess. In this wet etching, In _0.49 Ga _0.51 The P etch stopper layer 54 functions as an etching stopper.
[0086]
Next, a gate electrode 71 having a gate length of 0.1 μm is formed by electron beam lithography and vapor deposition lift-off. For a gate length of 0.1 μm, f _t Is around 100 GHz. Thereafter, the surface is passivated with an insulating film such as SiON, and then a semiconductor integrated circuit 40 in which the RTD 50 and the HEMT 70 are combined is formed by a wiring process. As a result, a return zero DFF circuit operable at 40 Gbps can be realized.
[0087]
Further, it is possible to form a semiconductor integrated circuit by forming an HBT instead of the HEMT 70. In addition to the MOVPE method, the semiconductor integrated circuit 40 can be formed by MBE method, CBE method, or the like.
[0088]
In the above description, a resonant tunneling element having a double barrier structure and a semiconductor integrated circuit using the same have been described. However, the present invention can of course be applied to a triple barrier structure having two well layers. it can.
[0089]
【The invention's effect】
As described above, in the present invention, in a resonant tunneling device having a barrier structure having a spacer layer, a barrier layer, and a well layer, the spacer layer or the well layer is formed using GaInNAs. Thereby, the thermal excitation current which flows through a barrier layer is suppressed, and P / V ratio can be improved.
[0090]
Furthermore, by forming an RTD that realizes a large P / V ratio, a semiconductor integrated circuit combined with a GaAs transistor having a high breakdown voltage can be formed at low cost.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of a main part of an RTD.
FIG. 2 is a diagram showing a relationship between an energy gap and a lattice constant of a compound semiconductor.
FIG. 3 is a diagram showing an example of an energy band structure in a double barrier structure.
FIG. 4 is a diagram illustrating a configuration example of a main part of an RHET.
FIG. 5 is a diagram illustrating a configuration example of a part of a semiconductor integrated circuit including an RTD and a HEMT.
FIG. 6 is a diagram illustrating a circuit configuration example of MOBILE.
FIG. 7 is a diagram showing current-voltage characteristics in an RTD and HEMT parallel element;
FIG. 8 is a load curve diagram of MOBILE, where (a) is greater than I (RTD2 + HEMT) than I (RTD1), and (b) is greater than I (RTD2 + HEMT) than I (RTD1). The small case is shown.
FIG. 9 is a diagram showing an example of an energy band structure of a GaAs / AlAs RTD.
FIG. 10 is a diagram showing an energy band structure of an RTD using InGaAs for a well layer.
FIG. 11 is a diagram showing an energy band structure of RTD using InGaAs for a well layer and a spacer layer.
[Explanation of symbols]
10,50 RTD
11, 21, 22, 55 n-GaAs contact layer
12, 56 1st n-Ga _1-x In _x N _y As _1-y Graded layer
13, 25, 57 Double barrier structure
13a, 25a, 57a Ga _0.9 In _0.1 N _0.02 As _0.98 Well layer
13b, 25b, 57b First AlAs barrier layer
13c, 25c, 57c Second AlAs barrier layer
13d, 25d, 57d First Ga _0.9 In _0.1 N _0.02 As _0.98 Spacer layer
13e, 25e, 57e Second Ga _0.9 In _0.1 N _0.02 As _0.98 Spacer layer
14, 58 Second n-Ga _1-x In _x N _y As _1-y Graded layer
15, 27, 59 n ⁺ -In _x Ga _1-x As contact layer
16, 60 Lower electrode
17, 61 Upper electrode
18, 31, 62 Passivation film
20 RHET
23,51 GaAs barrier layer
24 n-Ga _1-x In _x N _y As _1-y Graded base layer
26 n-Ga _1-x In _x N _y As _1-y Graded layer
28 Collector electrode
29 Base electrode
30 Emitter electrode
40 Semiconductor integrated circuit
41 GaAs substrate
52 In _0.2 Ga _0.8 As channel layer
53 n-Al _0.3 Ga _0.7 As electron supply layer
54 In _0.49 Ga _0.51 P etch stopper layer
71 Gate electrode
72 Source electrode
73 Drain electrode

Claims (5)

A resonance having a barrier structure having a spacer layer made of a first semiconductor, a barrier layer that becomes a barrier against carriers in the spacer layer, and a well layer made of a second semiconductor sandwiched between the barrier layers. In the tunnel element,
The resonant tunneling element, wherein the first semiconductor or the second semiconductor is GaInNAs lattice-matched to GaAs .   2. The resonant tunneling element according to claim 1, wherein the GaInNAs is lattice-matched to GaAs, has an In composition of 3% to 20%, and an N composition of 0.8% to 7%. The resonant tunneling device according to claim 1, wherein the barrier layer is made of Al _x Ga _1-x As and the Al composition ratio x is changed from 0 to 1. A resonance having a barrier structure having a spacer layer made of a first semiconductor, a barrier layer that becomes a barrier against carriers in the spacer layer, and a well layer made of a second semiconductor sandwiched between the barrier layers. In a semiconductor integrated circuit using a tunnel element,
A semiconductor integrated circuit using a resonant tunneling element, wherein the first semiconductor or the second semiconductor is GaInNAs lattice-matched to GaAs . A resonance having a barrier structure having a spacer layer made of a first semiconductor, a barrier layer that becomes a barrier against carriers in the spacer layer, and a well layer made of a second semiconductor sandwiched between the barrier layers. In the tunnel element,
The resonant tunneling device, wherein the first semiconductor or the second semiconductor is GaNASSb lattice-matched to GaAs or GaInNAsSb lattice-matched to GaAs .

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