JP3200142B2 - Field-effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter referred to as an FET) suitable as an amplifying element for transmitting and receiving satellite broadcasts and an element for high-speed data transfer.
Abbreviated).

[0002]

2. Description of the Related Art As a high-frequency device in the GHz band typified by an amplifying device for transmitting and receiving satellite broadcasts, a GaAs-MESFET (Meta-FET) using an epitaxial layer of GaAs on a GaAs substrate as an electron transit layer.
l Semiconductor FET) or FET using a two-dimensional electron layer that accumulates at the heterostructure interface between GaAs and AlGaAs, so-called HEMT
(High Electron Mobility Transistor: GaAs-HEM
Write T. JP-A-56-94780) is widely known. The reason why the GaAs device is fast is that the electron mobility of GaAs is about 8,000 cm ^{2 in the} undoped state (intrinsic state).
/ V · sec, which is several times (5 to 6 times) the value of Si.

However, in the GaAs-MESFET, the electron transit layer must be doped with impurities, and the electron mobility is reduced to about 4,000 cm ² / V · sec due to scattering of conduction electrons by the impurities. To solve this problem, GaAs-HEM
In T, the effect of impurity scattering is reduced by using a heterojunction of heterogeneous semiconductors with different band gaps to separate the impurity-doped electron supply layer and electron transit layer. Has been realized.

Japanese Patent Application Laid-Open No. 59-53714 describes the relationship between the impurity concentration and the film thickness of the electron supply layer of a GaAs-HEMT.
There are USP No.4,424,525 and USP No.Re.33,584.

In the HEMT structure, in general, it is difficult to form an ohmic electrode due to the low impurity concentration of the electron transit layer, and the controllability of electron mobility is poor. In order to compensate for this drawback, a GaAs-FET in which impurities are doped in both an electron supply layer and an electron transit layer forming a heterojunction has been proposed (Japanese Patent Application Laid-Open No. Sho 61/1986).
-54673).

For the purpose of increasing the concentration of two-dimensional electron gas, there has been proposed a GaAs semiconductor heterojunction device in which an impurity doping region is extended to a region including a heterojunction (Japanese Patent Laid-Open No. 61-276267). ).

Further, a double hetero-type GaAs-FET in which both the upper surface and the lower surface of the n-type electron transit layer have a wider gap and are in contact with an electron supply layer made of a compound semiconductor doped with impurities has been proposed. (Japanese Patent Laid-Open No. 61-1
No. 31565).

Further, USP defines that both an electron supply layer and an electron transit layer below a source and a drain of a GaAs-FET using the above heterojunction contain impurities.
No.4,424,525.

However, due to these elements, more than ten GHz
To obtain an element that can transmit and receive radio waves in the band, 0.2 μm
FETs with extremely short gate lengths of less than m are required. In order to form a gate electrode having such a length, optical lithography may be used, but a high level of technology is required, and stable production is not easy.

In practice, electron beam lithography is often used, but is more difficult than optical lithography in terms of industrial mass production. In addition, the GaAs-MESFET and GaAs-HEMT
In order to realize such a GaAs-FET, it is necessary to further reduce the gate length. However, due to the miniaturization of the gate length,
If an attempt is made to increase the frequency of the device, new technology development and advanced process technology that are not industrially feasible are required.
For this reason, miniaturization technology is easy, mass production is possible, and
There is a need for a high-frequency device having a new structure that can support a higher frequency band than ever before.

For such a purpose, it has been proposed to use an InGaAs thin film having an electron mobility higher than that of GaAs for an electron transit layer of a FET (Japanese Patent Application Laid-Open No. 63-272080). In this proposal, an n-type InGaAs layer is used as an electron transit layer, and an upper surface and a lower surface thereof form a double hetero junction in contact with the GaAs layer. The GaAs layer shows a prototype example in which both are doped, and a non-doped prototype example in both cases. The substrate is Ga
As substrate is used. In this proposal, the InGaAs layer
Because it is in direct contact with the GaAs layer, the In
The ratio of the number of atoms must be small due to the requirement of lattice matching. In the prototype example proposed above, it is suppressed to 20%, and the thickness of the InGaAs layer is as thin as 150 mm. With such a low In ratio, the improvement in mobility over GaAs is not very large.

Further, research has been conducted on using a high-quality thin film of InAs having an overwhelmingly high electron mobility and saturation speed as compared with GaAs as an electron transit layer of a FET.

The high electron mobility and saturation velocity of InAs
FETs with longer gate lengths than GaAs-FETs
It has the possibility of transmitting and receiving radio waves of the same high frequency. However, these conventional InAs-FET attempts have the following problems.

(1) The substrate used is expensive and is not suitable as an industrial material.

(2) The structure is complicated, and there are difficulties in reliability and manufacturing process.

(3) Due to the difference in lattice constant between the InAs layer and the semiconductor layer in contact with the InAs layer, defects are likely to occur.

(4) When stacking an InAs layer on a semiconductor layer having a different lattice constant, there is a limit to the thickness of the InAs layer that can be stacked without causing defects. This limit of film thickness,
That is, since the critical film thickness is small, an InAs layer having a film thickness required in the design of the FET cannot be obtained.

(5) Due to a large difference in lattice constant between the InAs layer and the semiconductor layer in contact with the InAs layer, strong stress is applied to the InAs layer, which causes problems such as thermal instability and large changes with time. Yes, lacks reliability.

(6) Due to the large parasitic capacitance between the substrate and the InAs layer, it is difficult to expect a sufficient function as a high-frequency element.

(7) Since a part of the material is very easily oxidized, the production method is extremely complicated and has a problem in reliability.

(8) InAs has a small band gap energy, and a non-ohmic junction such as an appropriate Schottky junction or a pn junction cannot be obtained.

For example, Japanese Patent Application Laid-Open No.
There is a proposal described in JP-A-5439. InAs substrates are expensive and difficult for industrial purposes.At room temperature, an insulating substrate cannot be obtained.Therefore, there is a parasitic capacitance between the InAs substrate and the electron transit layer to obtain good high-speed characteristics. It becomes an obstacle.

On the other hand, on a substrate having a significantly different lattice constant,
Some have an InAs thin film formed directly. For example,
No. 2-229438 discloses molecular beam epitaxy (M
A buffer layer of GaAs is formed using the BE (Molecular Beam Epitaxy) method, and an In transmissive layer is directly formed on the buffer layer.
A double hetero-type InAs-FET in which an As layer is formed and a GaAs layer is further formed thereon is disclosed. In this structure,
Since the InAs layer is formed on a GaAs substrate having a remarkably different lattice constant, the thickness of the InAs layer that can provide a high-quality InAs thin film is 20 μm.
The degree is limited to below. This becomes an obstacle in designing an element having a high current driving capability, severely restricts the degree of freedom in design, and has many practical problems.

As one method of alleviating the lattice mismatch between the GaAs substrate and the InAs substrate, Japanese Patent Application Laid-Open No.
We propose an InAs-FET using a stacked layer of AlSb and AlSb as a buffer layer. GaSb has a small lattice constant deviation from InAs, which is about 0.6%. However, in order to form an FET having an InAs layer as an electron transit layer, forming an InAs thin film directly on GaSb requires the upper end of the valence band of the GaSb layer 102 as shown in FIG. This is higher than the lower end of the conduction band of the InAs layer 103, which is not preferable. Therefore, as shown in FIG.
Forming an AlSb layer 104 on the GaSb layer 102 as a current barrier layer for electrically insulating the GaSb layer 102 and the InAs layer 103;
An InAs layer 103 is formed thereon. However, this structure not only complicates the buffer layer, but also, as shown in FIG. 1C, the parasitic capacitance using the AlSb layer 104 as a dielectric film and the GaSb layer 102 and the InAs layer 103 sandwiching it as electrodes. Is formed, which is not preferable as a structure of a high-speed device.
Further, since the AlSb layer 104 has a lattice constant different from that of the InAs layer 103 by 1.25%, the critical thickness of the InAs thin film 103 on the AlSb film 104 is
This is 200 mm or less, which is also a constraint in obtaining a device driven at a high current. The fact that the AlSb film 104 has the property of being easily oxidized also causes the process to be complicated when the active layer region is formed by the mesa etching method and the like, and there is a possibility that the element characteristics may change with time due to oxidation. Poor. Further, this proposal does not disclose an antioxidant method.

As one method of alleviating the lattice mismatch between the GaAs substrate and the InAs substrate, an InAs layer formed on a buffer layer composed of a laminated film of AlSb and Al _0.5 Ga _0.5 Sb is used as an electron transit layer. InAs-FET (IEEE ELECTRON DEVICE LETTER
S, Vol.11, No.11, NOVEMBER, 1990). FIG.
1 shows a structural diagram of an As-FET. Al _0.5 Ga _0.5 Sb has a lattice constant deviation from InAs of about 0.9% and a critical film thickness of 300 ° or less. For this reason, there is a limitation in obtaining an element driven at a high current. In addition, in this example, a 2.8 μm AlSb layer was
Used as a buffer layer between the Al _0.5 Ga _0.5 Sb layer and
In order to increase the carrier concentration of the electron transit layer, a complicated laminated structure in which a 60-degree AlSb layer is inserted between the Al _0.5 Ga _0.5 Sb layers is used. These carriers may also come from donors in the unintentionally doped AlSb or from the AlSb layer.
It is supplied from the interface with the InAs layer to the electron transit layer, and it is difficult to control the concentration according to the design value in the manufacturing process of this FET. Therefore, this is problematic in terms of industrial mass productivity and is not practical. Fig. 2 (b)
The following shows the current-voltage characteristics of the InAs-FET manufactured by the above method. Although pinch-off characteristics are observed, the linearity in the saturation region is poor and the gate length is as large as 1.7 μm, but the impact ionization effect is remarkable and practicality is poor.

The InAs layer is made of AlGaAs almost lattice-matched thereto.
An InAs-FET having a structure sandwiched by Sb layers has been proposed (JP-A-60-144979). In this proposal, an InGaAs multilayer structure in which the composition ratio and lattice constant change stepwise is arranged as a buffer layer on a semi-insulating InP substrate. The InGaAs multilayer structure is based on the InP lattice constant of the substrate.
It is designed to change little by little with each step up to the lattice constant of. On this, a laminated film having a structure in which an InAs layer is sandwiched by an AlGaAsSb layer is formed. The AlGaAsSb layer is used as a barrier layer for confining conduction electrons in the InAs layer. The structure of the InAs-FET obtained in this way is extremely complicated and is not preferable in manufacturing. In addition, the uppermost InGaAs layer of the InGaAs multilayer film forming the buffer layer is:
It has characteristics very close to InAs, and its band gap is close to that of InAs, and it is a conductor at room temperature. For this reason,
A parasitic capacitance is formed using the AlGaAsSb layer as a dielectric film and the InAs layer of the electron transit layer and the InGaAs layer of the buffer layer as electrodes, and good high-frequency characteristics cannot be obtained. In addition, the gate electrode and InAs
If the layer is in direct contact, it will make ohmic contact,
In the case where the active region is formed by the mesa separation method, it is necessary to devise a structure to avoid this contact, but there is no disclosure of such a structure. Further, since the AlGaAsSb film has a characteristic of being easily oxidized when the Ga component is small, the AlGaAsSb film is formed in a case where the active layer region is formed by the mesa etching method or in a structure where the AlGaAsSb film on the InAs film is exposed. Although measures to prevent oxidation of the film are essential, this proposal does not disclose an antioxidant method.

[0027]

As described above, there have been attempts to utilize InAs having a high electron mobility as an electron transit layer of an FET, but no FET structure suitable for practical use has been found.

An object of the present invention is to provide an FET having excellent high frequency characteristics as an amplifying element for transmitting and receiving satellite broadcasts and an element for high-speed data transfer.

[0029]

In order to achieve the above object, an FET according to the present invention comprises a first compound semiconductor layer functioning as a buffer layer and an electron transit layer on a semiconductor substrate having a lattice constant different from InAs. And an InAs layer functioning as a layer.

[0030]

In the present invention, In used as an electron transit layer is used.
As has much higher electron mobility and saturation velocity than GaAs, which is usually used as an electron transit layer of a high-frequency FET. In addition, its temperature dependence is moderately small, and it was expected as a material for next-generation high-speed devices exceeding GaAs-FETs. In particular, from a practical point of view, InAs
A technique for forming a high-quality crystal thin film has been desired.

Since a lattice constant of GaAs or Si substrate is significantly different from that of InAs, when an InAs layer is formed on these substrates, several atomic layers exceed the critical thickness and lattice defects occur. Therefore, in order to obtain a high-quality InAs thin film, it is necessary to form an insulating buffer layer between the substrate and the InAs thin film. It is a matter of course that the buffer layer should be substantially lattice-matched to InAs and have a smooth surface with few defects, but it is thermally stable from the viewpoint of the manufacturing method and reliability.
It is desirable to have a simple structure with little change over time, and it is also desirable to have a structure that protects the substrate leakage current, has a small parasitic capacitance, and is insulating.

The present invention is based on the discovery of a semiconductor layer having a simple structure which satisfies the conditions as a material for such a buffer layer, and based on the finding that an InAs layer formed on this buffer layer is used as an active layer. New FET that realizes a high-frequency FET on a substrate with a different lattice constant from the InAs layer
The structure is presented.

The first compound semiconductor layer is substantially lattice-matched with InAs and has a band gap larger than that of AlGaAs.
It is formed by selecting from Sb, AlGaPSb, AlInAsSb, or AlInPSb, and has a simple configuration.

The reason why the structure of the buffer layer could be simplified was that Al
It is because the fact that the first compound semiconductor layer such as the GaAsSb layer absorbs the influence of the lattice mismatch between the substrate and the InAs layer with only several tens of atomic layers and forms a smooth plane.
As a result, it was possible to form a high-quality InAs thin film with few lattice defects on a GaAs or Si substrate which is a general-purpose substrate. In addition, the critical thickness of the InAs layer is large enough to obtain the required film thickness for the FET design, the stress applied to the interface of the InAs layer is small, the thermal stability is stable, and the change with time is small. A high degree of element can be obtained and InAs
The parasitic capacitance between the layer and the substrate was small, and excellent characteristics as a high-frequency element were obtained. Although some of the materials are easily oxidized, the oxidation was prevented by the side walls of the mesa structure and the protective film. For Schottky bonding, etc.
By using several devices to make this easier, a FET with excellent high-frequency characteristics was realized.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present inventors, on an insulating substrate that is not lattice-matched with InAs, have substantially lattice-matched with InAs, and
We have studied a new structure of InAs-FET with a buffer layer that absorbs the lattice mismatch between layers. As a result, a structure in which AlGaAsSb, which is a compound semiconductor that is substantially lattice-matched to InAs and has a larger band gap than InAs, is formed on a substrate that does not lattice-match with InAs, and an InAs layer is formed on top of it. Was found. In this structure, the lattice mismatch between the substrate and InAs is alleviated in the AlGaAsSb layer of only several tens of atomic layers, and not only a high-quality InAs layer can be obtained, but also the substrate and the AlGas layer.
The lattice distortion near the interface of the AsSb layer was small, and it was found that the parasitic capacitance was small when the FET was manufactured. It has also been found that there are some other compound semiconductors that exhibit similar effects. These compound semiconductors are
A buffer layer for relaxing lattice mismatch between the InAs layers, an InAs layer is formed on the buffer layer,
By forming a compound semiconductor layer substantially lattice-matched with the InAs layer on the InAs layer, an InAs-FET having excellent characteristics which could not be realized until now was realized.

Embodiment 1 An embodiment of a field effect transistor according to the present invention will be described below with reference to FIG. In FIG. 3, 1 indicates a substrate, 2 indicates a first compound semiconductor layer, 3 indicates an InAs layer, and 4 indicates a second compound semiconductor layer. 5 and 7 are a pair of ohmic electrodes, 5 is a source electrode, and 7 is a drain electrode. Reference numeral 6 denotes a gate electrode provided between the source electrode 5 and the drain electrode 7. Hereinafter, each component will be described.

Substrate 1 The substrate 1 used in the present invention may be any substrate having a lattice constant different from that of InAs, such as a GaAs substrate or a GaP substrate, a Si substrate on which monocrystalline GaAs is grown on the surface, A sapphire substrate or the like is suitable. Above all, a GaAs substrate from which a semi-insulating and high-quality single crystal substrate can be obtained is particularly preferable. Here, the semi-insulating property means a substance having a resistivity of 10 ⁷ Ω · cm or more. When a single crystal substrate is used, the plane orientation of the substrate is preferably (100), (111), (110), or the like. A plane orientation shifted from 1 to 5 degrees from these plane orientations may be used.
Among them, the (100) plane is most suitable for growing a good quality thin film. Flatten the substrate surface as usual,
For the purpose of cleaning, a substrate obtained by growing a semiconductor of the same material as the substrate may be used as the substrate of the present invention. Growing GaAs on a GaAs substrate is one of the most typical examples. The present invention is superior to the conventional method when a substrate having a different lattice constant from InAs is used.
As a substrate having a lattice constant different from As by 3.5% or more, GaAs
There are many substrates, such as a substrate and a Si substrate, which are desirable from the viewpoint of crystal purity, flatness, substrate cost, and the like.

First Compound Semiconductor Layer 2 The first compound semiconductor layer 2 is (a) substantially lattice-matched with the InAs layer, and (b) directly connected to a substrate of GaAs or the like having a large lattice constant different from that of the InAs layer 3. Even when stacked, it has a smooth surface with few defects, and (c) a compound semiconductor with few crystal defects causing parasitic capacitance near the interface with the substrate; and (d) InAs
At the interface with the layer 3, it is preferable to form a barrier for preventing a substrate leakage current.

FIG. 4 shows how the electron mobility of the 300-degree InAs layer 3 stacked on the AlGaAsSb layer 2 formed directly on the GaAs substrate 1 using MBE varies with the thickness of the MBE layer. Indicated by For comparison, the white circles indicate the electron mobility of a 300-nm InAs layer formed on an AlSb layer provided directly on a GaAs substrate. The 300-nm InAs layer on the AlSb layer has already exceeded the critical film thickness, and the electron mobility has deteriorated.
The electron mobility of the InAs layer 3 formed on the AlGaAsSb layer 2 is
A high value is obtained when the thickness of the AlGaAsSb layer 2 is 0.1 μm or more, and a considerably high value is already obtained even at 300 °. The result and RHEED (REFLECTION HIGH ENERGY ELECTRON DIFF
RACTION) and X-ray analysis, etc.
m or more, the AlGaAsSb layer 2 not only has an extremely smooth surface, but also has good quality with few defects in most of the film except for a region at a distance of about 100 ° from the interface with the GaAs substrate 1. It was found to have crystallinity. AlGaPS
b, AlInAsSb and AlInPSb also have similar properties.

These four types of compound semiconductors, Al _x1 Ga _1-x1
As _y1 Sb _1-y1 , Al _x2 In _1-x2 As _y2 Sb _1-y2 , Al _x3 In _1-x3 P _y3 Sb
_1-y3 and _{Al x4 Ga 1-x4 P y4} Sb 1-y4 , any by choosing the component ratio can satisfy these conditions. The range of the composition ratio is determined by the following three different methods.

I. First Method The first method is determined so as to satisfy the following two conditions.

(1A) The lattice constant of the first compound semiconductor layer 2 matches the InAs lattice constant of the InAs layer 3 within 0.6%, and (2) the first compound semiconductor layer 2 has a lattice constant of 1 eV or more. , And forms a potential barrier necessary for confining the conduction electrons of the InAs layer 3 in the InAs layer 3.

There is no compound semiconductor other than InAs in the III-V group binary system that has a lattice matching within 0.6% with InAs. However, in order for the InAs layer 3 laminated on the first compound semiconductor 2 to have an appropriate critical thickness and to form a thin film with less stress that causes thermal stability and aging, 0.6 % Lattice matching is considered necessary.
FIG. 5 is a phase diagram of a III-V quaternary compound semiconductor satisfying this condition.

In the phase diagram shown in FIG. 5, Al _x1 Ga _1-x1 As _y1
Sb _{1 -y 1} is represented by a point in a rectangular area D 1 obtained by connecting four points of AlAs, AlSb, GaSb, and GaAs. In this region D1, the value of x1 changes from 0 to 1 in proportion to the distance from the line L1 connecting the points of GaAs and GaSb, and takes 1 on the line L2 connecting the points of AlAs and AlSb. The value of y1 is a straight line connecting AlSb and GaSb
AlAs and Ga change from 0 to 1 in proportion to the distance from L3.
It becomes 1 on the straight line L4 connecting As. The dashed line and the dashed line in the figure show the contour line of the band gap and the contour line of the lattice constant of the compound semiconductor having the composition and composition ratio represented by each point, respectively.

FIG. 5 shows a region including Al _x1 Ga _{1-x1 Asy1} Sb _1-y1 which satisfies the conditions (1A) and (2) by a rectangle R1 drawn by a solid line. This area is ｛0.21 ≦ x1 ≦ 1.0
, 0.02 ≦ y1 ≦ 0.22 °. Similarly, Al _x2 In _1-x2 As _y2 Sb _1-y2 , Al _x3 satisfying the conditions of (1A) and (2)
In _1-x3 P _y3 Sb _1-y3 , and a rectangular region including Al _x4 Ga _1-x4 P _y4 Sb _1-y4 , respectively, ｛0.34 ≦ x2 ≦ 1.0, 0.09 ≦ y2 ≦
0.79}, {0.07 ≦ x3 ≦ 1.0, 0.06 ≦ y3 ≦ 0.72}, and {0.13 ≦ x4 ≦ 1.0, 0.13 ≦ y4 ≦ 0.18}. More strictly, the ranges of the composition ratios of the four types of compound semiconductors satisfying the conditions of (1A) and (2) are {0.21 ≦ x1 ≦ 1.0, 0.09x1 ≦ y1 ≦ 0.07x1 + 0.15}, {0.34 ≤x2≤1.0, -0.82x2 + 0.91≤y2≤-0.87x2 + 1.09｝, ｛0.07≤x3≤1.0, -0.57x3 + 0.63≤y3≤-0.58x3 + 0.76｝, and ｛0.13≤x4≤1.0, 0.06x4 ≦ y4 ≦ 0.06x4 + 0.12}.

II. Second Method As a range in which a better quality InAs layer 3 can be obtained, the second method is determined so as to satisfy the following two conditions. (1B) The lattice constant of the first compound semiconductor layer 2 matches the InAs lattice constant of the InAs layer 3 within 0.4%, and (2) the first compound semiconductor layer 2 has a band gap of 1 eV or more. And InAs layer 3
Is formed in the InAs layer 3 to form a potential barrier necessary for confining the conduction electrons in the InAs layer 3.

The ranges of the composition ratios of the four types of compound semiconductors satisfying the conditions (1B) and (2) are defined as follows based on FIG.

Al _x1 Ga _1-x1 As _y1 Sb _1-y1 is {0.21 ≦ x1 ≦ 1.0, 0.08x1 + 0.03 ≦ y1 ≦ 0.08x1 + 0.12}, Al _x2 In _1-x2 As _y2 Sb _1-y2 is , ｛0.34 ≦ x2 ≦ 1.0, -0.83x2 + 0.94 ≦ y2 ≦ -0.86x2 + 1.06｝, Alx3In1-x3Py3Sb1-y3, ｛0.07 ≦ x3 ≦ 1.0, -0.57x3 + 0.65 ≦ y3 ≦ -0.58x3 + 0.74 ｝, And Al _x4 Ga _1-x4 P _y4 Sb _1-y4 are {0.13 ≦ x4 ≦ 1.0, 0.06x4 + 0.02 ≦ y4 ≦ 0.06x4 + 0.10}.

III. Third Method The third method is determined so as to satisfy the following two conditions.

(1C) The critical thickness of the InAs layer 3 formed on the first compound semiconductor layer 2 is such that the mutual conductance of the FET using the InAs layer 3 as an electron transit layer is maximized.
(2) The potential barrier necessary for confining the conduction electrons of the InAs layer 3 in the InAs layer 3 because the first compound semiconductor layer 2 has a band gap of 1 eV or more. To form

FIG. 6 shows the lattice constant of the AlGaAsSb layer 2 as InAs.
An outline of the relationship between the degree of lattice mismatch and the critical film thickness with respect to the lattice constant of FIG. AlGaPSb, InGaAsSb and InGaPS
b shows almost the same characteristics.

As shown in FIG. 6, the highest degree of lattice matching is required when the thickest electron transit layer is required. A preferred upper limit is defined as the film thickness at which the transconductance of the FET is maximized.

[0053] magnitude of the transconductance of the FET, the mobility μ in the bias condition whose value is maximum is substantially proportional to the product [mu] N _D a of thickness a donor concentration N _D and the electron transit layer. Therefore, in order to obtain a large FET transconductance is large structures of the product [mu] N _D a is desired. A voltage is applied vertically to the electron transit layer 3, and the potential difference between the upper surface and the lower surface of the electron transit layer 3 required to deplete the electron transit layer 3 is calculated.
If V _off, the voltage V _off increases with donor concentration N _D and the thickness a. In the FET, the value of the voltage V _off is preferably set to about 1 of the source-drain breakdown voltage V _B of the electron transit layer 3.

FIG. 7 is a graph showing an outline of the dependence of the product μN _D a on the film thickness a. Product μ at each film thickness a
The value of N _D a, such that the voltage V _off becomes about 1/4 breakdown voltage V _B, defines the donor concentration N _D, given in consideration of the N _D dependence of breakdown voltage V _B and the mobility μ I have. Product [mu] N _D a, the value of the thickness a is a maximum value in the vicinity of 2,000 Å, is changed to decreasing function from increasing function of a in this respect. Therefore, it is understood that the thickness of the InAs layer 3 may be 2,000 mm or less in a practical device.
FIG. 6 shows that the transconductance is about 80% of the maximum value when the thickness is about 400 Å.

From FIG. 5, the following conditions are obtained.

(3) InAs electron transit layer 3 with a critical film thickness of 2,000 mm
In order to realize the above, it is necessary to determine the component ratio of the AlGaAsSb layer 2 such that the deviation of its lattice constant from the lattice constant of InAs is within 0.2%.

The InAs electron transit layer 3 having a critical thickness of 400 400
It can be seen that in order to realize the above, the component ratio of the AlGaAsSb layer 2 needs to be determined so that the deviation of its lattice constant from the lattice constant of InAs is within 0.6%. Al
Similar results are obtained when GaPSb, InGaAsSb, and InGaPSb are used as the first compound semiconductor layer 2.

In order to realize a FET having a higher transconductance, the first compound semiconductor layer 2 not only satisfies the conditions (1C) and (2) but also satisfies the condition (3).
Can be determined based on the phase diagram of FIG.
The results are as follows.

Al _x1 Ga _1-x1 As _y1 Sb _1-y1 is {0.21 ≦ x1 ≦ 1.0, 0.08x1 + 0.05 ≦ y1 ≦ 0.08x1 + 0.10}, Al _x2 In _1-x2 As _y2 Sb _1-y2 is , ｛0.34 ≦ x2 ≦ 1.0, -0.84x2 + 0.97 ≦ y2 ≦ -0.85x2 + 1.03｝, Alx3In1-x3Py3Sb1-y3, ｛0.07 ≦ x3 ≦ 1.0, -0.57x3 + 0.67 ≦ y3 ≦ -0.58x3 + 0.72 ｝, And Al _x4 Ga _1-x4 P _y4 Sb _1-y4 are {0.13 ≦ x4 ≦ 1.0, 0.06x4 + 0.04 ≦ y4 ≦ 0.06x4 + 0.08}.

Among these four types of compound semiconductors, AlGaAsSb, Al, which is easy to control the composition and easy to obtain a good quality thin film,
InAsSb is preferred. In particular, when AlGaAsSb was used as the first compound semiconductor layer 2, the FET characteristics were the best.

The first compound semiconductor layer 2 may have conductivity even if it is not doped with impurities. in this case,
In order to cancel the effect of the carrier contributing to the electric conduction, an impurity having a polarity opposite to that of the carrier contributing to the electric conduction may be doped. The thickness of the first compound semiconductor layer 2 may be freely selected, but due to manufacturing restrictions,
0.05 to 3.0 μm is a preferable range. More preferably, 0.1 to 2.0 μm, even more preferably 0.1 to 1.0 μm
It is.

InAs Layer 3 The InAs layer 3 which is the electron transit layer of the present invention has a thickness of 0.2 μm for the purpose of controlling electric conduction by a voltage applied to the control electrode.
m or less is preferred. Although the InAs layer 3 may be non-doped, a sufficiently high electron mobility can be obtained even if an impurity is doped, so that the impurity can be doped if necessary. The donor impurity to be doped may be anything that acts as a donor atom in InAs.
S, Sn, Se, and Te are particularly preferred impurities. The amount of the impurity to be doped may be 5 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ¹⁸ / cm ³ , but a preferable range is 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / c
m ³ , more preferably 2 × 10 ¹⁷ / cm ³ to 8 × 10 ¹⁷ / cm ³
It is. The position where the impurity is doped may be uniform in the thickness direction of the InAs layer 3. However, if the impurity is doped only in the center of the film while avoiding the vicinity of the interface with the other compound semiconductor layers 2 and 4, the first compound semiconductor layer This is preferable because scattering of conduction electrons at the interface with the second and second compound semiconductor layers 4 can be reduced. Also, InAs
In may be replaced with Ga if it is within 9% of the total number of In atoms. Within this range, the difference in lattice constant between the InAs layer 3 and InAs is 0.6% or less, and the first compound semiconductor 2 and the second compound semiconductor 4 are substantially lattice-matched. For this reason, FE can be obtained without significantly impairing the characteristics of InAs.
The withstand voltage of T can be increased. Also, the lattice constants of the first compound semiconductor layer 2 and the second compound semiconductor layer 4 are
If the lattice constant of InAs in the InAs layer 3 is within 0.4%, the amount of Ga to be replaced with In is set to 6% or less, and deterioration of the characteristics of the InAs layer 3 due to lattice mismatch and change with time are reduced. it can. Further, when the lattice mismatch is set to 0.2% in order to achieve higher lattice matching, if the amount of Ga replacing In is set to 3% or less, the characteristic deterioration of the InAs layer 3 due to the lattice mismatch can be further reduced. .

Second compound semiconductor layer 4 Second compound semiconductor layer 4 formed on InAs layer 3
Is substantially lattice-matched with InAs, and
In order to form a barrier suitable for being confined in the layer at the interface with the InAs layer 3, one having a larger band gap than the InAs layer 3 is preferable. Further, the electron affinity of the second compound semiconductor layer 4 is smaller than the electron affinity of the InAs layer 3, and the sum of the electron affinity and the band gap is smaller than the sum of the electron affinity and the band gap of the InAs layer 3. It is preferable that the thickness be large without impairing the characteristics of the InAs layer 3. These requests are common to the requests for the first compound semiconductor layer 2.

Further, in the FET using the Schottky junction, it is necessary that the second compound semiconductor layer 4 and the gate electrode 6 form a good Schottky junction. on the other hand,
MI using the second compound semiconductor layer 4 as an insulating barrier layer
In the S-type FET, the second compound semiconductor layer 4 is desirably made of a material that becomes a good insulating film. Any compound semiconductor that satisfies these requirements may be used. Among them, Al _x1 Ga _{1-x1 Asy1} Sb _1-y1 , which is used as the first compound semiconductor layer 2,
Al _x2 In _1-x2 As _y2 Sb _1-y2 , Al _x3 In _1-x3 P _y3 Sb _1-y3 , Al _x4 Ga
_{1- x4Py4Sb1 -y4} is particularly preferred. The component ratio is determined in the same manner as in the first compound semiconductor layer 2. AlGaAsSb and AlInAsSb, from which high quality thin films are easily obtained, are particularly good. Second
The thickness of the compound semiconductor layer 4 is preferably 50Å to 1,000 、,
After the formation of the gate electrode 6, the second compound semiconductor layer 4 only needs to have a range in which conduction electrons do not exist.

When the second compound semiconductor layer 4 is doped with a donor impurity to form an electron supply layer to the InAs layer 3, the donor impurity to be doped is not limited as long as it acts as a donor atom. Se, S, Si and Sn are particularly preferred impurities. The amount of impurities to be doped is 5 × 10 ¹⁶
/ cm ^{3 to} 5 × 10 ¹⁸ / cm ³ , but the preferred range is 1
× 10 ¹⁷ / cm ^{3 to} 5 × 10 ¹⁸ / cm ³ . The doping position may be uniform in the thickness direction or may be distributed. In particular, a structure in which the impurity is not doped only in the vicinity of the interface on the side where the gate electrode 6 is formed is favorable without lowering the gate breakdown voltage. The second compound semiconductor layer 4 in the vicinity of the interface with the InAs layer 3 has a structure in which impurities are not doped, so that scattering of conduction electrons in the InAs layer 3 due to impurities can be reduced, and the operating speed of the FET can be reduced. It is preferable in increasing the value.

Further, the second compound semiconductor layer 4 is not limited to the above-mentioned compound semiconductors composed of Group III and Group V elements, but may be a compound semiconductor composed of Group II and Group VI elements.

When the first compound semiconductor layer 2 and the second compound semiconductor layer 4 are formed from compound semiconductors having the same composition,
Although preferable because the manufacturing process can be simplified, different compositions,
Alternatively, a structure in which compound semiconductors having the same composition and different composition ratios may be combined may be used as appropriate.

Source electrode 5 and drain electrode 7 Source electrode 5 and drain electrode 7
It is necessary to form an ohmic junction with the As layer 3. Although the ohmic junction has various structures, in the embodiment of FIG.
The electrode is in direct contact with the As layer 3.

The InAs layer 3 has a narrow band gap, and an ohmic junction with low contact resistance can be obtained only by contacting the electrodes. Therefore, the electrode can be directly formed on the InAs layer 3 by etching the second compound semiconductor layer 4 only under the ohmic electrodes 5 and 6. In this case, an alloying step may be performed to reduce the contact resistance between the electrodes 5, 7 and the InAs layer 3, but a good ohmic junction can be obtained only by vapor deposition. For this reason, the electrode metal is AuGe
A known laminated electrode structure including a three-layer structure of / Ni / Au may be used, or a single-layer metal such as Al, Ti, Au, and W may be used, and an extremely large number of combinations are possible.

Gate Electrode 6 The gate electrode 6 shown in FIG. 3 may be any as long as a depletion layer can be formed underneath. In addition to a method using a Schottky junction, an insulating layer is provided between the gate electrode 6 and the InAs layer 3. Pinched things
An MIS (METAL-INSULATOR-SEMICONDUCTOR) structure or a pn junction can also be used. In particular, as a material for forming a Schottky junction with a semiconductor such as the second compound semiconductor 4, Al, Ti, W, Pt, WSi, Au, or the like is preferable, and a material having a stacked structure thereof may be used.

The basic layer structure of the FET of the present invention has been described above. The electron mobility of the InAs layer 3 does not decrease so much even when impurities are doped, and the InAs layer 3 has a higher electron mobility than GaAs, InGaAs or the like. Therefore, depending on the combination of the doping of the donor impurity of the InAs layer 3 and the second compound semiconductor layer 4,
Transistors with different characteristics are possible. These will be described as modified examples 1-3 of the above embodiment.

Modification Example 1 In the first type, as shown in FIG. 8 , the second compound semiconductor layer 4 is used as an insulating barrier layer without being doped with a donor impurity. 1 is this first modification.
It belongs to

In this case, the InAs layer 3 need not be doped with a donor impurity, but may be doped with a donor impurity as long as the characteristics of the InAs layer 3 are not deteriorated. This FE
In T, since the gate electrode 6 is formed on the second compound semiconductor layer 4 having a low impurity concentration, a gate electrode having a high gate breakdown voltage and good rectification can be formed.
In addition, while intrinsic conduction electrons thermally excited in the InAs layer 3 are around 10 ¹⁵ / cm ³ to 10 ¹⁶ / cm ³ near room temperature,
The conduction electrons generated from the donor impurities are 10 ¹⁷ / cm ³ to 10 ¹⁸
/ cm ³ and high concentration. For this reason, the FET has a small variation in the FET characteristics with respect to a change in the ambient temperature of the FET.

[0074]

[0075]

[0076]

[0077]

Modification 4 The second compound semiconductor layer 4 is non-doped. When the thickness of the InAs layer 3 is such that a quantum level is formed, the energy level 30 of the conduction electrons in the InAs layer 3 is quantized as shown in the band diagram of FIG. A level is formed. For this reason, even if the use environment temperature of the element fluctuates, the fluctuation of the resistance value of the InAs layer 3 is reduced, and an FET having excellent temperature characteristics can be realized as compared with an FET that does not form a quantum level.

Further, since the conduction electrons flowing in the InAs layer 3 are hardly scattered, the transistor is suitable for high-speed operation. Moreover, while the InAs layer 3 having a narrow band gap is used as the electron transit layer, the effect of the discrete quantum level has substantially the same effect as an increase in the band gap. Therefore, the withstand voltage of the transistor can be increased.

In order to obtain such characteristics, the thickness of the InAs layer 3 is preferably set to 400 ° or less. In particular, 200 Å
In the following, the effect by the quantum level becomes more remarkable.

InAs as the material of the quantum well is GaAs, Si
Since the effective mass of electrons is smaller than that of the above, a quantum level is easily formed even if the width of the quantum well is wide. The lattice constant of the compound semiconductor is usually 5 to 6 °, but at the stage of thin film growth,
Even if a surface step of about one atomic layer may occur, the influence of the step can be suppressed to a small size because the thickness of the quantum well is large. Further, in InAs, since the width of the quantum well can be widened, a large conductance can be obtained while using the quantum well as an electron transit layer. Prototype Example 4 belongs to Modification Example 4 and is an example of a quantum effect type FET in which the InAs layer 3 has a thickness of 100 °.

Next, the source electrode 5 and the drain electrode 7
A modified example will be described.

Modification 5 As shown in FIG. 10, the source electrode 5 and the drain electrode 7 are formed through the second compound semiconductor layer 4 on the InAs
A structure that makes ohmic contact with the As layer 3 may be used. This structure is formed by the following method. That is, the electrodes 5,
In order to obtain an ohmic contact between the InAs layer 7 and the InAs layer 3, alloying annealing is performed to diffuse the electrode material to form the heavily doped regions 54 and 74, or Donor impurities are ion-implanted only in the lower regions 54 and 74 to lower the contact resistance.

Modification 6 As shown in FIG. 11, the source electrode 5 and the drain electrode 7
In order to form an ohmic contact with lower contact resistance between the InAs layer 3 and the InAs layer 3, there is a technique of forming contact layers 50 and 70.

The contact layers 50 and 70 are preferably made of GaAs, GaAsSb, InGaAs, InAs, InSb or the like doped with a donor impurity, and the thickness may be 500 Å or less, but is preferably 100 300 to 300 Å.
Is particularly preferred. The donor impurities doped in the contact layers 50 and 70 may be anything as long as they act as donor atoms in the contact layers, but may be Si, S, Sn, Se,
Te is a particularly good impurity. The amount of impurities to be doped varies depending on the material of the contact layers 50 and 70,
× 10 ¹⁷ / cm ³ to 10 ¹⁹ / cm ³ is a preferable range.

Next, a modification of the gate electrode 6 will be described.

Modification Example 7 When a high melting point metal such as W or WSi is used as the material of the gate electrode 6, as shown in FIG.
Donor impurities are ion-implanted into the regions 55 and 75 excluding the lower portion of the gate electrode 6, so that the peripheral regions 55 and 75 of the gate electrode 6 can have a self-aligned structure in which the resistance is reduced. With this structure, the parasitic resistance between the source electrode 5 and the gate electrode 6 and between the gate electrode 6 and the drain electrode 7 can be reduced. Further, the variation in the parasitic resistance can be extremely suppressed.

The impurity to be ion-implanted may be any impurity as long as it is a donor impurity in the second compound semiconductor layer 4 and the InAs layer 3. Particularly, S, Se, Sn, Si and the like are preferable. The concentration of the impurity to be implanted is 3 × 10 ¹⁷ / cm ³ to 1 × 10
¹⁹ / cm ³ is a preferred range.

The gate electrode 6, as shown in FIG.
May be formed directly on the compound semiconductor layer 4, or on another layer formed on the second compound semiconductor layer 4.

Modification 8 As shown in FIG. 13, the InA is formed below the gate electrode 6 following the second compound semiconductor layer 4 without being exposed to the air.
A gate electrode lower conductive layer 61 made of a semiconductor having a narrow band gap such as s or InSb is formed. In this structure,
There is no oxide film at the interface between the gate electrode lower conductive layer 61 and the second compound semiconductor layer 4, and an ideal interface with few interface states can be obtained. On the other hand, the gate electrode 6 and the gate electrode lower conductive layer 61
To form an ohmic junction with the gate electrode lower conductive layer 61
The barrier between the gate electrode 6 and the second compound semiconductor layer 4 is equivalent to a Schottky junction between the gate electrode 6 and the second compound semiconductor layer 4.

Modification 9 As shown in FIG. 14, at the place where the second compound semiconductor layer 4 is joined to the gate electrode 6, the second compound semiconductor layer 4
When the recess structure 12 is formed on the substrate, the withstand voltage of the FET can be increased. The recess structure 12 is not limited to the case where the gate electrode 6 is arranged in contact with the second compound semiconductor layer 4, but may be formed in another layer where the gate electrode 6 is arranged.

Modification with Insertion Layer, Protective Film, etc. Modification 10 In the FET of the present invention, the first compound semiconductor layer 2 is directly laminated on the substrate 1 and the InAs layer 3 is formed thereon. Even with a simple structure, a high-quality InAs layer 3 can be formed. However,
In the FET according to the present invention, it is possible to improve the characteristics of the FET by inserting another semiconductor layer between the respective layers. Fig. 15
Various insertion layers will be described using the example shown in FIG.

The FET shown in FIG.
And a second semiconductor insertion layer 21 between the first compound semiconductor layer 2 and the InAs layer 3.
22 and a third semiconductor insertion layer 41 between the InAs layer 3 and the second compound semiconductor layer 4. By incorporating these semiconductor insertion layers, hole current can be reduced and the conductance of the transistor can be improved.

The second and third semiconductor insertion layers 22 and 41 are
In order to more efficiently confine conduction electrons in the InAs layer 3, it is disposed in contact with the InAs layer 3 which is an electron transit layer. For this reason, it is selected from semiconductors having a band gap wider than InAs, and the electron affinity of the semiconductor used for the semiconductor insertion layers 22 and 41 is smaller than the electron affinity of the InAs layer 3 and the difference between the electron affinity and the band gap. A semiconductor layer whose sum is larger than the sum of the electron affinity and the band gap of the InAs layer 3 is preferable. Among them, AlSb, AlGaSb, and InAlAs are particularly suitable.

The inserted semiconductor layers 21, 22 and 41 are:
Since the lattice constant of InAs layer 3 is different from that of InAs, if the thickness is larger than a specific thickness, dislocation due to lattice mismatch occurs. Therefore, the characteristics of the InAs layer 3 may be deteriorated.
Therefore, the thickness of the semiconductor insertion layers 21, 22, and 41 is preferably a thickness that does not cause dislocation due to such lattice mismatch, that is, a range of the critical thickness. The critical film thickness varies depending on the material of the semiconductor to be inserted. In the case of AlSb, the critical film thickness is about 160 ° in combination with the InAs layer 3.

Further, as shown in FIG. 15B, an insulator layer 62 may be formed in contact with the lower part of the gate electrode 6.

Modification 11 In the present invention, the first compound semiconductor layer 2 and the second
The semiconductor used as the compound semiconductor layer 4 is GaAs or
It is easier to oxidize than semiconductors such as InAs. In order to reduce such a change in FET characteristics with time due to oxidation of the compound semiconductor layer, it is preferable to form a layer for preventing oxidation separately from a passivation layer used in a normal semiconductor device.

First, when a fourth semiconductor insertion layer 42 as shown in FIG. 15 (a) is formed on the second compound semiconductor layer 4, the second compound semiconductor layer 4 comes into contact with the atmosphere. Because of the protection, the problem of characteristic deterioration due to oxidation hardly occurs. The fourth semiconductor insertion layer 42 may be any semiconductor that does not easily oxidize, but GaAs, GaSb, and GaAsSb are particularly preferable. The appropriate thickness is 50 to 1,000 mm. In particular, 100Å-700Å
Is the optimal thickness.

Modification 12 In the FET, the current between the source and the drain is controlled by the voltage applied to the gate electrode 6. For this reason, it is necessary to separate the InAs layer 3 into an electrically inactive region and an active region 11 to be an electron transit layer of the FET. As the separation method, there are a method of forming a mesa structure and a method of making the area other than the active region 11 nonconductive.

When the active region 11 is formed by the mesa structure, etching with a liquid or etching with a gas based on an acid or an alkali is used.

On the other hand, the second compound semiconductor layer 4 and In
When the As layer 3 is made nonconductive, a normal method such as ion implantation or electron beam irradiation is used. Unlike the mesa structure, the structure in which the unnecessary portion is made nonconductive has no cross section, so that problems such as gate leak and oxidation hardly occur.

In the mesa structure, that is, a structure in which an unnecessary portion is removed by etching and only a necessary portion is left in a plateau shape, the following inconvenience may occur. That is,
The surfaces of the first compound semiconductor 2 and the second compound semiconductor layer 4 that are exposed to the air may be oxidized, which may lead to deterioration of transistor characteristics. In addition, the InAs layer 3 exposed in the cross section of the mesa structure forms an ohmic junction only by contacting with the gate electrode 6, so that a leak current from the gate electrode 6 to the InAs layer 3 may occur.

The side wall 9 shown in FIG. 16B is for preventing such inconvenience. The side wall 9 is formed of an insulating or semi-insulating material so that the InAs layer 3 and the gate electrode 6 do not come into direct contact. Thereby, a leak current from the gate electrode 6 to the InAs layer 3 can be prevented. In addition, since the cross section of the mesa structure is covered, the first compound semiconductor layer 2 and the second compound semiconductor layer 4 are covered.
Can also be prevented from being oxidized.

FIG. 16A is a plan view of the FET, and FIG.
16A is a cross-sectional view taken along the line AB, and FIG. 16C is a cross-sectional view taken along the CD line in FIG. These figures show a state in which the side wall 9 is formed so as to cover the cross section of the mesa structure, and the InAs layer 3 and the gate electrode 6 are not in direct contact.

The material of the side wall 9 is SiN _x , Si which is usually used as an insulating semiconductor or a semiconductor protective film.
O ₂ , SiO _X N _y , Al ₂ O _{3 and the} like are preferable. Among them, SiN _X , SiO _X N _y
Is particularly preferred.

Modification 13 FIG. 17 shows the result of oxidation of the first and second compound semiconductor layers.
This is an example in which a first protective film 81 and a second protective film 82 are provided on the surface of the element in order to reduce the deterioration of the characteristics of the FET.
The first protective film 81 is formed on the upper surface of the first compound semiconductor layer 2,
In the area where the active region 11 is not formed, SiN _x , Si
It was formed using an insulator such as O ₂ and Al ₂ O ₃ . The second protective film 82 was formed on the upper surface of the second compound semiconductor layer 4 in the active region 11 or on the upper surface of the fourth semiconductor insertion layer 42 except for the electrodes 5, 6, and 7. First protective film
The 81 and the second protective film 82 may be formed of the same film, but may be formed separately. The first protective film 81 and the second
The protective film 82 and the side wall 9 can be formed by removing the same insulating film by anisotropic etching using reactive ion etching. Therefore, there is an advantage that the process is easy.

Other General Application Structures A large number of FETs of the present invention can be integrated on the same substrate. Alternatively, the transistor and the transistor in which the substrate and the electron transit layer are formed of the same semiconductor material may be formed on the same substrate. In particular, the InAs-F of the present invention characterized by high-speed operation
A structure in which ET and a GaAs-FET formed on the same substrate are integrated is preferable.

[Trial Production Example 1] A trial production example of an FET using the second compound semiconductor layer 4 shown in FIG. 8 as a barrier layer of an insulating layer will be described.

A mirror-polished (100) plane semi-insulating GaAs substrate having a thickness of 350 μm was used as the substrate 1. On the substrate 1, a non-doped Al _0.8 Ga _0.2 As _0.14 Sb _0.86 layer lattice-matched to InAs as a first compound semiconductor layer 2 was doped at 8,000 ° and Si as a donor impurity was doped at 2 × 10 ¹⁷ / cm ³ . 700 nm of the InAs layer 3 and then a second compound semiconductor layer 4
Non-doped Al _0.8 Ga _0.2 As _0.14 Sb _0.86 layers were sequentially formed by molecular beam epitaxy at 400 μm. next,
Unnecessary portions of the laminated thin film formed on the GaAs substrate 1 were removed by photolithography to form a resist pattern for manufacturing an electron transit portion of the device. Then H ₂ SO
₄ : Etching was performed with an H ₂ O ₂ based etchant to form an active region 11 having a mesa structure. Next, after forming a resist pattern, the AlGaAsSb under the source electrode 5 and the drain electrode 7 is etched with an NH ₄ OH: H ₂ O ₂ etching solution.
Only the layer 4 was etched to expose the surface of the InAs layer 3. Subsequently, an AuGe (Au: Ge = 88: 12) layer 5 is formed by a vacuum evaporation method.
1,71 for 2,000 mm, Ni layers 52, 72 for 500 mm, Au layers 53, 73
3,500 Å continuous evaporation. Then lift off, 3 layers 5
A pattern of source electrode 5 and drain electrode 7 composed of 1, 52, 53 and 71, 72, 73 was formed, and an ohmic junction with the InAs layer 3 was obtained. Further, after forming a resist pattern for the gate electrode 6, 3,000 Al of Al was deposited on the entire surface of the wafer, and lift-off was performed to form the gate electrode 6. Then, dicing was performed to separate the individual elements. Thus, the FET of the present invention shown in FIG. 8A was manufactured. The device was packaged with leads through a normal assembly process.

[0110]

[0111]

[0112]

[Trial Example 4] In the FET of the present invention shown in FIG. 3, an example of a quantum effect type FET in which the InAs layer 3 has a thickness of 100 mm and a quantum level is formed in the InAs layer 3 will be described. I do. In
The As layer 3 is doped with Si as a donor impurity.

A mirror-polished (100) plane semi-insulating GaAs substrate having a thickness of 350 μm was used as a substrate 1, and a first
As the compound semiconductor layer 2, a non-doped Al _0.8 Ga _0.2 As _0.14 Sb _0.86 layer lattice-matched to InAs is 8,000 mm, and an InAs layer 3 doped with 2 × 10 ¹⁷ / cm ³ Si as a donor impurity is 10
Next, a non-doped Al _0.8 Ga _0.2 As _0.14 Sb _0.16 layer was formed as the second compound semiconductor layer 4 at 400 そ れ ぞ れ by a molecular beam epitaxy method. Below, prototype example 1
A quantum effect type FET as shown in FIG.

[Trial Production Example 5] A trial production example of the FET having the structure shown in FIG. 18 will be described. In this prototype example, the second compound semiconductor layer 4 and the InAs layer 3 are non-doped.
It is . GaAs is used as the fourth semiconductor insertion layer 42.
Sb is formed.

A non-doped Al _0.7 Ga _0.3 As _0.15 lattice-matched to InAs was formed as a first compound semiconductor layer 2 on a mirror-polished (100) plane semi-insulating GaAs substrate 1 having a thickness of 350 μm.
An Sb _0.85 layer is formed to 8,000 Å, followed by a 200 をnon-doped InAs layer 3 and a non-doped 500 Al Al _0.7 Ga _0.3 As _0.15 Sb as the second compound semiconductor layer 4.
_0.85 layers were sequentially formed by the molecular beam epitaxy method. Finally, as a fourth semiconductor insertion layer 42, a GaAs _0.15 Sb _0.85 layer not doped with impurities was formed to a thickness of 200 nm. Next, unnecessary portions of the laminated thin film formed on the GaAs substrate were removed by photolithography, and a resist pattern for manufacturing the active region 11 was formed. Then H ₃ PO
₄ : Etching was performed with an H ₂ O ₂ based etchant to form an active region 11 having a mesa structure. Next, after 3,000 Å of SiN was formed by the plasma CVD method, portions other than the side wall 9 were removed by etching using a reactive ion etching apparatus. Next, after forming a resist pattern for the ohmic electrode, an NH ₄ OH: H ₂ O ₂ based etchant is used.
GaAsSb under the source electrode 5 and the drain electrode 7 (fourth
Only the semiconductor insertion layer 42) and AlGaAsSb (second compound semiconductor layer 4) were etched to expose the surface of the InAs layer 3. Furthermore, by vacuum evaporation, 1,500 を of Ti and 2,500Å of Au
Continuous vapor deposition. Next, lift-off is performed, and the source electrode 5,
The drain electrode 7 was formed. Further, a resist pattern of the gate electrode 6 is formed, and GaAsSb, which is the fourth semiconductor insertion layer 42, is etched with an NH4OH: H2O2 type etching solution. did. Then, dicing,
Separated into individual elements. Thus, the FET shown in FIG. 18 was manufactured.

[Trial Production Example 6] Another trial production example of the present invention shown in FIG. 19 will be described. In this prototype, the second compound semiconductor layer 4 is non-doped. InAs
The layer 3 is doped with a donor impurity, and conduction electrons generated from the donor impurity in the InAs layer 3 and conduction electrons supplied from the second compound semiconductor layer 4 exist in the InAs layer 3. In addition to the second semiconductor insertion layer 22, the third semiconductor insertion layer 41, and the fourth semiconductor insertion layer 42, the contact layer 50,
This is an example in which 70, a first protective film 81, a second protective film 82, and a side wall 9 are also formed.

First, a mirror-polished (100) having a thickness of 350 μm was used.
A first compound semiconductor layer 2 on a semi-insulating GaAs substrate 1
Undoped Al _0.7 Ga _0.3 As lattice matched to InAs
_{The 0.15} Sb _0.85 layer is 10,000Å, the Al _0.7 Ga _0.3 Sb layer is 20Å as the second semiconductor insertion layer 22, the Si-doped InAs layer 3 having a carrier concentration of 5 × 10 ¹⁷ / cm ³ is 500Å, respectively. They were sequentially grown by molecular beam epitaxy. Then, the third
After growing an Al _0.7 Ga _0.3 Sb layer by 20 ° as a semiconductor insertion layer 41 , a non-doped second compound semiconductor layer 4 is formed.
An Al _0.7 Ga _0.3 As _0.15 Sb _0.85 layer was formed. Further, a GaAs _0.15 Sb _0.85 layer is formed as a fourth semiconductor insertion layer 42 on the layer.
An InAs layer to be 100 Å and the contact layers 50 and 70 was grown 100 Å. Next, unnecessary portions of the laminated thin film formed on the GaAs substrate 1 are removed by photolithography, and the active region is removed.
A resist pattern for manufacturing 11 was formed. Next, etching was performed using an H ₂ SO ₄ : H ₂ O ₂ based etchant to form an active region 11 having a mesa structure. Next, 2,000 .mu.m of SiN was formed on the entire surface by a plasma CVD method, and the first protective film 81, the second protective film 82, and the side wall 9 were simultaneously formed. Then, after forming a resist pattern, SiN in the portion where the source electrode 5 and the drain electrode 7 are formed was etched by anisotropic etching using a reactive ion etching apparatus, while leaving SiN in the portion of the side wall 9. . AuGe (Au: Ge = 88: 12) by vacuum evaporation
Was continuously deposited at 2,000 mm, Ni at 500 mm, and Au at 3,500 mm.
Next, lift-off is performed, and the source electrode 5, the drain electrode 7
Was formed. Thereafter, annealing was performed to obtain an ohmic junction between the source and drain electrode metals and the electron transit layer 3. Next, a resist pattern of the gate electrode 6 is formed, followed by anisotropic etching using a reactive ion etching apparatus, while leaving SiN on the side wall 9 and removing SiN on the portion where the gate electrode 6 is formed. Etching was performed. Furthermore, using this pattern, NH ₄ OH: H ₂
O ₂ -based etchant allows surface InAs layers 50 and 70 and GaAsSb
The layer 42 is etched to form the second compound semiconductor layer 4
A recess structure 12 was formed in the AlGaAsSb layer. Next, 3,000 Al of Al was deposited on the entire surface of the wafer, lifted off,
A gate electrode 6 having a gate length of 1.0 μm was formed. Then
Dicing was performed to separate individual devices. Thus, the FET shown in FIG. 19 was manufactured.

[Trial Production Example 7] Another trial production example shown in FIG. 20 will be described. In this prototype, a part of In of the InAs layer 3 is replaced with Ga to form an electron transit layer, and the thickness thereof is set to 70 °, so that conduction electrons form quantum levels. Also,
Isolation between elements is performed by the region 10 formed by ion implantation.

The p of a mirror-polished (100) plane having a thickness of 400 μm
A 3,000-mm-thick non-doped Ga is formed on the Si substrate 1 as a first semiconductor insertion layer 21 by molecular beam epitaxy.
After forming the As layer, as the first compound semiconductor layer 2, In
Non-doped Al _0.7 Ga _0.3 As _0.15 Sb _0.85 lattice-matched to As
InAs with 5,000 5,000 layer and 9% of In in InAs replaced with Ga
Layer 3 is 70 °, then undoped Al _0.7 Ga _0.3 As _0.15 Sb
_{The 0.85} layer is formed as a second compound semiconductor layer 4 with a thickness of 300 Å, and finally, as a fourth semiconductor insertion layer 42, a GaAs _0.15 Sb _0.85 layer is formed with 100
Å, each formed. Further, as the second protective film 82,
A 1,000Å SiN layer was grown on the entire surface by plasma CVD and covered the substrate surface. Next, a resist pattern for forming the active region 11 of the FET is formed, and then protons are ion-implanted over the entire surface to make the unnecessary portion 10 nonconductive (high resistance).
did.

The source electrode 5 and the drain electrode 7 were formed as follows. After forming the resist pattern,
After SiN was partially removed by reactive ion etching, AuGe (Au: Ge = 88: 12) 2,000 was deposited by vacuum evaporation.
0 Å, Ni were continuously deposited at 500 Å, and Au was continuously deposited at 3,500 Å. Next, lift-off was performed to form a pattern of the source electrode 5 and the drain electrode 7. Thereafter, annealing was performed to obtain an ohmic junction between the electrode metal and the electron transit layer. Next, after forming a resist pattern of the gate electrode 6, SiN was partially removed by reactive ion etching, and then Ti was continuously deposited at 500 ウ エ ハ, Pt at 500Å and Au at 1,0001,000 over the entire surface of the wafer, and lift-off was performed. Was performed to form the gate electrode 6. Finally, dicing was performed to separate the individual devices. Thus, the device of the present invention shown in FIG. 20 was manufactured. Also, this device is leaded by the normal assembly process,
Packaged.

[Trial Example 8] The FET of the present invention shown in FIG. 21 will be described with reference to a prototype example. Mirror-polished 350 μm thick
A non-doped GaAs layer having a thickness of 3,000 形成 was formed on a (100) plane semi-insulating GaAs substrate by molecular beam epitaxy to obtain a substrate 1 of the present invention. Next, the non-doped AlAs _0.15 Sb _0.85 layer 2 lattice-matched to InAs is 1,500Å, the non-doped InAs layer 3 is 700700, and then the non-doped AlAs
_0.15 Sb _0.85 layer 4 was formed. Next, unnecessary portions of the laminated thin film formed on the GaAs substrate 1 were removed by photolithography to form a resist pattern for manufacturing the active region 11 of the FET. Next, mesa etching was performed with an H ₂ SO ₄ : H ₂ O ₂ type etching solution to remove unnecessary portions. Next, after forming a resist pattern, AuGe (Au: Ge = 88: 12) was 2,000 Å, Ni was 500 Å, and vacuum evaporation was performed.
Au was continuously deposited for 3,500 Å. Next, lift-off was performed to form a pattern of the source electrode 5 and the drain electrode 7. Thereafter, annealing is performed at 450 ° C. for 5 minutes in an electric furnace in a nitrogen atmosphere, so that the source electrode 5 and the drain electrode 7 and the InAs layer 3
Ohmic junction was obtained. Further, after forming a resist pattern of the gate electrode 6, 3,000 μm is formed on the entire surface of the wafer.
Of Al was lifted off to form a gate electrode 6 having a gate length of 1.0 μm. Finally, a SiN protective film was formed on the entire surface by a plasma CVD method using silane gas and ammonia gas. And to open a window in the electrode part,
After forming a desired resist pattern, windows were formed in the electrode portion for bonding using reactive ion etching. Then, dicing was performed to separate the individual elements. Thus, the device of the present invention shown in FIG. 21 was manufactured. The device was packaged with leads through a normal assembly process.

The FET of the present invention has a high cutoff frequency due to the high electron mobility of InAs, and is superior in high-speed operability as long as the gate length is the same, as compared with a GaAs field-effect transistor having a conventional structure. Do you get it.

[0124]

[0125]

[Trial Production Example 11] Another trial production example of the FET of the present invention shown in FIG. 21 will be described. A non-doped GaAs layer having a thickness of 3,000 mm was formed on a mirror-polished (100) semi-insulating GaAs substrate having a thickness of 350 μm by a molecular beam epitaxy method. Then, the non-doped AlAs _0.15 Sb _0.85 layer 2 lattice-matched to InAs is 1,500 Å, and the InAs layer 3 is 100
Next, a non-doped AlAs _0.15 Sb _0.85 layer 4 was formed. Thereafter, the device of the present invention shown in FIG. 21 was manufactured in the same manner as in Prototype Example 8. The device was packaged with leads through a normal assembly process.

[Trial Production Example 12] The FET of the present invention shown in FIG. 22 will be described with reference to a trial production example. 350 μm thick mirror polished (1
A 3,000-nm-thick non-doped GaAs layer was formed by molecular beam epitaxy on a semi-insulating GaAs substrate having a surface of 00). Next, the In _0.53 Ga _0.47 As layer 21 is coated with 500 Å of InAs.
After forming a non-doped Ga _0.7 Al _0.3 As _0.15 Sb _0.85 layer 2 lattice-matched to 500 Å, a 100 ノ ン non-doped InAs layer 3
1, 500 In InAs layer 32 doped with Si, and 100 In
Forming an InAs layer 3 comprising a non-doped InAs layer 33 of
Further, a non-doped AlAs _0.15 Sb _0.85 layer 4 was formed. Finally, 200 μm of InAs layers serving as contact layers 50 and 70 doped with 5 × 10 ¹⁸ / cm ³ of Si as impurities were formed. Next, unnecessary portions of the laminated thin film formed on the GaAs substrate 1 were removed by photolithography to form a resist pattern for manufacturing the active region 11 of the FET. Then H ₂
Unnecessary portions were removed by etching with an SO ₄ : H ₂ O ₂ type etching solution. Then, after a resist pattern is formed, AuGe (Au: Ge = 88: 12) is deposited at 2,000 by vacuum evaporation.
0 Å, Ni were continuously deposited at 500 Å, and Au was continuously deposited at 3,500 Å. Next, lift-off was performed to form a pattern of the source electrode 5 and the drain electrode 7. Then, in an electric furnace with a nitrogen atmosphere, 450
Annealing was performed at 5 ° C. for 5 minutes to obtain an ohmic junction between the electrode metal and the electron transit layer. Next, after the resist was stripped, etching was performed with an H ₂ SO ₄ : H ₂ O ₂ -based etchant using both electrodes as a mask in order to remove the InAs layer other than below the source electrode and the drain electrode. Further, after forming a resist pattern of the gate electrode 6, the entire surface of the wafer is
Deposit 3,000 mm of Al, lift off, gate length 1.
A gate electrode 6 of 0 μm was formed. Finally, the plasma CVD method using silane gas and ammonia gas
Was formed on the entire surface. Then, in order to open a window in the electrode portion, a desired resist pattern was formed, and then a window was formed in the electrode portion for bonding using reactive ion etching. Then
Dicing was performed to separate individual devices. Thus, the device of the present invention shown in FIG. 22 was manufactured. The device was packaged with leads through a normal assembly process.

As described above, the device characteristics obtained by the prototype example were extremely desirable. An example is shown in FIG.

FIG. 23 is a graph showing the result of measuring the relationship between the source-drain voltage and the drain current at room temperature when the gate voltage of the FET of Prototype Example 5 was changed. Unlike the characteristics of the conventional InAs-FET shown in FIG.
It can be seen that the drain current is accurately controlled by the voltage applied to, and that it has a good FET characteristic with little leakage current. Good results were also obtained in other prototypes of the present invention.

[0130]

As described above, according to the present invention, an InAs layer having an electron mobility and an electron saturation velocity higher than that of GaAs is used as an electron transit layer, so that it is possible to operate up to a high frequency even with the same gate length. it can. Therefore, at the same operating frequency, the FET of the present invention requires about twice the gate length as compared with the conventional GaAs-HEMT. Therefore, processing of the gate becomes extremely easy. Processing with a dimension of 0.6 μm or more that can be photolithographically performed by a stepper and processing that is smaller than that have large gaps in precision, and the process is complicated. According to the present invention, it is possible to easily manufacture an element operating at an ultra-high frequency by a photolithography process using ultraviolet light. Furthermore, when the gate length is the same as that of the conventional case, the high electron mobility of InAs allows operation at twice as high frequency as that of GaAs. In addition, the yield of the process is good, and mass production is possible.

The present invention contributes to speeding-up, cost reduction, and multi-functionality of an amplifying element for transmitting and receiving satellite broadcasting and an element for high-speed data transfer. Further, the manufacture of a high-frequency device using a microfabrication technique is facilitated, and the manufacture of a higher-speed device is also realized.

[Brief description of the drawings]

FIG. 1 shows a conventional GaSb disclosed in JP-A-60-5572.
FIG. 3 is a band diagram of an FET having a stacked structure of AlSb, and FIG.
The band diagram in the case where Sb and InAs are directly bonded, (b) is a band diagram in the stacked structure of FET, and (c) is a band diagram in the stacked structure of (b).

FIG. 2A is a cross-sectional view of a conventional InAs-FET shown in IEEE EDL Vo.11, No.11, p.526 (1990), and FIG.
It is a graph which shows a characteristic.

FIG. 3 is a sectional view showing the configuration of an embodiment of the FET according to the present invention.

FIG. 4 is a graph showing the electron mobility of InAs when AlGaAsSb is formed on a GaAs substrate and used as a buffer layer of an InAs layer.

FIG. 5 is a phase diagram showing the relationship between the composition ratio, band gap, and lattice constant of AlGaAsSb, which is a quaternary compound semiconductor, and is quoted from JJAP Vol.19 p.1675 1980.

FIG. 6 is a graph showing a calculated value of a critical thickness of an InAs layer with respect to a magnitude of lattice mismatch between a first compound semiconductor layer functioning as a buffer layer and InAs.

FIG. 7 is a graph showing a calculation result of a relationship between a film thickness of an InAs layer and a mutual conductance of an FET.

FIG. 8 shows a configuration of a modification of the FET according to the present invention.
There, the second compound semiconductor layer 4 is an insulating barrier layer without doping donor impurity, a cross-sectional view of a FET as a modification of the above embodiment doped only InAs layer is an electron transit layer.

FIG. 9 is a diagram showing quantum levels formed in an electron transit layer in an FET as a modification 4 of the embodiment.

FIG. 10 shows an InAs layer via a second compound semiconductor layer;
Ohmic junctions with the source and drain electrodes were taken.
FIG. 14 is a cross-sectional view illustrating a configuration of an FET as a modification 5 of the embodiment.

FIG. 11 shows an FE as a modification 6 of the above embodiment, in which a contact layer is arranged below the source electrode and the drain electrode.
FIG. 4 is a cross-sectional view showing the configuration of T.

FIG. 12 is a cross-sectional view showing the configuration of an FET as a modification 7 of the above embodiment, in which donor impurities are ion-implanted around the gate electrode except for the lower portion using the gate electrode as a mask.

FIG. 13 shows an FE as a modification 8 of the above embodiment, in which a conductive layer is inserted between the second compound semiconductor layer and the gate electrode.
FIG. 4 is a cross-sectional view showing the configuration of T.

FIG. 14 is a cross-sectional view showing a configuration of an FET as a modification 9 of the above embodiment, in which a gate electrode portion has a recess structure.

FIG. 15 shows FE obtained by adding various spacer layers to the above example.
FIG. 13 is a cross-sectional view showing the configuration of T, wherein (a) shows modified examples 10 and 11 of the above embodiment, in which first to fourth semiconductor insertion layers are arranged.
FIG. 13B is a cross-sectional view of an FET as a modification 10 of the above embodiment, in which an insulator layer is disposed below the gate electrode.

FIG. 16 is a view showing a configuration of an FET as a twelfth modification of the above embodiment, in which elements are separated by mesa etching and insulating sidewalls are formed on the side surfaces of the mesa cross section, and (a) is a plan view, (b) is a sectional view taken along the line AB, and (c) is a sectional view taken along the CD line.

FIG. 17 is a cross-sectional view showing a configuration of an FET as a modification 13 of the above embodiment, in which an oxidation preventing layer is added to the above embodiment.

FIG. 18 is a cross-sectional view showing the structure of an FET according to Prototype Example 5.

FIG. 19 is a cross-sectional view showing a structure of an FET according to Prototype Example 6.

FIG. 20 is a cross-sectional view showing a structure of an FET according to Prototype Example 7.

FIG. 21 is a cross-sectional view showing a structure of an FET according to prototype examples 8 to 11.

FIG. 22 is a sectional view showing the structure of an FET according to Prototype Example 12.

FIG. 23 is a graph showing IV characteristics of a FET according to Prototype Example 5.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 2 1st compound semiconductor layer 3 InAs layer 4 2nd compound semiconductor layer 5 Source electrode 6 Gate electrode 7 Drain electrode 9 Side wall 10 High resistance region 11 Active region 12 Recess structure 21 First semiconductor insertion layer 22 Second semiconductor insertion layer 30 Quantum level in InAs layer 31, 33 Non-doped InAs layer 32 Doped InAs layer 41 Third semiconductor insertion layer 42 Fourth semiconductor insertion layer 50 Contact layer (below source electrode) 51 AuGe layer of source electrode 5 52 Ni layer of source electrode 5 53 Au layer of source electrode 5 61 Gate electrode lower conductive layer 62 Gate electrode lower insulator layer 70 Contact layer (lower of drain electrode) 71 AuGe layer of drain electrode 7 72 Drain Ni layer of electrode 7 73 Au layer of drain electrode 7 Donor impurity partially introduced under source electrode 75 Region (drain side) into which ions are implanted using gate as a mask 81 First protective film 82 2 of the protective layer 101 GaAs substrate 102 GaSb layer 103 InAs layer 104 AlSb layer

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number Japanese Patent Application No. 3-192410 (32) Priority date August 1, 1991 (1991.8.1) (33) Priority claim country Japan (JP) Preliminary examination (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 29/778 H01L 21/338 H01L 29/812

Claims (1)

(57) [Claims] 1. A substrate having a lattice constant different from that of InAs, disposed on the substrate surface, substantially lattice-matched with InAs,
A first compound semiconductor layer formed of at least one film selected from thin films having a composition defined by AlGaAsSb, AlInAsSb, AlInPSb, and AlGaPSb; and a first compound semiconductor layer disposed on the first compound semiconductor layer. Occurs in the layers
An InAs layer serving as a channel layer having only electrons as carriers , disposed on the InAs layer, substantially lattice-matched to the InAs of the InAs layer, having a large band gap compared to the InAs, and being undoped. An insulating second compound semiconductor layer, at least a pair of ohmic electrodes in ohmic contact with the InAs layer, and disposed on the second compound semiconductor between the pair of ohmic electrodes; A field-effect transistor having at least one gate electrode for controlling current.