JPH0590301A - Field effect transistor - Google Patents

Abstract

PURPOSE:To form a good thin film with little lattice defect, etc., and to acquire a FET of good high-frequency characteristics by forming a compound semiconductor layer as a buffer layer and InAs as channel layer one by one on a semiconductor substrate whose lattice constant is different from that of InAs. CONSTITUTION:A first compound semiconductor layer 2 such as an AlGaAsSb layer is formed to a 0.05 to 3mum thickness by using MBE on a GaAs substrate, for example, whose lattice constant is different from that of InAs. Then, an InAs layer 3 as the channel layer is formed to 0.2mum or less thickness. A second compound semiconductor layer 4 which performs practical lattice matching with InAs and has larger band gap is formed a 50 to 1000mum thickness on an upper part. Furthermore, a source electrode 5 and a drain electrode 7 are formed with ohmic junction with an InAs layer 3, and a gate electrode 6 such as Al, Ti is laminated by using Schottky junction. Manufacture of an element which operates at ultra high-frequency becomes possible and producibility is improved by improvement of yield.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter referred to as FET) suitable as an amplifying element for transmitting / receiving satellite broadcasting and an element for high speed data transfer.
Abbreviated as)).

[0002]

2. Description of the Related Art As a high frequency element in the GHz band, which is represented by an amplifier element for transmitting / receiving satellite broadcasts, a GaAs-MESFET (MetaSFET (MetaSFET) with an epitaxial layer of GaAs on a GaAs substrate as an electron transit layer
Semiconductor FET) or FET using a two-dimensional electron layer accumulated at the heterostructure interface of GaAs and AlGaAs, so-called HEMT
(High Electron Mobility Transistor: Later, GaAs-HEM
Write T. JP-A-56-94780) is widely known. The speed of GaAs devices is that the electron mobility of GaAs is approximately 8,000 cm ² when the impurities are not doped (intrinsic state).
This is because it is as high as / V · sec and has a value several times (5 to 6 times) that of Si.

However, in the GaAs-MESFET, the electron transit layer must be doped with impurities, and due to the scattering of conduction electrons by the impurities, the electron mobility is lowered to about 4,000 cm ² / V · sec. In order to solve this problem, GaAs-HEM
At T, the heterojunction of different semiconductors with different band gaps is used to separate the impurity-doped electron supply layer and the electron transit layer, thereby reducing the influence of impurity scattering and increasing the electron mobility. Has been realized.

Japanese Patent Application Laid-Open No. 59-53714 discloses that the relationship between the impurity concentration and the film thickness of the electron supply layer of GaAs-HEMT is specified.
There are USP No.4,424,525 and USP No.Re.33,584.

In the HEMT structure, generally, the impurity concentration of the electron transit layer is low, so that it is difficult to form an ohmic electrode, and the controllability of electron mobility is poor. In order to compensate for this drawback, a GaAs-FET in which an impurity is doped in both the electron supply layer and the electron transit layer forming the heterojunction has been proposed (JP-A-61).
-54673 publication).

Further, in order to increase the concentration of the two-dimensional electron gas, a GaAs semiconductor heterojunction device has been proposed in which an impurity doping region is expanded to a region including a heterojunction (Japanese Patent Laid-Open No. 61-276267). ).

Further, a double hetero type GaAs-FET is proposed in which both the upper surface and the lower surface of the n-type electron transit layer have a wider gap than this and are in contact with an electron supply layer made of a compound semiconductor doped with impurities. (Japanese Patent Laid-Open No. 61-1
No. 31565).

In addition, USP is defined as defining that both the electron supply layer and the electron transit layer below the source and drain of the GaAs-FET using the above heterojunction contain impurities.
There are No.4,424,525.

However, with these elements, a dozen GHz
To obtain an element that can send and receive band radio waves, 0.2 μ
FETs with very short gate lengths, less than m, are needed. Although photolithography may be used to form a gate electrode having such a length, it requires a high level of technology and stable production is not easy.

In practice, electron beam lithography is often used, but it is more difficult than optical lithography in terms of industrial mass productivity. In addition, the high-frequency element corresponding to the higher frequency band must be the above-mentioned GaAs-MESFET or GaAs-HEMT.
In order to realize it with GaAs-FETs such as, the gate length must be further miniaturized. However, due to the miniaturization of the gate length,
In order to increase the frequency of devices, new technology development and advanced process technology that is difficult to achieve industrially are required.
Therefore, miniaturization technology is easy, mass production is possible, and
There is a demand for a high-frequency element having a new structure that can support a higher frequency band than ever before.

For this purpose, it has been proposed to use an InGaAs thin film having an electron mobility higher than that of GaAs for the electron transit layer of FET (Japanese Patent Laid-Open No. 63-272080). In this proposal, the n-type InGaAs layer is used as an electron transit layer, and the upper and lower surfaces form a double heterojunction in contact with the GaAs layer. As for the GaAs layer, a prototype example in which both of them are doped and a non-doped prototype example are shown. Ga on the substrate
As substrate is used. In this proposal, the InGaAs layer is
Since it is in direct contact with the GaAs layer, In
The ratio of the number of atoms must be small because of the demand for lattice matching. In the prototype example proposed above, it is suppressed to 20%, and the thickness of the InGaAs layer is as thin as 150Å. With such a low In ratio, the improvement in mobility over GaAs is not so great.

Furthermore, studies have been conducted in which a high-quality InAs thin film having an electron mobility and a saturation speed that are overwhelmingly larger than that of GaAs is used for an electron transit layer of a FET.

The high electron mobility and saturation rate of InAs are
-Even if the FET has a longer gate length than the FET, GaAs-FET
It has the possibility of realizing transmission and reception of radio waves of the same high frequency as. However, these conventional InAs-FET attempts have the following problems.

(1) The substrate used is expensive and is not suitable as an industrial material.

(2) The structure is complicated and there are problems in reliability and manufacturing process.

(3) Defects are likely to occur due to the difference in lattice constant between the InAs layer and the semiconductor layer in contact with the InAs layer.

(4) When an InAs layer is laminated on a semiconductor layer having a lattice constant different from that of the InAs layer, there is a limit to the film thickness of the InAs layer that can be laminated without causing defects. This limit film thickness,
That is, since the critical film thickness is small, an InAs layer having a film thickness required for FET design cannot be obtained.

(5) Since there is a large difference in lattice constant between the InAs layer and the semiconductor layer in contact with the InAs layer, strong stress is applied to the InAs layer, which causes thermal instability and a large change over time. Yes Unreliable.

(6) Since the parasitic capacitance between the substrate and the InAs layer is large, it is difficult to expect a sufficient function as a high frequency element.

(7) Since a part of the material is very easily oxidized, the manufacturing method is very complicated and there is a problem in reliability.

(8) InAs has a small band gap energy and cannot obtain a suitable Schottky junction or a non-ohmic junction such as a pn junction.

For example, using an InAs substrate, JP-A-2-
There is a proposal described in Japanese Patent No. 5439. InAs substrates are not only expensive and difficult for industrial purposes, but because an insulating substrate cannot be obtained at room temperature, they have a parasitic capacitance between them and the electron transit layer, so that good high-speed characteristics can be obtained. It becomes an obstacle.

On the other hand, on substrates with greatly different lattice constants,
There is also a InAs thin film directly formed. For example,
No. 2-229438 discloses that molecular beam epitaxy (M
BE: Molecular Beam Epitaxy) is used to form a GaAs buffer layer, and the In layer as an electron transit layer is directly formed on the GaAs buffer layer.
A double hetero type InAs-FET in which an As layer is formed and a GaAs layer is further formed thereon is disclosed. In this structure,
Since the InAs layer is formed on a GaAs substrate with a significantly different lattice constant, a good quality InAs thin film can be obtained with an InAs layer thickness of 20Å
Limited to below. This is an obstacle in designing an element having a high current drive capability, significantly restricts the degree of freedom in design, and is practically problematic.

As one method of relaxing the lattice mismatch between the GaAs substrate and the InAs substrate, Japanese Patent Laid-Open No. 60-5572 discloses GaSb.
We have proposed an InAs-FET using a stack of AlSb and AlSb layers as a buffer layer. GaSb has a small lattice constant deviation from InAs, which is about 0.6%. However, in order to form a FET using the InAs layer as the electron transit layer, the InAs thin film is directly formed on GaSb as shown in Fig. 1 (a). It is higher than the bottom of the conduction band of the InAs layer 103, which is not preferable. Therefore, as shown in Fig. 1 (b),
An AlSb layer 104 is formed on the GaSb layer 102 as a current barrier layer for electrically insulating the GaSb layer 102 and the InAs layer 103,
An InAs layer 103 is formed on this. However, this structure not only complicates the buffer layer, but also uses the AlSb layer 104 as a dielectric film and the parasitic capacitance using the sandwiched GaSb layer 102 and InAs layer 103 as electrodes, as shown in Fig. 1 (c). Are formed, which is not preferable as a structure of a high speed device.
Further, since the AlSb layer 104 has a lattice constant different from the InAs layer 103 by 1.25%, the critical film thickness of the InAs thin film 103 on the AlSb film 104 is
It becomes less than 200 Å, which is also a limitation in obtaining a high current drive element. The fact that the AlSb film 104 has a property of being easily oxidized is also a cause of complicating the process when forming the active layer region by the mesa etching method, etc., and there is a possibility that the element characteristics of the AlSb film 104 may change with time due to the oxidation. Poor. Furthermore, this proposal does not disclose an antioxidant method.

As one of the methods for alleviating the lattice mismatch between the GaAs substrate and the InAs substrate, the InAs layer formed on the buffer layer made of the laminated film of AlSb and Al _0.5 Ga _0.5 Sb layer is used as the electron transit layer. There is an InAs-FET (IEEE ELECTRON DEVICE LETTER
S, Vol.11, No.11, NOVEMBER, 1990). Figure 2 (a) shows the above In
The structural drawing of As-FET is shown. Al _0.5 Ga _0.5 Sb has a deviation of the lattice constant from InAs of about 0.9% and a critical film thickness of 300 Å or less. Therefore, it is a limitation in obtaining a device driven by a high current. Moreover, in this example, an AlSb layer of 2.8 μm is used as the substrate.
It is used as a buffer layer between Al _0.5 Ga _0.5 Sb layers and the InAs layer.
Between the Al _0.5 Ga _0.5 Sb layers, in order to increase the carrier concentration in the electron transit layer, a complicated laminated structure in which a 60 Å AlSb layer is inserted is used. Also, these carriers can come from donors in unintentionally doped AlSb or with the AlSb layer.
It is supplied to the electron transit layer from the interface with the InAs layer, and it is difficult to control its concentration according to the design value in the manufacturing process of this FET. Therefore, this has a problem in terms of industrial mass productivity and is not practical. Figure 2 (b)
Shows the current-voltage characteristics of the InAs-FET manufactured by the above method. Although pinch-off characteristics can be seen, the linearity in the saturation region is poor, and the gate length is 1.7 μm, the impact ionization effect is remarkable, and it is not practical.

AlGaAs whose InAs layer is approximately lattice-matched to it
An InAs-FET having a structure sandwiched by Sb layers has been proposed (JP-A-60-144979). In this proposal, an InGaAs multilayer structure in which the composition ratio and the lattice constant change stepwise is arranged as a buffer layer on a semi-insulating InP substrate. The InGaAs multi-layer structure is based on the InP lattice constant of the substrate.
Up to the lattice constant of is designed to change little by little at each step. On top of this, a laminated film having a structure in which an InAs layer is sandwiched by AlGaAsSb layers is formed. The AlGaAsSb layer is used as a barrier layer for confining conduction electrons in the InAs layer. The structure of the InAs-FET thus obtained is extremely complicated and not preferable in manufacturing. Further, the uppermost InGaAs layer of the InGaAs multilayer film forming the buffer layer is
It has characteristics very close to those of InAs, its bandgap is close to that of InAs, and it is a conductor at room temperature. For this reason,
A parasitic capacitance is formed using the AlGaAsSb layer as a dielectric film and the InAs layer of the electron transit layer and the InGaAs layer of the buffer layer as electrodes, and good high frequency characteristics cannot be obtained. In addition, the gate electrode and InAs
If it comes into direct contact with the layer, ohmic contact will occur,
When the active region is formed by the mesa separation method, it is necessary to devise a structure to avoid this contact, but there is no disclosure of such a structure. Furthermore, since the AlGaAsSb film has the property of being extremely easily oxidized when the Ga component is small, when the active layer region is formed by the mesa etching method or in the structure where the AlGaAsSb film above the InAs film is exposed, the AlGaAsSb film is exposed. Although a film antioxidation measure is essential, this proposal does not disclose an antioxidation method.

[0027]

As described above, there have been attempts to utilize InAs having a high electron mobility as an electron transit layer of a FET, but no FET structure suitable for practical use has been found.

It is an object of the present invention to provide an FET having excellent high frequency characteristics as an amplifying element for transmitting / receiving satellite broadcasts and an element for high speed data transfer.

[0029]

In order to achieve the above object, a FET according to the present invention comprises a first compound semiconductor layer functioning as a buffer layer and an electron transit layer on a semiconductor substrate having a lattice constant different from InAs. It has a structure in which an InAs layer functioning as is sequentially laminated.

[0030]

Function: In used as the electron transit layer in the present invention
As has an electron mobility and saturation velocity that are overwhelmingly higher than GaAs, which is usually used as the electron transit layer of high-frequency FETs. In addition, the temperature dependence is reasonably small and was expected as a material for next-generation high-speed devices that surpass GaAs-FETs. Above all, from a practical point of view, InAs on a general-purpose substrate of GaAs or Si
There has been a demand for a technique for forming a high-quality crystalline thin film.

Since GaAs and Si substrates have remarkably different lattice constants from InAs, when an InAs layer is formed on these substrates, the critical thickness is exceeded by several atomic layers and lattice defects occur. Therefore, in order to obtain a good quality InAs thin film, it is necessary to form an insulating buffer layer between the substrate and the InAs thin film. Of course, it is desirable that the buffer layer is substantially lattice-matched to InAs and has a smooth surface with few defects, but it is thermally stable from the viewpoint of manufacturing method and reliability,
A simple structure with little change over time is desirable, and it is also desirable that the structure protects the substrate leakage current, has a small parasitic capacitance, and is insulative.

The present invention is based on the discovery of a semiconductor layer having a simple structure that satisfies the conditions as a material for such a buffer layer, and uses an InAs layer formed on this buffer layer as an active layer. A completely new FET that realizes a high-frequency FET on a substrate with a lattice constant different from that of the InAs layer
It presents the structure.

The first compound semiconductor layer is made of AlGaAs which has a substantially lattice matching with InAs and has a larger band gap.
It is formed by selecting from Sb, AlGaPSb, AlInAsSb, or AlInPSb, and has a simple structure.

The structure of the buffer layer could be simplified because
This is due to the fact that the first compound semiconductor layer such as the GaAsSb layer absorbs the influence of the lattice mismatch between the substrate and the InAs layer with only a few tens of atomic layers to form a smooth plane.
As a result, a good quality InAs thin film with few lattice defects and the like could be formed on a general-purpose substrate such as GaAs or Si substrate. Moreover, the critical film thickness of the InAs layer is large enough to obtain the film thickness required for FET design, the stress received at the interface of the InAs layer is small, it is thermally stable, and it is stable with a small change over time. InAs can be obtained with high frequency
The parasitic capacitance between the layers and the substrate was small, and excellent characteristics as a high frequency device were obtained. Some of the materials are easily oxidized, but the side walls of the mesa structure and the protective film prevented the oxidation. For Schottky junction, etc.
We have been able to realize a FET with excellent high-frequency characteristics by using several measures to facilitate this.

[0035]

EXAMPLES The inventors of the present invention have shown that InAs is substantially lattice-matched with InAs on the insulating substrate which is not lattice-matched with InAs, and InAs is used.
We have investigated a new structure of InAs-FET with a buffer layer that absorbs the lattice mismatch between the two. As a result, AlGaAsSb, which is a compound semiconductor that is substantially lattice-matched to InAs and has a larger bandgap than InAs, is formed on a substrate that is not lattice-matched to InAs, and an InAs layer is formed on top of it. Found. In this structure, the lattice mismatch between the substrate and InAs is relaxed in the AlGaAsSb layer, which is only a few tens of atomic layers, and not only a good InAs layer is obtained, but also the substrate and AlGa
It was found that the lattice distortion near the interface of the AsSb layer was small and the parasitic capacitance was small when the FET was manufactured. In addition, it was also revealed that there are some compound semiconductors showing similar effects. These compound semiconductors are used as substrates
As a buffer layer for relaxing lattice mismatch between InAs layers, an InAs layer is formed on this buffer layer, and
By forming a compound semiconductor layer that substantially lattice-matches with the InAs layer on the InAs layer, an InAs-FET with good characteristics, which could not be realized up to now, was realized.

Embodiment 1 An embodiment of the field effect transistor according to the present invention will be described below with reference to FIG. In FIG. 3, 1 is a substrate, 2 is a first compound semiconductor layer, 3 is an InAs layer, and 4 is a second compound semiconductor layer. Further, 5 and 7 are a pair of ohmic electrodes, 5 is a source electrode, and 7 is a drain electrode. Reference numeral 6 is a gate electrode provided between the source electrode 5 and the drain electrode 7. Hereinafter, each component will be described.

Substrate 1 The substrate 1 used in the present invention may be any substrate as long as it has a lattice constant different from InAs, but it may be a GaAs substrate, a GaP substrate, or a Si substrate on the surface of which single crystal GaAs is grown. A sapphire substrate or the like is suitable. Of these, a GaAs substrate is particularly preferable because it is semi-insulating and a good quality single crystal substrate can be obtained. The term "semi-insulating property" as used herein means that the resistivity is 10 ⁷ Ω · cm or more. When a single crystal substrate is used, the plane orientation of the substrate is preferably (100), (111), (110) or the like. A plane direction deviated from these plane directions by 1 ° to 5 ° may be used.
Among them, the (100) plane is optimal for growing good quality thin films. Flatten the surface of the substrate, as usual
For the purpose of cleaning, a grown semiconductor of the same material as the substrate may be used as the substrate of the present invention. Growing GaAs on a GaAs substrate is one of the most representative examples of this. The present invention is superior to the conventional method in the case where a substrate having a lattice constant different from that of InAs is used.
Substrates with a lattice constant that differs from As by more than 3.5% are
There are substrates, Si substrates, etc., and since many substrates are desirable in terms of crystal purity, flatness, substrate cost, etc., the superiority of the present invention over the conventional method is most remarkable.

First Compound Semiconductor Layer 2 The first compound semiconductor layer 2 is directly (a) substantially lattice-matched with the InAs layer and (b) directly on a substrate such as GaAs having a lattice constant largely different from that of the InAs layer 3. Even when stacked, it has a smooth surface with few defects, and (c) is a compound semiconductor with few crystal defects that cause parasitic capacitance near the interface with the substrate, and (d) InAs
It is preferable that the interface with the layer 3 forms a barrier that blocks the substrate leakage current.

FIG. 4 shows how the electron mobility of the 300 Å InAs layer 3 laminated on the AlGaAsSb layer 2 formed directly on the GaAs substrate 1 using MBE changes depending on the film thickness. Indicate. Further, for comparison, the electron mobility of the 300 Å InAs layer formed on the AlSb layer directly provided on the GaAs substrate is shown by a white circle. The 300 Å InAs layer on the AlSb layer has already exceeded the critical thickness and the electron mobility is poor.
The electron mobility of the InAs layer 3 formed on the AlGaAsSb layer 2 is
A high value was obtained when the film thickness of the AlGaAsSb layer 2 was 0.1 μm or more, and a considerably high value was already obtained even at 300 Å. This result and RHEED (REFLECTION HIGH ENERGY ELECTRON DIFF
RACTION) and X-ray analysis results show that the film thickness is 0.1 μ
The AlGaAsSb layer 2 having a thickness of m or more has a very smooth surface, and has a good quality with few defects in most of the film except the region at a distance of about 100 Å from the interface with the GaAs substrate 1. It was found to have crystallinity. AlGaPS
b, AlInAsSb and AlInPSb have similar characteristics.

These four types of compound semiconductors, Al _x1 Ga _1-x1
As _y1 Sb _1-y1 , Al _x2 In _1-x2 As _y2 Sb _1-y2 , Al _x3 In _1-x3 P _y3 Sb
_{Both 1-y3} and Al _x4 Ga _1-x4 P _y4 Sb _1-y4 can satisfy these conditions by selecting their component ratios. The range of the composition ratio is determined by three different methods described below.

I. First Method The first method is defined so as to satisfy the following two conditions.

(1A) The lattice constant of the first compound semiconductor layer 2 matches the InAs lattice constant of the InAs layer 3 within 0.6%, and (2) the first compound semiconductor layer 2 is 1 eV or more. And has a bandgap of 1 to form a potential barrier necessary for confining conduction electrons of the InAs layer 3 in the InAs layer 3.

There is no compound semiconductor other than InAs in the binary system of the III-V group, which has a lattice matching with InAs within 0.6%. However, in order to form a thin film in which the InAs layer 3 laminated on the first compound semiconductor 2 has an appropriate critical film thickness and less stress that causes thermal stability and aging, 0.6 It is considered that lattice matching within% is necessary.
FIG. 5 is a phase diagram of a III-V group quaternary compound semiconductor that satisfies this condition.

In the phase diagram shown in FIG. 5, Al _x1 Ga _1-x1 As _y1
Sb _1-y1 is represented by a point in a rectangular region D1 obtained by connecting four points of AlAs, AlSb, GaSb, and GaAs. In this region D1, the value of x1 changes from 0 to 1 in proportion to the distance from the straight line L1 connecting the points of GaAs and GaSb, and takes 1 on the straight line L2 connecting the points of AlAs and AlSb. The value of y1 is the straight line connecting AlSb and GaSb
It changes from 0 to 1 in proportion to the distance from L3, and AlAs and Ga
It becomes 1 on the straight line L4 connecting As. The broken line and the alternate long and short dash line in the figure show the contour line of the band gap and the contour line of the lattice constant of the compound semiconductor having the composition and the composition ratio represented by each point, respectively.

FIG. 5 shows a region containing Al _x1 Ga _1-x1 As _y1 Sb _1-y1 which satisfies the above conditions (1A) and (2) by a region of a rectangle R1 drawn by a solid line. This area is {0.21 ≦ x1 ≦ 1.0
, 0.02 ≦ y1 ≦ 0.22}. Similarly, Al _x2 In _1-x2 As _y2 Sb _1-y2 , Al _x3 that satisfies the conditions (1A) and (2)
The rectangular regions containing In _1-x3 P _y3 Sb _1-y3 and Al _x4 Ga _1-x4 P _y4 Sb _1-y4 are {0.34 ≦ x2 ≦ 1.0, 0.09 ≦ y2 ≦, respectively.
0.79}, {0.07≤x3≤1.0, 0.06≤y3≤0.72}, and {0.13≤x4≤1.0, 0.13≤y4≤0.18}. More precisely, the composition ratio ranges of the above four kinds of compound semiconductors satisfying the conditions (1A) and (2) are as follows: {0.21 ≦ x1 ≦ 1.0, 0.09x1 ≦ y1 ≦ 0.07x1 + 0.15}, {0.34 ≤x2≤1.0, -0.82x2 + 0.91≤y2≤-0.87x2 + 1.09}, {0.07≤x3≤1.0, -0.57x3 + 0.63≤y3≤-0.58x3 + 0.76}, and {0.13≤x4≤1.0, 0.06x4 ≦ y4 ≦ 0.06x4 + 0.12}.

II. Second Method As a range in which a higher quality InAs layer 3 can be obtained, the second method is defined so as to satisfy the following two conditions. (1B) The lattice constant of the first compound semiconductor layer 2 matches the InAs lattice constant of the InAs layer 3 within 0.4%, and (2) the first compound semiconductor layer 2 has a band gap of 1 eV or more. InAs layer 3
To form a potential barrier necessary for confining the conduction electrons of (3) in the InAs layer 3.

The ranges of the composition ratios of the above four kinds of compound semiconductors which satisfy the above conditions (1B) and (2) are defined as follows based on FIG.

Al _x1 Ga _1-x1 As _y1 Sb _1-y1 is {0.21 ≦ x1 ≦ 1.0, 0.08x1 + 0.03 ≦ y1 ≦ 0.08x1 + 0.12}, Al _x2 In _1-x2 As _y2 Sb _1-y2 is , {0.34≤x2≤1.0, -0.83x2 + 0.94≤y2≤-0.86x2 + 1.06}, Alx3In1-x3Py3Sb1-y3 is {0.07≤x3≤1.0, -0.57x3 + 0.65≤y3≤-0.58x3 + 0.74 }, And Al _x4 Ga _1-x4 P _y4 Sb _1-y4 are {0.13 ≦ x4 ≦ 1.0, 0.06x4 + 0.02 ≦ y4 ≦ 0.06x4 + 0.10}.

III. Third Method The third method is defined so as to satisfy the following two conditions.

(1C) InAs such that the critical film thickness of the InAs layer 3 formed on the first compound semiconductor layer 2 maximizes the mutual conductance of the FET having the InAs layer 3 as an electron transit layer.
A potential barrier required to confine the conduction electrons of the InAs layer 3 into the InAs layer 3 because the thickness is equal to or larger than the thickness of the As layer, and (2) the first compound semiconductor layer 2 has a bandgap of 1 eV or more. To form.

FIG. 6 shows InAs of the lattice constant of the AlGaAsSb layer 2.
An outline of the relationship between the degree of lattice mismatch and the critical film thickness with respect to the lattice constant of is shown. AlGaPSb, InGaAsSb and InGaPS
b also shows almost the same characteristics.

As shown in FIG. 6, the highest lattice matching degree is required when the thickest electron transit layer is required, but in the present invention, the required electron transit layer thickness is required. The preferred upper limit was defined as the film thickness that maximizes the FET transconductance.

The magnitude of the transconductance of the FET is substantially proportional to the product μN _D a of the mobility μ, the donor concentration N _D and the film thickness a of the electron transit layer under the bias condition that maximizes the value. Therefore, in order to obtain a FET with large transconductance, a structure with a large product μN _D a is desired. A potential difference between the upper surface and the lower surface of the electron transit layer 3 necessary for depleting the electron transit layer 3 by applying a voltage perpendicularly to the electron transit layer 3
Assuming V _off , the voltage V _off increases with the donor concentration N _D and the film thickness a. In the FET, the value of voltage V _off is preferably about 1/4 of the source-drain breakdown voltage V _B of the electron transit layer 3.

FIG. 7 is a graph showing an outline of the dependence of the product μN _D a on the film thickness a. Product μ at each film thickness a
The value of N _D a, such that the voltage V _off becomes about 1/4 breakdown voltage V _B, defines the donor concentration N _D, given in consideration of the N _D dependence of breakdown voltage V _B and the mobility μ There is. The product μ N _D a takes a maximum value when the value of the film thickness a is around 2,000 Å, and at this point, it changes from an increasing function of a to a decreasing function. Therefore, it is understood that the thickness of the InAs layer 3 may be 2,000 Å or less in the practical device.
Also, from FIG. 6, it can be seen that the transconductance is about 80% of the maximum value when the film thickness is about 400 Å.

From FIG. 5, the following conditions are obtained.

(3) InAs electron transit layer 3 with a critical thickness of 2,000Å
In order to realize the above, it is necessary to determine the component ratio of the AlGaAsSb layer 2 so that the deviation of the lattice constant from the lattice constant of InAs is within 0.2%.

InAs electron transit layer 3 with a critical film thickness of 400 Å
In order to realize the above, it is understood that the component ratio of the AlGaAsSb layer 2 needs to be determined so that the deviation of the lattice constant from the lattice constant of InAs is within 0.6%. Al
Similar results are obtained when GaPSb, InGaAsSb and InGaPSb are used as the first compound semiconductor layer 2.

In order to realize an FET having a higher transconductance, the first compound semiconductor layer 2 not only satisfies the above conditions (1C) and (2) but also satisfies the condition (3).
The composition of can be determined based on the phase diagram of FIG.
The results are as follows.

Al _x1 Ga _1-x1 As _y1 Sb _1-y1 is {0.21 ≦ x1 ≦ 1.0, 0.08x1 + 0.05 ≦ y1 ≦ 0.08x1 + 0.10}, Al _x2 In _1-x2 As _y2 Sb _1-y2 is , {0.34≤x2≤1.0, -0.84x2 + 0.97≤y2≤-0.85x2 + 1.03}, Alx3In1-x3Py3Sb1-y3 is {0.07≤x3≤1.0, -0.57x3 + 0.67≤y3≤-0.58x3 + 0.72 }, and _{Al x4 Ga 1-x4 P y4} Sb 1-y4 is, {0.13 ≦ x4 ≦ 1.0, 0.06x4 + 0.04 ≦ y4 ≦ 0.06x4 + 0.08}.

Among these four kinds of compound semiconductors, AlGaAsSb, Al whose composition is easy to control and thin films of good quality can be easily obtained.
InAsSb is preferred. In particular, when AlGaAsSb was used as the first compound semiconductor layer 2, the FET characteristics were the best.

The first compound semiconductor layer 2 may have conductivity even when it is not doped with impurities. in this case,
In order to cancel the effect of the carriers contributing to the electric conduction, an impurity having a polarity opposite to that of the carriers contributing to the electric conduction may be doped. The thickness of the first compound semiconductor layer 2 may be freely selected, but due to manufacturing restrictions,
The preferable range is 0.05 to 3.0 μm. More preferably 0.1 to 2.0 μm, even more preferably 0.1 to 1.0 μm
Is.

InAs Layer 3 The InAs layer 3 which is the electron transit layer of the present invention has a thickness of 0.2 μm for the purpose of controlling electric conduction by the voltage applied to the control electrode.
m or less is preferable. The InAs layer 3 may be non-doped, but even if it is doped with impurities, sufficiently high electron mobility can be obtained. Therefore, it is possible to dope impurities as necessary. Any doped donor impurity may be used as long as it acts as a donor atom in InAs.
S, Sn, Se and Te are particularly preferred impurities. The amount of impurities to be doped may be 5 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ¹⁸ / cm ³ , but a preferable range is 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / c.
m ³ and more preferably 2 × 10 ¹⁷ / cm ³ to 8 × 10 ¹⁷ / cm ³
Is. The position where impurities are doped may be uniform in the thickness direction of the InAs layer 3, but if the central portion of the film is doped while avoiding the vicinity of the interface with other compound semiconductor layers 2 and 4, the first compound semiconductor layer 2 and the scattering of conduction electrons at the interface with the second compound semiconductor layer 4 can be reduced, which is preferable. Also, InAs
In may be replaced with Ga as long as it is within 9% of the total number of In atoms. Within this range, the difference in lattice constant from InAs of the InAs layer 3 is 0.6% or less, and the lattice matching with the first compound semiconductor 2 and the second compound semiconductor 4 is substantially achieved. Therefore, FE can be
The breakdown voltage of T can be increased. The lattice constants of the first compound semiconductor layer 2 and the second compound semiconductor layer 4 are
When the lattice constant of InAs of InAs layer 3 is 0.4% or less, if the amount of Ga replaced with In is 6% or less, deterioration of characteristics of InAs layer 3 due to lattice mismatch and deterioration with time are reduced. it can. Furthermore, if the lattice mismatch is set to 0.2% in order to achieve a higher lattice match, the characteristic deterioration of the InAs layer 3 due to the lattice mismatch can be further reduced by setting the amount of Ga replacing In to 3% or less. ..

Second compound semiconductor layer 4 Second compound semiconductor layer 4 formed on the InAs layer 3
Is substantially lattice-matched with InAs, and conduction electrons are InAs.
In order to form a barrier suitable for being confined in the layer at the interface with the InAs layer 3, one having a larger band gap than the InAs layer 3 is preferable. Further, the electron affinity of the second compound semiconductor layer 4 is smaller than the electron affinity of the InAs layer 3, and the sum of the electron affinity and the band gap is smaller than the sum of the electron affinity and the band gap of the InAs layer 3. When it becomes large, the characteristics of the InAs layer 3 are not impaired, which is preferable. These requirements are common with the requirements for the first compound semiconductor layer 2.

Further, in the FET using the Schottky junction, it is necessary that the second compound semiconductor layer 4 and the gate electrode 6 form a good Schottky junction. on the other hand,
MI using the second compound semiconductor layer 4 as an insulating barrier layer
In the S-type FET, the second compound semiconductor layer 4 is preferably made of a material that forms a good insulating film. Any compound semiconductor satisfying these requirements may be used, but among them, Al _x1 Ga _1-x1 As _y1 Sb _1-y1 , which is used as the first compound semiconductor layer 2,
Al _x2 In _1-x2 As _y2 Sb _1-y2 , Al _x3 In _1-x3 P _y3 Sb _1-y3 , Al _x4 Ga
_1-x4 P _y4 Sb _1-y4 is particularly preferred. Further, the component ratio thereof is determined similarly to that of the first compound semiconductor layer 2. AlGaAsSb and AlInAsSb, which can easily obtain high quality thin films, are particularly good. Second
The thickness of the compound semiconductor layer 4 is preferably 50 Å to 1,000 Å,
After the gate electrode 6 is formed, it may be in a range where conduction electrons do not exist in the second compound semiconductor layer 4.

When the second compound semiconductor layer 4 is doped with a donor impurity to form an electron supply layer to the InAs layer 3, the doped donor impurity may be anything that acts as a donor atom. Se, S, Si and Sn are particularly preferable impurities. The amount of impurities doped is 5 × 10 ¹⁶
/ cm ^{3 to} 5 × 10 ¹⁸ / cm ³ may be used, but the preferred range is 1
× 10 ¹⁷ / cm ^{3 to} 5 × 10 ¹⁸ / cm ³ . The doping position may be uniform or may be distributed in the thickness direction. In particular, when the structure is such that the impurities are not doped only in the vicinity of the interface on the side where the gate electrode 6 is formed, the gate breakdown voltage is not lowered, which is favorable. Further, the second compound semiconductor layer 4 near the interface with the InAs layer 3 has a structure in which impurities are not doped, so that scattering of conduction electrons in the InAs layer 3 due to impurities can be reduced and the operating speed of the FET can be reduced. It is preferable for increasing the value.

Further, the second compound semiconductor layer 4 is not limited to the above-mentioned compound semiconductor composed of the elements of group III and group V, but may be a compound semiconductor composed of the elements of group II and VI.

When the first compound semiconductor layer 2 and the second compound semiconductor layer 4 are made of compound semiconductors having the same composition,
It is preferable because it can simplify the manufacturing process, but different composition,
Alternatively, a structure in which compound semiconductors having the same composition but different composition ratios are combined may be used, and the structure is appropriately performed as necessary.

Source Electrode 5 and Drain Electrode 7 The source electrode 5 and drain electrode 7 are
It is necessary to form an ohmic contact with the As layer 3. Although there are various structures in the ohmic junction, in the embodiment shown in FIG.
The electrode is in direct contact with the As layer 3.

The InAs layer 3 has a narrow band gap, and an ohmic junction having a low contact resistance can be obtained only by contacting the electrodes. Therefore, the second compound semiconductor layer 4 can be etched only under the ohmic electrodes 5 and 6 to directly form electrodes on the InAs layer 3. In this case, in order to reduce the contact resistance between the electrodes 5 and 7 and the InAs layer 3, an alloying step may be performed, but good ohmic contact can be obtained only by vapor deposition. Therefore, the electrode metal is AuGe
A well-known laminated electrode structure including a three-layer structure of / Ni / Au may be used, but a single-layer metal such as Al, Ti, Au, and W may be used, and an extremely large number of combinations are possible.

Gate Electrode 6 The gate electrode 6 shown in FIG. 3 may be any one as long as it can form a depletion layer thereunder. In addition to the method of using the Schottky junction, insulation between the gate electrode 6 and the InAs layer 3 is obtained. Sandwiched things
It is also possible to use a MIS (METAL-INSULATOR-SEMICONDUCTOR) structure or a pn junction. In particular, Al, Ti, W, Pt, WSi, Au, or the like is preferable as a material for forming a Schottky junction with a semiconductor such as the second compound semiconductor 4, and those having a laminated structure may be used.

The above is the basic layer structure of the FET of the present invention, but the InAs layer 3 does not exhibit a significant decrease in electron mobility even when doped with impurities, and has a higher electron mobility than GaAs, InGaAs, and the like. Therefore, depending on how the InAs layer 3 and the second compound semiconductor layer 4 are doped with donor impurities,
Transistors with different types of features are possible. These will be described as Modifications 1-3 of the above embodiment.

Modified Example 1 As shown in FIG. 8A, the first type is used as an insulating barrier layer without doping the second compound semiconductor layer 4 with a donor impurity, and will be described later. The prototype example 1 of the above belongs to the modification example 1.

In this case, the InAs layer 3 need not be doped with the donor impurity, but may be doped with the donor impurity as long as the characteristics of the InAs layer 3 are not deteriorated. This FE
At T, since the gate electrode 6 is formed on the second compound semiconductor layer 4 having a low impurity concentration, a gate electrode having a high gate breakdown voltage and good rectifying property can be formed.

Modification 2 In the second type, as shown in FIG. 8B, only the second compound semiconductor layer 4 is doped with a donor impurity. Belong to. InAs layer 3
The conduction electrons in the inside are mainly electrons supplied from the second compound semiconductor layer 4 due to the difference in electron affinity.
Impurities are not intentionally doped in the As layer 3. Therefore, the scattering of conduction electrons due to impurities in the InAs layer 3 is the smallest of the three types. Therefore, among the InAs-FETs according to the present invention, it is possible to manufacture the FET that is most excellent in high-speed operability and has excellent noise characteristics.

Modification 3 As shown in FIG. 8 (c), the third type is the InAs layer 3 and the second type.
Both of the compound semiconductor layers 4 of Example 2 are doped with a donor impurity, and the prototype example 3 belongs to the modification example 3.

In this case, both the conduction electrons generated from the donor impurities in the InAs layer 3 and the conduction electrons supplied from the second compound semiconductor layer 4 due to the difference in electron affinity exist in the InAs layer 3. And serves as a current carrier. Therefore, at an impurity concentration that does not impair the characteristics of the InAs layer 3,
An extremely high concentration of conduction electrons can be concentrated in the InAs layer 3, and even if the InAs layer 3 is extremely thin, a large current can be taken, so that an ideal structure for an electron transit layer of a FET can be realized.

Further, while the intrinsic conduction electrons thermally excited in the InAs layer 3 are 10 ¹⁵ / cm ³ to 10 ¹⁶ / cm ³ near room temperature, the conduction electrons generated from the donor impurity Is 10 ¹⁷
High concentration of / cm ³ to 10 ¹⁸ / cm ³ . For this reason, FETs with small fluctuations in FET characteristics due to changes in the operating environment temperature of the FET
Becomes

Modification 4 When the thickness of the InAs layer 3 becomes a thickness at which a quantum level is formed, regardless of the method of doping impurities into the second compound semiconductor layer 4 and the InAs layer 3, As shown in the band diagram of FIG. 9, the energy level 30 of conduction electrons in the InAs layer 3 is quantized, and a so-called quantum level is formed. For this reason, even if the operating environment temperature of the element changes, the resistance value of the InAs layer 3 changes less, and a FET having excellent temperature characteristics can be obtained as compared with the case where no quantum level is formed.

Furthermore, since the conduction electrons flowing in the InAs layer 3 are less likely to be scattered, the transistor is suitable for high speed operation. Moreover, while the InAs layer 3 having a narrow bandgap is used as the electron transit layer, the effect is the same as that of the bandgap being substantially widened due to the effect of the discrete quantum levels. Therefore, the breakdown voltage of the transistor can be increased.

In order to obtain such characteristics, it is preferable that the thickness of the InAs layer 3 be 400 Å or less. Especially 200 Å
In the following, the effect of the quantum level becomes more remarkable.

InAs as the material of the quantum well is GaAs, Si
Since the effective mass of electrons is smaller than that of, the quantum level can be easily formed even if the width of the quantum well is wide. The lattice constant of a compound semiconductor is usually 5 to 6Å, but at the stage of thin film growth,
Even if a surface step difference of about one atomic layer is generated, the influence of the step difference can be suppressed to be small because the quantum well is thick. In addition, since InAs has a large quantum well width, it is possible to obtain a large conductance while using the quantum well as an electron transit layer. The prototype example 4 belongs to the modification example 4 and is an example of a quantum effect FET in which the InAs layer 3 is 100 Å.

Next, the source electrode 5 and the drain electrode 7
A modified example will be described.

Modified Example 5 As shown in FIG. 10, the source electrode 5 and the drain electrode 7 are formed of In via the second compound semiconductor layer 4 on the InAs layer 3.
A structure that makes ohmic contact with the As layer 3 may be used. This structure is formed by the following method. That is, the electrodes 5,
In order to obtain an ohmic contact between the In and the InAs layer 3, alloying annealing is performed to diffuse the electrode material to form heavily doped regions 54 and 74, or Donor impurities are ion-implanted only in the lower regions 54 and 74 to reduce the contact resistance.

Modification 6 As shown in FIG. 11, the source electrode 5 and the drain electrode 7
There is also a technique of forming the contact layers 50 and 70 between the InAs layer 3 and the InAs layer 3 to form an ohmic contact having a lower contact resistance.

The contact layers 50, 70 are preferably GaAs, GaAsSb, InGaAs, InAs, InSb doped with a donor impurity and have a thickness of 500 Å or less, but 100 Å to 300 Å.
Are particularly suitable. Further, the donor impurities doped into the contact layers 50 and 70 may be Si, S, Sn, Se, as long as they act as donor atoms in the contact layer.
Te is a particularly good impurity. The amount of impurities to be doped varies depending on the materials of the contact layers 50 and 70, but 5
× 10 ¹⁷ / cm ³ to 10 ¹⁹ / cm ³ is a preferable range.

Next, a modification of the gate electrode 6 will be described.

Modified Example 7 When a high melting point metal such as W or WSi is used as the material of the gate electrode 6, as shown in FIG.
Donor impurities may be ion-implanted into the regions 55 and 75 excluding the lower portion of the gate electrode 6 to form a self-alignment structure in which the peripheral regions 55 and 75 of the gate electrode 6 have low resistance. With this structure, the parasitic resistance between the source electrode 5 and the gate electrode 6 and between the gate electrode 6 and the drain electrode 7 can be reduced. Furthermore, variations in parasitic resistance can be suppressed to an extremely small value.

The impurities to be ion-implanted may be any impurities serving as donor impurities in the second compound semiconductor layer 4 and the InAs layer 3. Particularly, S, Se, Sn, Si and the like are suitable. The concentration of the injected impurities is 3 × 10 ¹⁷ / cm ³ to 1 × 10
¹⁹ / cm ³ is the preferred range.

The gate electrode 6, as shown in FIG.
Although it may be formed directly on the compound semiconductor layer 4 of FIG. 3, it may be formed on another layer formed on the second compound semiconductor layer 4.

Modification 8 As shown in FIG. 13, under the gate electrode 6, following the second compound semiconductor layer 4, InA is exposed without being exposed to the atmosphere.
A gate electrode lower conductive layer 61 made of a semiconductor having a narrow bandgap such as s and InSb is formed. In this structure,
There is no oxide film at the interface between the gate electrode lower conductive layer 61 and the second compound semiconductor layer 4, and an ideal interface with few interface states can be obtained. On the other hand, the gate electrode 6 and the gate electrode lower conductive layer 61
Since an ohmic junction is formed with the
Due to the barrier between the second compound semiconductor layer 4 and the second compound semiconductor layer 4, the gate electrode 6 and the second compound semiconductor layer 4 are equivalent to a Schottky junction.

Modification 9 As shown in FIG. 14, the second compound semiconductor layer 4 is formed at a portion where the second compound semiconductor layer 4 is joined to the gate electrode 6.
The withstand voltage of the FET can be increased by forming the recess structure 12 on the above. The recess structure 12 is not limited to the case where the gate electrode 6 is arranged in contact with the second compound semiconductor layer 4, and may be formed in another layer where the gate electrode 6 is arranged.

Modification with Insertion Layer, Protective Film, etc. Modification 10 In the FET of the present invention, the first compound semiconductor layer 2 is directly laminated on the substrate 1, and the InAs layer 3 is formed thereon. Even with such a structure, a good quality InAs layer 3 can be formed. However,
In the FET according to the present invention, it is possible to improve the characteristics of the FET by inserting another semiconductor layer between the layers. Figure 15
Various insertion layers will be explained using the example shown in (a).

The FET shown in FIG.
And a second semiconductor insertion layer 21 between the first compound semiconductor layer 2 and the InAs layer 3.
22 and a third semiconductor insertion layer 41 between the InAs layer 3 and the second compound semiconductor layer 4. By inserting these semiconductor insertion layers, it is possible to reduce the hole current and improve the conductance of the transistor.

The second and third semiconductor insertion layers 22 and 41 are
In order to more efficiently trap conduction electrons in the InAs layer 3, the InAs layer 3 is arranged in contact with the InAs layer 3 which is an electron transit layer. Therefore, a semiconductor having a bandgap wider than that of InAs is selected, and the electron affinity of the semiconductor used for the semiconductor insertion layers 22 and 41 is smaller than that of the InAs layer 3, and the electron affinity and the bandgap are not equal to each other. A semiconductor layer whose sum is larger than the sum of the electron affinity of InAs layer 3 and the band gap is preferable. Among them, AlSb, AlGaSb and InAlAs are particularly suitable.

Each of the inserted semiconductor layers 21, 22 and 41 is
Since the lattice constant is different from that of InAs of the InAs layer 3, dislocation occurs due to lattice mismatch when the thickness is larger than a specific film thickness. Therefore, the characteristics of the InAs layer 3 may deteriorate.
Therefore, the thickness of the semiconductor insertion layers 21, 22 and 41 is preferably within the range of the film thickness at which dislocations due to such lattice mismatch do not occur, that is, the critical film thickness. The critical film thickness varies depending on the material of the semiconductor to be inserted, but in the case of AlSb, it becomes about 160Å in combination with the InAs layer 3.

Further, as shown in FIG. 15B, the insulator layer 62 may be formed in contact with the lower portion of the gate electrode 6.

Modification 11 In the present invention, the first compound semiconductor layer 2 and the second compound semiconductor layer 2
The semiconductor used as the compound semiconductor layer 4 is GaAs or
Easier to oxidize than semiconductors such as InAs. In order to reduce the change in FET characteristics over time due to such oxidation of the compound semiconductor layer, it is preferable to form a layer for preventing oxidation in addition to the passivation layer used in a normal semiconductor device.

First, when the fourth semiconductor insertion layer 42 as shown in FIG. 15A is formed on the second compound semiconductor layer 4, the second compound semiconductor layer 4 is exposed to the atmosphere. Since it is protected, the problem of characteristic deterioration due to oxidation is less likely to occur. The fourth semiconductor insertion layer 42 may be a semiconductor that is difficult to oxidize, but GaAs, GaSb, and GaAsSb are particularly preferable. A suitable thickness is 50 to 1,000 Å. Especially, 100 Å ~ 700 Å
Is the optimum thickness.

Modification 12 In the FET, the source-drain current is controlled by the voltage applied to the gate electrode 6. Therefore, it is necessary to separate the InAs layer 3 into an electrically inactive region and an active region 11 to be the electron transit layer of the FET. As this separating method, there are a method of forming a mesa structure and a method of making the portions other than the active region 11 non-conductive.

When the active region 11 is formed by the mesa structure, liquid etching or gas etching based on acid or alkali is used.

On the other hand, the second compound semiconductor layer 4 and In
To make the As layer 3 non-conductive, a usual method such as ion implantation or electron beam irradiation is used. Unlike the mesa structure, the structure in which the unnecessary portion is made non-conductive does not have a cross section, and thus problems such as gate leakage and oxidation are unlikely to occur.

In the mesa structure, that is, in the structure in which the unnecessary portion is removed by etching and only the necessary portion is left on the plateau, the following inconvenience may occur. That is,
The surfaces of the first compound semiconductor 2 and the second compound semiconductor layer 4 that are in contact with the atmosphere may be oxidized, leading to deterioration of transistor characteristics. Further, the InAs layer 3 exposed in the cross section of the mesa structure makes ohmic contact only by contacting the gate electrode 6, so that a leak current from the gate electrode 6 to the InAs layer 3 may occur.

The side wall 9 shown in FIG. 16 (b) is for preventing such inconvenience. The side wall 9 is formed of an insulating or semi-insulating material so that the InAs layer 3 and the gate electrode 6 do not come into direct contact with each other. Thereby, the leak current from the gate electrode 6 to the InAs layer 3 can be prevented. Moreover, since the cross section of the mesa structure is covered, the first compound semiconductor layer 2 and the second compound semiconductor layer 4 are formed.
It is also possible to prevent the oxidation of

FIG. 16 (a) is a plan view of the FET, and FIG. 16 (b) is FIG.
16A is a sectional view taken along line AB in FIG. 16A, and FIG. 16C is a sectional view taken along line CD in FIG. 16A. These figures show that the sidewall 9 is formed so as to cover the cross section of the mesa structure, and the InAs layer 3 and the gate electrode 6 are not in direct contact with each other.

The material of the side wall 9 is an insulating semiconductor, or SiN _x , Si which is usually used as a protective film for a semiconductor.
O ₂ , SiO _X N _y , Al ₂ O ₃ etc. are preferable. Among them, SiN _X , SiO _X N _y
Are particularly suitable.

Modification 13 FIG. 17 shows the result of oxidation of the first and second compound semiconductor layers.
This is an example in which the first protective film 81 and the second protective film 82 are provided on the surface of the element in order to reduce the deterioration of the characteristics of the FET.
The first protective film 81 is on the upper surface of the first compound semiconductor layer 2,
In addition, SiN _X , Si is formed on the portion where the active region 11 is not formed.
It was formed using an insulator such as O ₂ and Al ₂ O ₃ . Further, the second protective film 82 is formed on the upper surface of the second compound semiconductor layer 4 in the active region 11 or the upper surface of the fourth semiconductor insertion layer 42 except the electrodes 5, 6 and 7. First protective film
The 81 and the second protective film 82 may be formed of the same film, but may be formed separately. In addition, the first protective film 81, the second
The protective film 82 and the side wall 9 can be formed by removing the same insulating film by anisotropic etching using reactive ion etching. Therefore, there is also an advantage that the process becomes easy.

Other General Application Structures Many FETs of the present invention can be integrated on the same substrate. Further, a transistor in which the substrate and the electron transit layer are made of the same semiconductor material may be formed on the same substrate. Particularly, the InAs-F of the present invention characterized by high-speed operation
A structure in which ET and GaAs-FET formed on the same substrate are integrated is preferable.

[Prototype Example 1] A prototype example of an FET in which the second compound semiconductor layer 4 shown in FIG. 8A is used as an insulating barrier layer will be described.

A mirror-polished (100) surface semi-insulating GaAs substrate having a thickness of 350 μm was used as the substrate 1. On the substrate 1, as the first compound semiconductor layer 2, a non-doped Al _0.8 Ga _0.2 As _0.14 Sb _0.86 layer lattice-matched with InAs was doped with 8,000 Å, and Si as a donor impurity was doped with 2 × 10 ¹⁷ / cm ³ . InAs layer 3 is 700 Å, then as the second compound semiconductor layer 4,
Non-doped Al _0.8 Ga _0.2 As _0.14 Sb _0.86 layers were sequentially formed by 400 Å by molecular beam epitaxy. next,
An unnecessary portion of the laminated thin film formed on the GaAs substrate 1 was removed by a photolithography method, and a resist pattern for forming an electron transit portion of the device was formed. Then H ₂ SO
Etching was performed with a ₄ : H ₂ O ₂ based etching solution to form the active region 11 having a mesa structure. Then, after forming a resist pattern, the AlGaAsSb under the source electrode 5 and the drain electrode 7 is etched with an NH ₄ OH: H ₂ O ₂ based etching solution.
Only the layer 4 was etched to expose the surface of the InAs layer 3. Subsequently, the AuGe (Au: Ge = 88: 12) layer 5 was formed by the vacuum evaporation method.
1,71 to 2,000 Å, Ni layer 52, 72 to 500 Å, Au layer 53, 73 to
3,500Å Continuous vapor deposition. Then lift off and do 3 layers 5
A pattern of the source electrode 5 and the drain electrode 7 made of 1, 52, 53 and 71, 72, 73 was formed to obtain an ohmic contact with the InAs layer 3. Further, after forming a resist pattern for the gate electrode 6, 3,000 Å Al was vapor-deposited on the entire surface of the wafer and lift-off was performed to form the gate electrode 6. Then, dicing was performed to separate into individual elements. Thus, the FET of the present invention shown in FIG. 8 (a) was manufactured. Also, the device was packaged with lead wires attached by a normal assembly process.

[Prototype Example 2] The FET of the present invention shown in FIG. 8B will be described with reference to a prototype example. In this prototype example, the second compound semiconductor layer 4 is doped with a donor impurity and functions as an electron supply layer to the InAs layer 3, and the InAs layer 3 is intentionally not doped with impurities. On the semi-insulating GaAs substrate 1 having a mirror-polished (100) surface of 350 μm, the first compound semiconductor layer 2 was a non-doped lattice-matched InAs layer.
Al _0.8 Ga _0.2 As _0.14 Sb _0.86 layer was 8,000 Å, InAs layer 3 not doped with donor impurities was 700 Å, and then Se was doped as 2 × 10 ¹⁸ / cm ³ as the second compound semiconductor layer 4.
400 Å Al _0.8 Ga _0.2 As _0.14 Sb _0.86 layers were sequentially formed by molecular beam epitaxy. After that, the FET shown in FIG. 8B was manufactured through the same steps as in the prototype example 1.

[Prototype 3] The FET of the present invention shown in FIG. 8 (c) will be described with reference to a prototype. In this prototype, both the second compound semiconductor layer 4 and the InAs layer 3 are doped with donor impurities. The conduction electrons in the InAs layer 3 are composed of electrons supplied from the second compound semiconductor layer 4 and electrons due to donor impurities in the InAs layer 3.

On the mirror-polished (100) -plane semi-insulating GaAs substrate 1 having a thickness of 350 μm, as the first compound semiconductor layer 2, non-doped Al _0.8 Ga _0.2 As _0.14 lattice-matched to InAs was used.
Sb _0.86 layer is 8,000 Å, Se as donor impurity is 5 × 10 ¹⁷
/ cm ³ doped InAs layer 3 is 700 Å, then Se as the second compound semiconductor layer 4 is 5 × 10 ¹⁷ / cm ³ doped Al
400 Ga of _0.8 Ga _0.2 As _0.14 Sb _0.16 layers were sequentially formed by molecular beam epitaxy. After that, the FET shown in FIG. 8 (c) was manufactured through the same steps as in the prototype example 1.

[Prototype Example 4] In the FET of the present invention shown in FIG. 3, a prototype example of a quantum effect FET in which the InAs layer 3 has a thickness of 100 Å and a quantum level is formed in the InAs layer 3 will be described. To do. In
The As layer 3 is doped with Si as a donor impurity.

A mirror-polished (100) -plane semi-insulating GaAs substrate having a thickness of 350 μm was used as the substrate 1, and the first substrate was formed on the substrate 1.
As the compound semiconductor layer 2, the non-doped Al _0.8 Ga _0.2 As _0.14 Sb _0.86 layer lattice-matched to InAs is 8,000 Å, and the InAs layer 3 doped with Si as a donor impurity is 2 × 10 ¹⁷ / cm ³ 10
Then, a non-doped Al _0.8 Ga _0.2 As _0.14 Sb _0.16 layer of 400 Å was sequentially formed as the second compound semiconductor layer 4 by the molecular beam epitaxy method. Hereafter, Prototype Example 1
The quantum effect type FET as shown in FIG.

[Prototype Example 5] An example of the prototype of the FET having the structure shown in FIG. 18 will be described. In this prototype example, the second compound semiconductor layer 4 is doped with a donor impurity and is used as an electron supply layer to the InAs layer 3 not doped with the donor impurity. Further, GaAsSb is formed as the fourth semiconductor insertion layer 42.

On the mirror-polished (100) -plane semi-insulating GaAs substrate 1 having a thickness of 350 μm, as the first compound semiconductor layer 2, non-doped Al _0.7 Ga _0.3 As _0.15 lattice-matched to InAs was formed.
An Sb _0.85 layer is formed at 8,000 Å, then an InAs layer 3 not doped with impurities is 200 Å, and 500 Å Al is doped as a second compound semiconductor layer 4 with a donor impurity Se.
_0.7 Ga _0.3 As _0.15 Sb _0.85 layers were sequentially formed by the molecular beam epitaxy method. Finally, the fourth semiconductor insertion layer 4
2 as undoped GaAs _0.15 Sb _0.85
A layer of 200 Å was formed. Next, an unnecessary portion of the laminated thin film formed on the GaAs substrate was removed by photolithography to form a resist pattern for manufacturing the active region 11. Then, etching was carried out with an H ₃ PO ₄ : H ₂ O ₂ based etching solution to form an active region 11 having a mesa structure. Next, after forming 3,000 Å SiN by plasma CVD method,
A portion other than the side wall 9 was etched and removed using a reactive ion etching device. Next, after forming a resist pattern for the ohmic electrode, GaAsSb (fourth semiconductor insertion layer 42) and AlGaAsSb (second semiconductor insertion layer 42) under the source electrode 5 and the drain electrode 7 are formed by an NH ₄ OH: H ₂ O ₂ based etching solution. Only the compound semiconductor layer 4) of 1) was etched to expose the surface of the InAs layer 3. Furthermore, Ti is 1,500 by the vacuum deposition method.
Å, Au was continuously deposited by 2,500Å. Next, lift-off was performed to form the source electrode 5 and the drain electrode 7. Further, a resist pattern for the gate electrode 6 is formed, and NH ₄ OH is used.
: The H ₂ O ₂ etchant, a fourth semiconductor insert layer 42
After etching GaAsSb which is, Al is vapor-deposited on the entire surface,
The gate electrode 6 was formed by the lift-off method. Then,
Dicing was performed to separate the individual elements. In this way, the FET shown in Fig. 18 was manufactured.

[Prototype 6] Another prototype of the present invention shown in FIG. 19 will be described. This prototype example shows the second compound semiconductor layer 4
Both the InAs layer 3 and the InAs layer 3 are doped with a donor impurity, and conduction electrons generated from the donor impurities in the InAs layer 3 and conduction electrons supplied from the second compound semiconductor layer 4 exist in the InAs layer 3. There is. In addition to the second semiconductor insertion layer 22, the third semiconductor insertion layer 41, and the fourth semiconductor insertion layer 42, the contact layers 50 and 70, the first protective film 81, the second protective film 82, and the sidewall 9 are also included. Is also formed.

First, 350 μm-thick mirror-polished (100)
On the surface of the semi-insulating GaAs substrate 1, the first compound semiconductor layer 2
As a non-doped Al _0.7 Ga _0.3 As lattice-matched to InAs
10,000Å a _0.15 Sb _0.85 layer, a second semiconductor insert layer 22, 20 Å and Al _0.7 Ga _0.3 Sb layer, Si-doped, the InAs layer 3 of the carrier concentration of ^{5 × 10 17 / cm 3 500} Å, respectively Sequential growth was performed by the molecular beam epitaxy method. Then, the third
After the Al ₀₇ Ga _0.3 Sb layer is grown to 20 Å as the semiconductor insertion layer 41 of, the second compound semiconductor layer 4 is made of Se of 1 × 10
^{An 18} _0.7 cm ³ doped Al _0.7 Ga _0.3 As _0.15 Sb _0.85 layer was formed. Further, as a fourth semiconductor insertion layer 42 on the layer, Ga
As _0.15 Sb _0.85 100 Å layer, contact layers 50, 70 In
The As layer was grown to 100 Å. Next, an unnecessary portion of the laminated thin film formed on the GaAs substrate 1 was removed by photolithography, and a resist pattern for forming the active region 11 was formed. Next, etching was performed using a H ₂ SO ₄ : H ₂ O ₂ based etching solution to form the active region 11 having a mesa structure. Next, 2,000 Å SiN was deposited on the entire surface by plasma CVD method.
Then, the first protective film 81, the second protective film 82, and the side wall 9 were simultaneously formed. After forming a resist pattern, anisotropic etching using a reactive ion etching device was performed to etch SiN in the portion where the source electrode 5 and drain electrode 7 are formed, leaving SiN in the sidewall 9 portion. .. Furthermore, by the vacuum evaporation method, AuGe (Au:
Ge = 88:12) was continuously deposited by 2,000 Å, Ni by 500 Å and Au by 3,500 Å. Next, lift-off was performed to form a pattern of the source electrode 5 and the drain electrode 7. After that, annealing is performed to source and drain electrode metals and the electron transit layer 3
I got an ohmic contact with. Next, a resist pattern of the gate electrode 6 is formed, and then anisotropic etching is performed using a reactive ion etching apparatus to remove the side wall 9 portion.
With the SiN left, etching of the SiN in the portion where the gate electrode 6 is formed was performed. Furthermore, using this pattern,
NH ₄ OH: H ₂ O ₂ system etching solution, InAs layer 50 on the surface,
The 70 and the GaAsSb layer 42 were etched to form the recess structure 12 in the AlGaAsSb layer which is the second compound semiconductor layer 4. Next, 3,000 Å Al was vapor-deposited on the entire surface of the wafer and lift-off was performed to form a gate electrode 6 having a gate length of 1.0 μm. Then, dicing was performed to separate into individual elements. In this way, the FET shown in Fig. 19 was manufactured.

[Prototype Example 7] Another prototype example shown in FIG. 20 will be described. In this prototype example, part of In in the InAs layer 3 is replaced with Ga to form an electron transit layer, and the film thickness thereof is set to 70Å. Therefore, conduction electrons form a quantum level. Also,
The element isolation is performed by the region 10 formed by ion implantation.

The p of the (100) surface, which was mirror-polished with a thickness of 400 μm, was used.
On the Si-type Si substrate 1, the first semiconductor insertion layer 21 was formed by molecular beam epitaxy to form undoped Ga with a thickness of 3,000 Å.
After forming the As layer, the first compound semiconductor layer 2
Undoped Al _0.7 Ga _0.3 As _0.15 Sb _0.85 lattice-matched to As
InAs with 5,000 Å layers and Ga replaced 9% of In in InAs
Layer 3 70 Å, then undoped Al _0.7 Ga _0.3 As _0.15 Sb
_{The 0.85} layer is 300 Å as the second compound semiconductor layer 4, and finally the GaAs _0.15 Sb _0.85 layer is 100 as the fourth semiconductor insertion layer 42.
Å, each formed. Further, as the second protective film 82,
A 1,000Å SiN layer was grown on the entire surface by plasma CVD to cover the substrate surface. Next, a resist pattern for forming the active region 11 of the FET is formed, and then protons are ion-implanted on the entire surface to make the unnecessary portion 10 a non-conductor (high resistance).
did.

The source electrode 5 and the drain electrode 7 were formed as follows. After forming the resist pattern,
After partially removing SiN by reactive ion etching, AuGe (Au: Ge = 88: 12) 2.00 by vacuum deposition method
0 Å, Ni was 500 Å and Au was 3,500 Å continuous vapor deposition. Next, lift-off was performed to form a pattern of the source electrode 5 and the drain electrode 7. Then, annealing was performed to obtain ohmic contact between the electrode metal and the electron transit layer. Next, after forming the resist pattern for the gate electrode 6, the SiN is partially removed by reactive ion etching, and then 500 Å of Ti, 500 Å of Pt, and 1,000 Å of Au are continuously deposited on the entire surface of the wafer, and liftoff is performed. Then, the gate electrode 6 was formed. Finally, dicing was performed to separate the individual elements. Thus, the element of the present invention shown in FIG. 20 was manufactured. In addition, this element has a lead wire attached by a normal assembly process,
Packaged.

[Prototype Example 8] The FET of the present invention shown in FIG. 21 will be described with reference to a prototype example. Mirror-polished with a thickness of 350 μm
A non-doped GaAs layer having a thickness of 3,000 Å was formed on a (100) plane semi-insulating GaAs substrate by a molecular beam epitaxy method to obtain a substrate 1 of the present invention. Next, 1,500 Å non-doped AlAs _0.15 Sb _0.85 layer 2 lattice-matched to InAs, 700 Å non-doped InAs layer 3, and then non-doped AlAs
_{A 0.15} Sb _0.85 layer 4 was formed. Next, an unnecessary portion of the laminated thin film formed on the GaAs substrate 1 was removed by a photolithography method to form a resist pattern for manufacturing the active region 11 of the FET. Next, mesa etching was performed using an H ₂ SO ₄ : H ₂ O ₂ based etching solution to remove unnecessary portions. Then, after forming the resist pattern, by vacuum evaporation method, 2,000 Å of AuGe (Au: Ge = 88: 12) and 500 Å of Ni,
Au was continuously vapor-deposited at 3,500 Å. Next, lift-off was performed to form patterns of the source electrode 5 and the drain electrode 7. After that, annealing is performed at 450 ° C. for 5 minutes in an electric furnace in a nitrogen atmosphere to form the source electrode 5 and the drain electrode 7 and the InAs layer 3
I got an ohmic contact with. Furthermore, after forming the resist pattern of the gate electrode 6, 3,000Å over the entire surface of the wafer.
Al was evaporated and lifted off to form a gate electrode 6 having a gate length of 1.0 μm. Finally, a SiN protective film was formed on the entire surface by the plasma CVD method using silane gas and ammonia gas. And to open a window in the electrode part,
After forming the desired resist pattern, reactive ion etching was used to open a window in the electrode portion for bonding. Then, dicing was performed to separate into individual elements. Thus, the element of the present invention shown in FIG. 21 was manufactured. Also, the device was packaged with lead wires attached by a normal assembly process.

In the FET of the present invention, due to the high electron mobility of InAs, the cutoff frequency is also large, and compared with the field effect transistor of GaAs of the conventional structure, if the gate length is the same, it is superior in high speed operation. Do you get it.

[Prototype 9] The FET of the present invention shown in FIG. 21 will be described with reference to another example. A non-doped GaAs layer having a thickness of 3,000 Å was formed on a (100) semi-insulating GaAs substrate having a thickness of 350 μm and mirror-polished by the molecular beam epitaxy method to obtain a substrate 1. Next, undoped AlAs _0.15 Sb _0.85 layer 2 lattice-matched to InAs is 1,500 Å and InAs layer 3 is 700
Å Then, AlAs _0.15 Sb doped with Si at 1 × 10 ¹⁸ / cm ³
_0.85 Layer 4 was formed. After that, in the same manner as in Prototype Example 8,
An element of the present invention shown in 21 was manufactured.

[Prototype 10] The FET of the present invention shown in FIG. 21 will be described with reference to another example. A non-doped GaAs layer having a thickness of 3,000 Å was formed on a (100) semi-insulating GaAs substrate having a thickness of 350 μm and mirror-polished by the molecular beam epitaxy method to obtain a substrate 1. Next, 500 Å of undoped AlAs _0.15 Sb _0.85 layer 2 lattice-matched to InAs was doped with Si,
Carrier concentration 1 × 10 ¹⁷ / cm ³ , electron mobility 14,000 cm ² / v ・ se
The InAs layer 3 of c was 700 Å, and then the AlAs _0.15 Sb _0.85 layer 4 doped with Si at 1 × 10 ¹⁸ / cm ³ was formed. After that, the device of the present invention shown in FIG. 21 was manufactured in the same manner as in Prototype Example 8.

[Prototype Example 11] The FET of the present invention shown in FIG. 21 will be described with reference to another prototype example. A non-doped GaAs layer having a thickness of 3,000 Å was formed on a (100) semi-insulating GaAs substrate having a thickness of 350 μm and mirror-polished by the molecular beam epitaxy method to obtain a substrate 1. Then, undoped AlAs _0.15 Sb _0.85 layer 2 lattice-matched to InAs was deposited at 1,500 Å and InAs layer 3 was deposited at 100
Å Then, a non-doped AlAs _0.15 Sb _0.85 layer 4 was formed. After that, the device of the present invention shown in FIG. 21 was manufactured in the same manner as in Prototype Example 8. Also, the device was packaged with lead wires attached by a normal assembly process.

[Prototype Example 12] The FET of the present invention shown in FIG. 22 will be described by way of a prototype example. 350 μm thick mirror-polished (1
A 3,000 Å non-doped GaAs layer having a thickness of 3,000 Å was formed on the (00) plane semi-insulating GaAs substrate by the molecular beam epitaxy method to obtain a substrate 1. Next, In _0.53 Ga _0.47 As layer 21 with 500 Å, InAs
After forming 500 Å of undoped Ga _0.7 Al _0.3 As _0.15 Sb _0.85 layer 2 that is lattice-matched to 100 Å of undoped InAs layer 3
1, Si-doped 500 Å InAs layer 32, and 100 Å
Forming an InAs layer 3 composed of the non-doped InAs layer 33 of
Further, a non-doped AlAs _0.15 Sb _0.85 layer 4 was formed. Finally, an InAs layer of 5 × 10 ¹⁸ / cm ³ Si was doped as an impurity to form the contact layers 50 and 70, 200 Å. Next, an unnecessary portion of the laminated thin film formed on the GaAs substrate 1 was removed by a photolithography method to form a resist pattern for manufacturing the active region 11 of the FET. Then H ₂
Etching was performed with a SO ₄ : H ₂ O ₂ based etching solution to remove unnecessary portions. Then, after forming a resist pattern, AuGe (Au: Ge = 88: 12) was added to 2,000 by vacuum deposition.
0 Å, Ni was 500 Å and Au was 3,500 Å continuous vapor deposition. Next, lift-off was performed to form a pattern of the source electrode 5 and the drain electrode 7. Then, in an electric furnace in a nitrogen atmosphere, 450
Annealing was performed at 5 ° C. for 5 minutes to obtain an ohmic contact between the electrode metal and the electron transit layer. Then, after stripping the resist, in order to remove the InAs layer other than the lower part of the source electrode and the drain electrode, etching was performed with an H ₂ SO ₄ : H ₂ O ₂ based etching solution using both electrodes as a mask. Furthermore, after forming the resist pattern of the gate electrode 6, the entire surface of the wafer is
Gate length of 1.
A gate electrode 6 of 0 μm was formed. Finally, the SiN was formed by the plasma CVD method using silane gas and ammonia gas.
Was formed on the entire surface. Then, to form a window in the electrode portion, after forming a desired resist pattern, the electrode portion was opened for bonding by reactive ion etching. Then,
Dicing was performed to separate the individual elements. Thus, the element of the present invention shown in FIG. 22 was manufactured. Also, the device was packaged with lead wires attached by a normal assembly process.

As described above, the device characteristics obtained by the prototypes are extremely desirable. An example thereof is shown in FIG.

FIG. 23 is a graph showing the results of measuring the relationship between the source-drain voltage and the drain current at room temperature when the gate voltage of the FET of prototype example 5 was changed. Unlike the characteristics of the conventional InAs-FET shown in FIG. 2, the gate electrode 6
It can be seen that the drain current is accurately controlled by the voltage applied to, and that it has good FET characteristics with little leakage current. In addition, similarly good results were obtained in other prototypes of the present invention.

[0130]

As described above, according to the present invention, the InAs layer having the electron mobility and the electron saturation speed higher than that of GaAs is used as the electron transit layer, so that the same gate length can be operated up to a high frequency. it can. Therefore, at the same operating frequency, the FET of the present invention may have a gate length about twice as long as that of the conventional GaAs-HEMT. Therefore, the processing of the gate becomes extremely easy. There is a great difference in precision between the processing of 0.6 μm or more, which allows photolithography by a stepper, and the processing of smaller dimensions, and the process is complicated. According to the present invention, it is possible to easily manufacture an element that operates at an ultrahigh frequency by a photolithography process using ultraviolet light. Further, when the gate length is the same as the conventional one, the high electron mobility of InAs makes it possible to operate at a high frequency twice as high as that of GaAs. In addition, the process yield is good and mass production is possible.

INDUSTRIAL APPLICABILITY The present invention contributes to speeding up, cost reduction and multi-functionalization of a satellite transmission / reception amplification element and a high speed data transfer element. Further, it becomes easy to manufacture a high-frequency element using a fine processing technique, and a higher-speed element can be manufactured.

[Brief description of drawings]

FIG. 1 shows the conventional GaSb disclosed in Japanese Patent Laid-Open No. 60-5572 and
It is a band diagram of a FET with a laminated structure of AlSb, (a) is Ga
A band diagram in the case where Sb and InAs are directly bonded, (b) is a layered structure of FET, and (c) is a band diagram in the layered structure of (b).

[FIG. 2] (a) is a cross-sectional view of a conventional InAs-FET shown in IEEE EDL Vo.11, No.11, p.526 (1990), and (b) is its IV.
It is a graph which shows a characteristic.

FIG. 3 is a cross-sectional view showing the configuration of an embodiment of an FET according to the present invention.

FIG. 4 is a graph showing electron mobility of InAs when AlGaAsSb was formed on a GaAs substrate and used as a buffer layer of the InAs layer.

FIG. 5 is a phase diagram showing the relationship between the composition ratio, the band gap, and the lattice constant of AlGaAsSb, which is a quaternary compound semiconductor, and is quoted from JJAP Vol.19 p.1675 1980.

FIG. 6 is a graph showing calculated values of the critical film thickness of the InAs layer with respect to the size of the lattice mismatch between the first compound semiconductor layer functioning as a buffer layer and InAs.

FIG. 7 is a graph showing the calculation result of the relationship between the film thickness of the InAs layer and the mutual conductance of the FET.

8A and 8B are cross-sectional views showing the configurations of three types of modified examples of the FET according to the present invention, which are classified according to the difference in the doping position of the donor impurity, and (a) is the donor in the second compound semiconductor layer 4. A cross-sectional view of an FET as a modified example 1 of the above embodiment, in which an Ins layer, which is an electron transit layer, is doped with impurities and is used as an insulating barrier layer, and (b) is a donor impurity doped into the InAs layer. Not shown, but a cross-sectional view of an FET as a modified example 2 of the above embodiment in which the donor impurity is doped only in the second compound semiconductor layer to form an electron supply layer to the InAs layer, (c) shows the second compound semiconductor layer A modified example of the above embodiment in which both of the InAs layer and the InAs layer are doped with a donor impurity, and the conduction element generated from the impurities in the InAs layer and the conduction electron supplied from the second compound semiconductor layer 4 are used as current carriers. It is sectional drawing of FET as 3.

FIG. 9 is a diagram showing a quantum level formed in an electron transit layer in a FET as a modified example 4 of the above embodiment.

FIG. 10 shows an InAs layer via a second compound semiconductor layer,
An ohmic contact with each of the source and drain electrodes was taken,
It is sectional drawing which shows the structure of FET as the modification 5 of the said Example.

FIG. 11 is a FE as a modified example 6 of the above embodiment in which a contact layer is arranged under the source electrode and the drain electrode.
FIG. 3 is a cross-sectional view showing the structure of T 1.

FIG. 12 is a cross-sectional view showing the structure of a FET as a modified example 7 of the above-mentioned embodiment, in which donor impurities are ion-implanted into the periphery except the lower part of the gate electrode using the gate electrode as a mask.

FIG. 13 is an FE as a modified example 8 of the above embodiment, in which a conductive layer is inserted between the second compound semiconductor layer and the gate electrode.
FIG. 3 is a cross-sectional view showing the structure of T 1.

FIG. 14 is a cross-sectional view showing the structure of a FET as a modified example 9 of the above embodiment, in which the gate electrode portion has a recess structure.

FIG. 15: FE with various spacer layers added to the above example
It is sectional drawing which shows the structure of T, (a) is modification 10 and 11 of the said Example which arrange | positioned the 1st-4th semiconductor insertion layer.
FIG. 10B is a cross-sectional view of an FET as a tenth modification of the above-described embodiment, in which an insulating layer is arranged below the gate electrode.

FIG. 16 is a diagram showing the structure of an FET as a modified example 12 of the above embodiment, in which elements are separated by mesa etching and insulating side walls are formed on the side surfaces of the mesa cross section, (a) is a plan view, (b) is a sectional view taken along line AB, and (c) is a sectional view taken along line CD.

FIG. 17 is a cross-sectional view showing a structure of a FET as a modified example 13 of the above-mentioned embodiment, in which an antioxidant layer is added to the above-mentioned embodiment.

FIG. 18 is a cross-sectional view showing the structure of a FET according to prototype example 5.

FIG. 19 is a cross-sectional view showing the structure of a FET according to prototype example 6.

FIG. 20 is a cross-sectional view showing the structure of a FET according to Prototype Example 7.

FIG. 21 is a cross-sectional view showing the structures of FETs according to prototype examples 8 to 11.

22 is a cross-sectional view showing the structure of an FET according to Prototype Example 12. FIG.

FIG. 23 is a graph showing IV characteristics of the FET according to the prototype example 5.

[Explanation of symbols]

1 substrate 2 first compound semiconductor layer 3 InAs layer 4 second compound semiconductor layer 5 source electrode 6 gate electrode 7 drain electrode 9 sidewall 10 high resistance region 11 active region 12 recess structure 21 first semiconductor insertion layer 22 Second semiconductor insertion layer 30 Quantum level in InAs layer 31, 33 Non-doped InAs layer 32 Doped InAs layer 41 Third semiconductor insertion layer 42 Fourth semiconductor insertion layer 50 Contact layer (lower part of source electrode) 51 Source electrode 5 AuGe layer 52 Source electrode 5 Ni layer 53 Source electrode 5 Au layer 61 Gate electrode lower conductive layer 62 Gate electrode lower insulator layer 70 Contact layer (Drain electrode lower portion) 71 Drain electrode 7 AuGe layer 72 Drain Ni layer of electrode 7 73 Au layer of drain electrode 74 Donor impurities partially introduced under the source electrode 75 Region (ion side) where ions are implanted using the gate as a mask 81 First protective film 82 2 of the protective layer 101 GaAs substrate 102 GaSb layer 103 InAs layer 104 AlSb layer

Continuation of the front page (31) Priority claim number Japanese Patent Application No. 3-192410 (32) Priority Day Hei 3 (1991) August 1 (33) Priority claim country Japan (JP)

Claims (1)

[Claims] 1. A substrate having a lattice constant different from InAs, disposed on the surface of the substrate, and substantially lattice-matched to InAs.
And Al _x1 Ga _1-x1 As _y1 Sb _1-y1 , {0.21 ≦ x1 ≦ 1.0, 0.02 ≦ y1 ≦ 0.22}, Al _x2 In _1-x2 As _y2 Sb _1-y2 , {0.34 ≦ x2 ≦ 1.0, 0.09 ≦ y2 ≤ 0.79}, Al _x3 In _1-x3 P _y3 Sb _1-3y , {0.07 ≤ x3 ≤ 1.0, 0.06 ≤ y3 ≤ 0.72}, and Al _x4 Ga _1-x4 P _y4 Sb _1-y4 , {0.13 ≤ x4 ≦ 1.0, 0.01 ≦ y4 ≦ 0.18}, and a first compound semiconductor layer formed of at least one film selected from the thin films having a composition defined by: and disposed on the first compound semiconductor layer. An InAs layer formed on the InAs layer, a second compound semiconductor layer disposed on the InAs layer, substantially lattice-matched to InAs of the InAs layer, and having a band gap larger than that of the InAs layer; At least one pair of ohmic electrodes that are in ohmic contact with each other, and at least one gate electrode that is disposed between the pair of ohmic electrodes and is disposed on the second compound semiconductor and that controls the current in the InAs layer. Field effect transistor and having and.