JP4243593B2 - HETERO FIELD EFFECT TRANSISTOR, MANUFACTURING METHOD THEREOF, AND TRANSMITTING / RECEIVING APPARATUS EQUIPPED - Google Patents

Description

  The present invention relates to a hetero field effect transistor using a gallium indium arsenide nitride epitaxial wafer, a manufacturing method thereof, and a transmission / reception apparatus using the hetero field effect transistor.

  A hetero field effect transistor such as a high electron mobility transistor (HEMT) is a compound semiconductor device using a two-dimensional electron gas formed in a hetero structure.

FIG. 13 shows a HEMT having an InAlAs carrier supply layer / InGaAs channel layer / InAlAs buffer layer formed on an InP substrate as a first conventional example of such a HEMT. In FIG. 13, reference numeral 1 denotes an electrode metal, reference numeral 2 denotes an n ⁺ -InGaAs cap layer, reference numeral 3 denotes an n-InAlAs carrier supply layer, reference numeral 4 denotes an i-InAlAs spacer layer, reference numeral 5 denotes an i-InGaAs channel layer, reference numeral 6 Is an i-InAlAs buffer layer, and 7 is a semi-insulating InP substrate (SI-InP substrate). Since this HEMT uses InGaAs as the channel layer 5, the HEMT exhibits excellent high-frequency characteristics because of its high electron transport characteristics as compared with HEMTs using GaAs for the channel layer. In particular, this conventional example is characterized in that an InAs layer 8 having a thickness of 1 to 7 nm is inserted into the InGaAs channel layer 5 at a position 0 to 6 nm away from the InAlAs spacer layer 4 (for example, Patent Document 1). reference).

FIG. 14 shows a HEMT having a GaInNAs channel layer formed on a GaAs substrate as a second conventional example. In this HEMT, an undoped GaAs buffer layer 12 having a thickness of 0.5 μm is provided on a semi-insulating GaAs substrate 11, and an undoped GaInNAs channel layer 13 having a thickness of 15 nm is formed on the buffer layer 12. Furthermore, an n-type AlGaAs carrier supply layer 14 is formed to a thickness of 50 nm via an undoped AlGaAs spacer layer 16 having a thickness of 2 nm, and an electrode 18 is formed on the AlGaAs carrier supply layer 14 by vapor deposition. Yes. Both the Al composition of the spacer layer 16 and the carrier supply layer 14 is 0.28 (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 5-36726 JP 2000-164852 A

  However, in the first conventional example, when the InAs layer 8 is inserted as described above, lattice mismatch occurs, and defects occur beyond the critical film thickness. For this reason, the thickness of the channel layer cannot be increased beyond the critical film thickness, and sufficient carrier density cannot be realized, so that the characteristic improvement is insufficient.

  On the other hand, in the second conventional example, in order to solve the characteristic problem caused by the difficulty of lattice matching of the InGaAs layer to the GaAs substrate when the InGaAs layer is formed on the GaAs substrate 11, the channel layer N is introduced into InGaAs constituting the structure. In such a second conventional example, the channel layer 13 made of GaInNAs is lattice-matched to the GaAs substrate 11, so that the characteristics are certainly improved as compared with the case where the InGaAs channel layer is formed on the GaAs substrate 11. Yes. However, characteristics exceeding the first conventional example in which an InGaAs channel layer is formed on an InP substrate have not been realized.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a hetero field effect transistor capable of improving electron mobility and thereby enabling high-speed operation, a manufacturing method thereof, and a transmitting / receiving device. Yes.

In order to achieve the above object, a hetero field effect transistor according to the present invention includes a substrate, a channel layer formed on the substrate via a buffer layer, and a semiconductor having a larger band gap than the channel layer. A spacer layer formed in a heterojunction with the channel layer; and a carrier supply layer formed adjacent to the spacer layer, wherein the substrate is made of InP, and the channel layer has the chemical formula Ga _x In _{1. -x} N _y A _1-y, where A is As or Sb, the composition x is 0 ≦ x ≦ 0.2, and the composition y is 0.03 ≦ y ≦ 0.10. A compound semiconductor layer, wherein A is As, and the channel layer includes a first channel layer and a second channel layer adjacent to the first channel layer and heterojunction with the spacer layer. And Serial first channel layer formed of the compound semiconductor layer, the second channel layer is composed of InAs layer.

  x = 0 may be sufficient.

  The N concentration of the first channel layer may be lowered as it approaches the second channel layer.

  A pair of the second channel layers are formed adjacent to the upper surface and the lower surface of the first channel layer, and the pair of spacer layers are formed so as to be heterojunction with the pair of second channel layers, A pair of the carrier supply layers may be formed adjacent to the pair of spacer layers.

  0 <x may be sufficient.

  It may further satisfy 3y ≦ x ≦ 0.2.

  0.1 ≦ x ≦ 0.2 may be satisfied.

  The first channel layer may be composed of a GaInNAs / InAsMQW layer having a multiple quantum well structure in which GaInNAs layers and InAs layers, which are the compound semiconductors with 0 <x, are alternately stacked.

  The first channel layer may include an InNAs / InAsMQW layer having a multiple quantum well structure in which InNAs layers and InAs layers, which are compound semiconductors with x = 0, are alternately stacked.

In addition, a method for manufacturing a hetero field effect transistor according to the present invention includes a channel layer forming step of forming a channel layer on a substrate via a buffer layer, and a spacer layer made of a semiconductor having a larger band gap than the channel layer. A spacer layer forming step for forming a heterojunction with the channel layer; and a carrier layer forming step for forming a carrier supply layer adjacent to the spacer layer, wherein the substrate is made of InP, and the channel layer has Represented by the chemical formula Ga _x In _1-x N _y A _1-y , the A is As or Sb, the composition x is 0 ≦ x ≦ 0.2, and the composition y is 0.03 ≦ has a compound semiconductor layer is a y ≦ 0.10, a buffer layer forming step of forming the buffer layer made of InAlAs on the InP substrate, said channel layer form A step of forming a first channel layer made of InNAs on the buffer layer, and a second channel layer made of InAs on the first channel layer. 2 channel layer forming step, and in the spacer layer forming step, the spacer layer made of InAlAs may be formed on the second channel layer. With such a configuration, when the interface between the channel layer and the spacer layer is formed, N atoms and Al atoms do not exist at the same time, so that a good interface is formed.

  A transmitting / receiving apparatus according to the present invention includes the hetero field effect transistor according to claim 1 for processing a transmission signal or a reception signal.

  The present invention has the configuration as described above, and has an effect of enabling high-speed operation in a hetero field effect transistor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
{Concept of the present invention}
First, the concept of the present invention will be described.

  The hetero field effect transistor of the present invention is characterized in that GaInNAs having a composition ratio of Ga and N in a predetermined range is formed as a channel layer on an InP substrate. In the present invention, this GaInNAs includes InNAs as an embodiment when the Ga composition ratio is zero. In other words, the first conventional example has a configuration in which the Ga composition ratio of the InGaAs channel layer is set to a predetermined value and nitrogen (N) is added to the InGaAs channel layer so as to have a predetermined composition ratio. Yes.

  First, the effect of adding N atoms to an InGaAs crystal will be briefly described with reference to FIGS. 2 (a), 2 (b), 3 (a), and (b).

  FIG. 2A shows a band structure of InGaAs, and FIG. 2B shows a band structure of GaInNAs. 3A is an enlarged view showing the energy state at the Γ point in FIG. 2A, and FIG. 3B is an enlarged view showing the energy state at the Γ point in FIG. 2B. is there. 2A and 2B, the horizontal axis represents the position in the K space, and the vertical axis represents energy. 3A and 3B, the horizontal axis represents momentum, and the vertical axis represents energy.

2A and 2B are obtained by simulation. In the conventional example, an In _0.5 Ga _0.5 As crystal layer is formed on an InP substrate. In the present invention, a Ga layer is formed on an InP substrate. It is assumed that a _0.5 In _0.5 N _0.125 As _0.875 crystal layer has been formed.

In FIG. 2A, in the band structure of the conduction band 34 of the In _0.5 Ga _0.5 As crystal, the energy level at the Γ point is the lowest, and electrons travel through this Γ point. In FIG. 3A, in the case of bulk InGaAs, as indicated by a dotted line 41, energy has a relationship proportional to the square of momentum. In the case of a quantum well structure having an InGaAs layer as a well layer, the energy is quantized into a step-like band structure as shown by a thick solid line 42, as shown by a solid line 43 thinner than the overlap integral with the electron Fermi distribution 46. Take high electron density.

On the other hand, as shown in FIG. 2B, in the case of Ga _0.5 In _0.5 N _0.125 As _0.875 crystal, the energy state near the W point is flat, and the effect of adding nitrogen appears. Although the energy at the Γ point decreases due to the presence of the nitrogen level, the energy at the L point hardly decreases. From this, it can be seen that the energy difference _ΔΓL between the Γ point and the L point increases by adding nitrogen. As will be described later, it is known that the maximum value of the drift velocity of electrons increases as _ΔΓL increases, and there is a merit of adding nitrogen. However, as shown in FIG. 3B, when the vicinity of the Γ point is enlarged, the energy distribution 48 of the bulk GaInNAs deviates from the square relationship with respect to the momentum, and the amount of increase in energy decreases. End up. This is because a band 47 derived from a nitrogen atom is formed by adding a nitrogen atom, and as a result, mixing with the band 41 (see FIG. 3A) unique to InGaAs occurs. When band mixing occurs, as shown in FIG. 3B, the band 47 derived from nitrogen atoms and the band 41 inherent to InGaAs repel each other, so the band inherent to InGaAs is derived from nitrogen atoms. As the value approaches 47, the energy at the same momentum decreases. Even when the momentum is 0, the curvature of the energy distribution 48 of GaInNAs becomes large even if the momentum is 0 because the band 47 derived from nitrogen atoms and the band 41 inherent to InGaAs exist.

  As another viewpoint, the effect of adding nitrogen atoms will be described from the effective mass of electrons. An increase in the curvature of the band means an increase in the effective mass of the electrons. Since the energy momentum dependence of the band 47 derived from the nitrogen atom is linear, the curvature is large and the effective mass is It will be big. On the other hand, since the band inherent to InGaAs has a small curvature, the effective mass is also small. Therefore, when nitrogen atoms are added, a band of nitrogen atoms having a large effective mass is mixed in InGaAs, so that the effective mass of GaInNAs is larger than that of InGaAs, which means that the curvature of the energy distribution 48 of GaInNAs is increased. Is equivalent to

  Next, the influence on the electronic device due to the increase in the curvature of the band by adding nitrogen atoms will be described. When used as an electronic device having a heterostructure, since electrons are generally localized at the heterointerface between the spacer layer and the channel layer, the energy state is quantized to have a stepwise energy distribution. As a result, since the energy changes abruptly at the stepped shape, the state (state density) where electrons can exist in that portion increases. The larger the energy difference between the spacer layer and the channel layer and the smaller the effective mass, the smaller the number of steps. On the other hand, the Fermi distribution 46 indicates how much energy electrons can exist at room temperature. Taking the product of the Fermi distribution of electrons from the density of states where electrons can exist, the electron density at a specific energy is obtained. To increase the electron density, (1) reduce the band gap of the channel layer and increase the product with the Fermi distribution by bringing it closer to the Fermi level, and (2) reduce the energy difference of the staircase. There are three ways to increase the product with the Fermi distribution by bringing the higher-order quantum level closer to the Fermi level, and (3) increasing the effective mass to increase the state density itself. By adding nitrogen atoms to the channel layer, (1) the band gap decreases (addition of nitrogen to increase the amount of In for lattice matching by adding nitrogen atoms further reduces the band gap), (2) effective As the mass increases, the level difference decreases. (3) The effective density increases, so the density of states increases. From the results of adding nitrogen atoms, the electron density increases and a large electric field is applied. However, there is a merit that electrons do not easily overflow from the Γ point to the L point. This is extremely effective when the channel length is shortened and the operation speed becomes difficult to saturate or gun oscillation does not occur.

As described above, the addition of nitrogen atoms increases the effective mass and decreases the mobility, but has the advantage of increasing _{ΔΓL and} increasing the density of states. Therefore, we quantitatively evaluated how much of these effects can be expected. The results are shown in the table of FIG. This table shows the physical property values obtained in the study. By clarifying these physical property values, the hetero field effect transistor of the present invention can be realized and evaluated. FIG. 5 shows the result of calculating the electron velocity when an electric field is applied from the mobility (hole mobility) μ1 of the electron in a weak electric field and _ΔΓL . From this, the electron velocity increases as the electric field is applied, but even if an electric field equal to or higher than the point v _d at which the electron velocity is maximized is applied, the electron velocity is reduced. As shown in the leftmost part of FIG. 5, when the electric field is low, electrons are present at the Γ point where the effective mass is small and the mobility is high, so the electron velocity increases as the electric field is applied. When an electric field higher than that is applied, electrons overflow to the L point. At point L, since the effective mass m ^* is large and the mobility is small, the total mobility is lowered and the electron velocity is also lowered. FIG. 4 shows the maximum value of the electron velocity as v _d . As is apparent from FIG. 4, the maximum value of electron velocity v _d increases in the order of GaInNAs <GaAs <InP <InGaAs <InNAs <InAs. This is because _ΔΓL is larger in InP than in GaAs. This is because InGaAs and InAs are even larger by μ1. Here, in the case of GaInNAs, _ΔΓL is large, but μ1 becomes extremely small, so that the maximum value of electron velocity v _d falls below GaAs. On the other hand, in the case of InNAs, in order delta _GanmaL large although μ1 is reduced compared to InGaAs, resulting in _{InGaAs (v d = 3.96 × 10} 5 m / s) greater than v _d (= 4. 47 × 10 ⁵ m / s) is obtained. As a result, it has been found that by replacing the channel layer with an InNAs layer instead of an InGaAs layer, the electron velocity is increased and the operation speed is improved by about 20%.

  In other words, when the channel layer is replaced with an InGaAs layer and a GaInNAs layer is used, the electron velocity is reduced and the operating speed is reduced. Improve by about 20%. Therefore, it has been found that, when the channel layer is a GaInNAs layer having a Ga composition ratio in a certain range instead of the InGaAs layer, the electron velocity is increased and the operation speed is improved.

  Next, a preferable range of the composition ratio of Ga and N in this GaInNAs layer will be described.

FIG. 6 is a diagram showing a preferred range of the composition ratio of Ga and N (hereinafter also referred to as concentration (to be precise, atomic concentration)) in the GaInNAs quaternary compound constituting the channel layer of the present invention.

As shown in FIG. 6, as a result of the study by the present inventors, a region where the Ga concentration is in the range of 0% to 20% and the N concentration is in the range of 3% to 10% (hereinafter referred to as the region of the present invention) ) 63, it was found that a GaInNAs layer can be grown on the InP substrate without causing defects. In FIG. 6, reference numeral 61 indicates a straight line representing the relationship between the Ga composition and the N composition lattice-matched to InP. If the composition of the GaInNAs, expressed as _{Ga x In 1-x N y} As 1-y, this line becomes x = 0.47-6.7y. Conventionally, it is said that x = 0.47-3y, and the N concentration has been required to be about 15%, but a cluster is not formed based on the principle of mass spectrometry by filtering nitrogen ions with a magnetic field. By sorting the ions uniformly and supplying them to the substrate surface, the crystal growth temperature is set to an optimum temperature of 550 ° C., so that N atoms are uniformly dispersed in GaInAs, and lower N atoms It was found that the lattice matched to InP at the concentration. As a result, the phenomenon in which the N concentration locally increases and the band gap decreases is eliminated, and lattice matching and stable band shift are possible with a smaller N concentration. In particular, when the N concentration was 3% or more and 7% or less, compressive strain was generated in the channel layer, and hole mobility around 15000 cm ² / Vs was stably obtained. This is considered to be because when the Ga concentration is 20% or less, the effective mass of electrons decreases rapidly and the hole mobility increases. In the first embodiment to be described later, the channel layer is composed of InN _0.07 As _0.93 (composition of 1 in FIG. 6) having a composition lattice-matched to the InP substrate. However, the composition is within the range of the region 63 of the present invention. If so, a high hole mobility of 15000 cm ² / Vs or higher was obtained. The region 63 of the present invention is set so that the lattice strain is within ± 1.5% in order to make the channel layer thickness 10 nm or more.

To summarize the above description, the Ga and N composition ratio of GaInNAs constituting the channel layer of the present invention is such that the Ga concentration is in the range of 0% to 20% and the N concentration is in the range of 3% to 10%. Preferably there is. This is because when the Ga concentration is 20% or less, the effective mass of electrons is rapidly reduced and the hole mobility is increased. Further, when the N concentration is less than 3%, the operation speed is not improved sufficiently by increasing the electron velocity, and when the N concentration exceeds 10%, lattice mismatch with the InP substrate occurs. The N concentration is more preferably in the range of 3% to 7%. This is because, within this range, compressive strain is generated in the channel layer, and high (here, around 15000 cm ² / Vs) hole mobility can be stably obtained.

Hereinafter, embodiments embodying the concept of the present invention will be sequentially described.
( Reference Example 1 )
FIG. 1 is a cross-sectional view showing a configuration of a hetero field effect transistor according to Reference Example 1 of the present invention.

  As shown in FIG. 1, this hetero field effect transistor has an InP substrate 21. On the InP substrate 21, an InAlAs buffer layer 22, an InNAs channel layer 23, an InAlAs first spacer layer 25a, an n-InAlAs carrier supply layer 26, and an InAlAs second spacer layer 25b are sequentially stacked. An electrode 29a constituting a gate electrode is formed on the InAlAs second spacer layer 25b, and a pair of electrodes 29b and 29c constituting a source electrode and a drain electrode are formed at intervals on both sides of the electrode 29a. . The electrodes 29b and 29c are formed on the InAlAs second spacer layer 25b via the n-InGaAs contact layer 28.

  Next, a manufacturing method of the hetero field effect transistor configured as above will be described.

In this manufacturing method, a gas source MBE (Molecular Beam Epitaxy) method was used. The source gas is PH ₃ , AsH ₃ , N ₂ , In, Ga, or Si. N ₂ is supplied after being decomposed into N atoms by a plasma source. PH ₃ and AsH ₃ are supplied by being decomposed by heat. The temperature is raised to 550 ° C. while supplying PH ₃ , and an i-InAlAs buffer layer (film thickness 500 nm) 22, an InNAs channel layer (20 nm) 23, and an i-InAlAs spacer layer (5 nm) are formed on the semi-insulating InP substrate 21. 25a, n ⁺ -InAlAs carrier supply layer (10 nm, n-type impurity concentration n = 10 ¹⁹ cm ⁻³ ) 26, i-InAlAs spacer layer (20 nm) 25b, and n ⁺ -InGaAs contact layer (100 nm) 28 were grown. Thereafter, the contact layer 28 in the gate region was removed by etching, and electrode metals 29a, 29b, and 29c constituting the gate electrode, the source electrode, and the drain electrode were formed in predetermined regions by vapor deposition, respectively. The gate length was 0.2 μm and the gate width was 200 μm. As a result, the hole mobility when the InGaAs layer is formed on the InP substrate is 10000 cm ² / Vs, whereas in this reference example , the hole mobility is in the range of 12000 cm ² / Vs to 15000 cm ² / Vs. At the same time, the operating speed f _T of the hetero-field effect transistor is 200 GHz when the InGaAs layer is formed on the InP substrate, whereas in this reference example , the operating speed f _T is increased to a value in the range of 250 GHz to 300 GHz. I understood.
( Embodiment 1 )
FIG. 7 is a cross-sectional view showing the configuration of the hetero field effect transistor according to Embodiment 1 of the present invention. 7, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.

As shown in FIG. 7, in this embodiment, the channel layer is an InNAs layer 23 (thickness 10 nm) as a first channel layer and an InAs layer as a second channel layer formed on the InNAs layer 23. It is composed of two types of layers of 24 (4 nm). Other points are the same as in Reference Example 1 .

The reason for this configuration is that, as explained with reference to FIGS. 4 and 5 at the beginning, the InAs layer has a higher maximum electron velocity v _d than the InNAs layer. It is for use. More specifically, since the InAs channel layer 24 has a lattice mismatch of about 3% with respect to the InP substrate 21, it cannot be laminated to a thickness of 4 nm or more. When such a thin InAs layer is formed in the InGaAs layer as in the first conventional example, a transition from the Γ point to the L point occurs before carriers overflow into the InGaAs layer, resulting in a decrease in operating speed. There was a problem such as. However, when the InN _0.03 As _0.97 channel layer 23 (composition 2 in FIG. 6) having a slightly lower energy than the InAs channel layer 24 is formed adjacent to the InAs channel layer 24 as in the present embodiment, InAs is formed. It has been confirmed that the operating speed does not decrease because carriers overflow from the InAs channel layer 24 to the InNAs channel layer 23 before carriers localized in the channel layer 24 transition from the Γ point to the L point. Here, since the InNAs channel layer 23 is lower in energy by about 0.1 eV than the InAs channel layer 24, it can be considered that carriers travel preferentially in the InNAs channel layer 23. Since the band is bent as shown in FIG. 8A at the interface between the InAs channel layer 24 and the InAlAs spacer layer 25 because it is joined to the InAlAs spacer layer 25 having a large gap, electrons are transferred from the InAs channel layer 24 and the InAlAs spacer. It will be confined at the interface with the layer 25.

Furthermore, by inserting the InAs channel layer 24 between the InAlAs spacer layer 25 and the InNAs channel layer 23, the supply of Al atoms may be started after a while after the supply of N atoms is stopped even during crystal growth. As in Reference Example 1 , when the interface between the InAlAs spacer layer 25 and the InNAs channel layer 23 is formed, there is no situation in which Al atoms and N atoms are simultaneously supplied, so that a good interface is formed. The reason is that when Al and N are present at the same time, AlN, which is a high-resistance insulator, is formed, so that a large number of impurity levels are formed at the interface. This is probably because AlN is not formed because Al and N do not exist at the same time.

By the way, although the N concentration of InNAs is constant in Reference Example 1 and Embodiment 1 , the N concentration is reduced from the substrate side to the surface side in the InNAs channel layer in any embodiment (thickness direction). In FIG. 8B, the band structure as shown in FIG. 8B is obtained. In particular, in Embodiment 1 , carriers are unnecessarily removed from the InAs channel layer 24. The flow out to the InNAs channel layer 23 could be suppressed.

In the present embodiment, the carrier supply layer is formed of the δ-doped region 26 in which Si is added to InAlAs at 5 × 10 ¹² cm ⁻² per atomic layer. As a result, it was found that the hole mobility increased to 20000 cm ² / Vs, and the operating speed f _T of the hetero field effect transistor increased to 400 to 450 GHz.

As a modification of the present embodiment, as shown in FIG. 9, first and second carrier supply layers 26a and 26b made of a δ-doped region, and first and second spacer layers 25a and 25b made of InAlas, respectively. The first and second InAs channel layers 24a and 24b are formed on both sides of the InNAs channel layer 23 and the first and second InAs channel layers 24a and 24b. A channel structure may be employed. An InAlAs third spacer layer 25c is formed between the first carrier supply layer 26a and the InAlAs buffer layer 22, and an InAlAs fourth spacer layer 25d is formed on the second carrier supply layer 26b. In the case of this structure, since the amount of current flowing increases as the number of channels increases, high-speed operation of about 500 GHz is realized with a single gate up to a current range of about 500 mA. Further, by forming the pair of first and second InAs layers 24a and 24b so as to sandwich the InNAs layer 23, carriers overflowing from the first and second InAs layers 24a and 24b flow into the InNAs layer 23. It has been found that a channel is substantially formed also in the InNAs layer 23, and the resulting current also contributes to the increase in the amount of current.
( Embodiment 2 )
FIG. 10A is a cross-sectional view showing the configuration of the hetero field effect transistor according to Embodiment 2 of the present invention, and FIG. 10B is a diagram showing the energy state in the vicinity of the channel layer of FIG. 10A, the same reference numerals as those in FIG. 7 denote the same or corresponding parts.

As shown in FIG. 10A, in this embodiment, a GaInNAs channel layer 23 is formed as the first channel layer in place of the InNAs channel layer 23 of the first embodiment . The other points are the same as in the first embodiment .

In the first embodiment , since the first channel layer is the InNAs layer 23 to facilitate crystal growth, there is a concern that carriers overflow from the InAs layer 24 as shown in FIG. Therefore, in this embodiment, an attempt was made to increase the band gap by using the GaInNAs channel layer 23 in which Ga is added to InNAs instead of the InNAs channel layer 23.

In FIG. 6, energy contour lines 64 having the same energy gap as InAs are shown. In the region 63 of the present invention, the region where the energy is higher than the energy contour line 64, that is, the Ga concentration is three times or more of the N concentration (x ≧ 3y It was found that the energy of the GaInNAs layer is larger than the energy of the InAs layer. As a result, as shown in FIG. 10B, it is found that the overflow of carriers from the InAs channel layer 24 (hereinafter sometimes simply referred to as “InAs layer”) to the GaInNAs layer 23 is suppressed. It was. Further, the composition of the GaInNAs layer 23 is, for example, Ga _0.1 In _0.9 N _0.03 As _0.97 (composition of 3 in FIG. 6), and the Ga concentration is set to 0.1 or more, so that the single gate has a large value of about 600 mA. It was found that high-speed operation of about 500 GHz was realized up to the current range. The GaInNAs layer was formed to a thickness of 10 nm and the InAs layer was formed to a thickness of 4 nm.

  Next, a modification of the present embodiment will be described. As a first modification, instead of the GaInNAs channel layer 23, a GaInNAs / InAsMQW channel layer 23 is formed by alternately laminating 3 nm thick InAs layers and 3 nm thick GaInNAs layers. With such a configuration, a slightly better result than the above configuration was obtained. Therefore, a plurality of InAs layers can be stacked, and the range of design conditions is expanded.

In this case, if GaInNAs is a composition of Ga _0.1 In _0.9 N _0.03 As _0.97 (3 in FIG. 6), a compressive strain of 1% is introduced, but a composition of Ga _0.16 In _0.84 N _0.05 As _0.95 (FIG. 6), the same band gap as that of InAs can be obtained under the condition of lattice matching with InP.

Here, it is known that GaInNAs has a larger amount of change in the band of the conduction band than InAs. In order to make the band gap of the conduction band of GaInNAs and InAs the same, Ga _0.2 In _0.8 N _0.045 As _0.955 The composition (the composition of 5 in FIG. 6) was used. As a result, it was found that the bleeding of carriers into the GaInNAs layer was suppressed and the operation speed was improved by about 10%.

In this MQW channel layer 23, an InNAs layer having the following composition may be formed instead of the GaInNAs layer. That is, since compressive strain is introduced into the InAs layer, it is possible to stably stack a plurality of InAs channel layers by introducing tensile strain into the InNAs layer. As an InNAs layer, it was found that a laminated structure can be stably grown up to a composition of InN _0.1 As _0.9 (composition 6 in FIG. 6) into which 1% of compressive strain is introduced.

  As described above, even when the InAs layer and the GaInNAs layer are stacked and used, if the Ga concentration is 0 to 20% and the N concentration is in the range of 3% to 10%, the operation speed is improved. I was able to plan.

In the above embodiment, that is, in the channel layer composition shown in FIG. 6, the band gap is increased by adding Ga to InAsN. However, by adding P to InAsN, InAs _{1−y−xN y} P _z also increases the band gap. In the case of P, since it has the same dependence as Ga, it has been found that the P composition needs to be about three times the N concentration (z = 3y). Since the upper limit of the N concentration is 10% or less in InAs _1-yz N _y P _z , 0.03 <y <0.1 and 0 <z <0.3. In this case, when crystal growth is performed, it is necessary to completely remove P after the growth of the first channel layer. Therefore, there is a problem that the growth time becomes long. Because of the large change, the operating current can be increased slightly.

  In the composition of the GaInNAs channel layer shown in FIG. 6, As may be replaced with Sb. Since the mobility of InSb is higher than that of InAs, the HEMT can be speeded up. The GaInNSb channel layer is considered to be more effective than the GaInNAs layer.

  Further, as a second modification of the present embodiment, as shown in FIG. 11, the first and second carrier supply layers 26a and 26b configured by the δ-doped region are replaced with first and second spacer layers made of InAlas. A double layer in which the GaInAs channel layer 23 and the first and second InAs channel layers 24a and 24b are formed on both sides of the GaInNAs channel layer 23 through the first and second InAs channel layers 24a and 24b, respectively. A channel structure (that is, a structure in which the InNAs channel layer 23 is replaced with the GaInNAs channel layer 23 in the double channel structure of FIG. 9) can be employed.

In this case, it has been found that the amount of current flowing increases as the number of channels increases.
( Embodiment 3 )
FIG. 12 is a block diagram showing a configuration of a transmission / reception apparatus according to Embodiment 3 of the present invention.

This embodiment exemplifies a transmission / reception device using the hetero field effect transistor of Embodiments 1 and 2 .

  In FIG. 12, the transmitting / receiving device 302 is a wireless terminal here. The transmission / reception apparatus 302 includes an antenna 321, a reception amplification unit 312 that amplifies a reception radio wave signal from the antenna 321, a transmission amplification unit 313 that amplifies a transmission radio wave signal and transmits the signal to the antenna 321, and a reception amplification unit 312. A control unit 325 that extracts the reception signal from the reception radio signal from the signal and superimposes the transmission signal on a carrier wave to generate a transmission radio signal and sends it to the transmission amplification unit 313.

The hetero field effect transistors according to the first and second embodiments are used for the amplifiers of the reception amplification unit 312 and the transmission amplification unit 313. As described above, since this hetero field effect transistor can operate at a higher speed than the conventional example, the transmission / reception device 302 of this embodiment is also preferably used for a higher frequency (for example, a terahertz frequency band) than the conventional example. be able to. Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  The hetero field effect transistor according to the present invention is useful as a semiconductor element or the like used in a high frequency transmitting / receiving apparatus.

  Moreover, the method for producing a hetero field effect transistor according to the present invention is useful as a method for producing a semiconductor element or the like used in a high-frequency transmitting / receiving device.

  The transmission / reception apparatus according to the present invention is useful as a wireless terminal or the like.

It is sectional drawing which shows the structure of the hetero field effect transistor which concerns on the reference example 1 of this invention. FIG. 2A is a diagram showing a band structure of InGaAs, and FIG. 2B is a diagram showing a band structure of GaInNAs. 3A and 3B are diagrams showing energy states in the band structure of FIG. 2, in which FIG. 3A is an enlarged view showing the energy state at the Γ point in FIG. 2A, and FIG. 3B is FIG. It is a figure which expands and shows the energy state of Γ point. It is a table | surface which shows the physical-property value in the crystal body of various compound semiconductors. It is a figure which shows the relationship between the electron velocity and electric field in the crystal body of various compound semiconductors. It is a figure which shows the preferable range of the composition ratio of Ga and N in the GaInNAs quaternary compound which comprises the channel layer of this invention. It is sectional drawing which shows the structure of the hetero field effect transistor which concerns on Embodiment 1 of this invention. It is a figure which shows the energy state of the channel layer vicinity of the hetero field effect transistor of FIG. It is sectional drawing which shows the structure of the hetero field effect transistor which concerns on the modification of Embodiment 1 of this invention. It is a figure which shows the structure of the hetero field effect transistor which concerns on Embodiment 2 of this invention, Comprising: Fig.10 (a) is sectional drawing, FIG.10 (b) shows the energy state of the channel layer vicinity of Fig.10 (a). FIG. It is sectional drawing which shows the structure of the hetero field effect transistor which concerns on the 2nd modification of Embodiment 1 of this invention. It is a block diagram which shows the structure of the transmission / reception apparatus which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the hetero field effect transistor of a 1st prior art example. It is sectional drawing which shows the structure of the hetero field effect transistor of the 2nd prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electrode metal 2 InGaAs cap layer 3 InAlAs carrier supply layer 4 InAlAs spacer layer 5 InGaAs channel layer 6 InAlAs buffer layer 7 InP substrate 11 GaAs substrate 12 GaAs buffer layer 13 GaInNAs channel layer 14 AlGaAs carrier supply layer 16 AlGaAs spacer layer 18 Electrode metal 21 InP substrate 22 InAlAs buffer layer 23 InNAs channel layer, etc. 24 InAs channel layer 25 InAlAs spacer layer 26 n-InAlAS carrier supply layer, δ-doped region 28 n-InGaAs contact layer 29 Electrode 34 Conductive band 35 Fermi level 41 Energy and momentum 42 Energy states in quantum wells 43 Electron density 46 Fermi distribution 47 Nitrogen atoms in GaInNAs 48 According to the relationship between energy and momentum in GaInNAs 49 Energy states in quantum wells in GaInNAs 50 Electron density in GaInNAs 60 On GaAs substrate 61 On InP substrate 62 Nitrogen concentration dependence of band gap 63 Area of the present invention 302 Transceiver 321 Antenna 322 reception amplification unit 323 transmission amplification unit 325 control unit

Claims (11)

A substrate, a channel layer formed on the substrate via a buffer layer, a spacer layer formed of a semiconductor having a larger band gap than the channel layer, and formed to be heterojunction with the channel layer; and the spacer layer A carrier supply layer formed so as to be adjacent to
The substrate is made of InP;
Said channel layer is represented by the chemical formula _{Ga x In 1-x N y} A 1-y, wherein A is As or Sb, the composition x is 0 ≦ x ≦ 0.2, and the composition y is Having a compound semiconductor layer of 0.03 ≦ y ≦ 0.10
A is As,
The channel layer includes a first channel layer and a second channel layer adjacent to the first channel layer and heterojunction with the spacer layer, and the first channel layer includes the compound semiconductor layer. And the second channel layer is formed of an InAs layer .   The hetero field effect transistor of claim 1, wherein x = 0.   The hetero-field effect transistor according to claim 1, wherein the N concentration of the first channel layer decreases as the second channel layer is approached.   A pair of the second channel layers are formed adjacent to the upper surface and the lower surface of the first channel layer, and the pair of spacer layers are formed so as to be heterojunction with the pair of second channel layers, The hetero field effect transistor according to claim 1, wherein the pair of carrier supply layers are formed so as to be adjacent to the pair of spacer layers.   The hetero field effect transistor of claim 1, wherein 0 <x.   The hetero field effect transistor according to claim 5, further satisfying 3y ≦ x ≦ 0.2.   The hetero field effect transistor according to claim 5, wherein 0.1 ≦ x ≦ 0.2 is satisfied.   The said 1st channel layer is comprised by the GaInNAs / InAsMQW layer of the multiquantum well structure formed by alternately laminating the GaInNAs layer and InAs layer which are the said compound semiconductor layer of 0 <x. Hetero field effect transistor.   The said 1st channel layer is comprised by the InNAs / InAsMQW layer of the multiquantum well structure where the InNAs layer and InAs layer which are the said compound semiconductor layers of x = 0 are laminated | stacked alternately. Hetero field effect transistor. A channel layer forming step of forming a channel layer on a substrate via a buffer layer;
A spacer layer forming step of forming a spacer layer made of a semiconductor having a larger band gap than the channel layer so as to be heterojunction with the channel layer;
A carrier layer forming step of forming a carrier supply layer adjacent to the spacer layer,
The substrate is made of InP;
Said channel layer is represented by the chemical formula _{Ga x In 1-x N y} A 1-y, wherein A is As or Sb, the composition x is 0 ≦ x ≦ 0.2, and the composition y is 0.03 is ≦ y ≦ 0.10 compound have a semiconductive layer,
A buffer layer forming step of forming the buffer layer made of InAlAs on the InP substrate;
The channel layer forming step includes a first channel layer forming step of forming a first channel layer made of InNAs on the buffer layer, and a second channel layer made of InAs on the first channel layer. A second channel layer forming step of forming
The method for manufacturing a hetero field effect transistor, wherein, in the spacer layer forming step, the spacer layer made of InAlAs is formed on the second channel layer .   A transmission / reception apparatus comprising the hetero field effect transistor according to claim 1 for processing a transmission signal or a reception signal.

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